CS61535A-IL1 Cirrus Logic, Inc., CS61535A-IL1 Datasheet

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CS61535A-IL1

Manufacturer Part Number
CS61535A-IL1
Description
E1 line interface unit
Manufacturer
Cirrus Logic, Inc.
Datasheet

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Features
[TCODE]
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
[RDATA]
[TDATA]
RNEG
RPOS
TNEG
TPOS
RCLK
TCLK
[BPV]
Provides Analog PCM Line Interface
for T1 and E1 Applications
Provides Line Driver, and Data and
Clock Recovery Functions
Transmit Side Jitter Attenuation
Starting at 6 Hz, with > 300 UI of Jitter
Tolerance
Low Power Consumption
(typically 175 mW)
B8ZS/HDB3/AMI Encoders/Decoders
14 dB of Transmitter Return Loss
Compatible with SONET, M13 , CCITT
G.742, and Other Asynchronous
Muxes
[ ] = Pin Function in Extended Hardware Mode
( ) = Pin Function in Host Mode
2
3
4
8
7
6
CODER
B8ZS,
HDB3
AMI,
RLOOP
(CS)
26
LOOP
BACK
LLOOP
(SCLK)
27
T1/E1 Line Interface
XTALIN
ATTENUATOR
9
JITTER
XTALOUT
10
Copyright
MODE
General Description
The CS61535A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
The device features a transmitter jitter attenuator mak-
ing it ideal for use in asynchronous multiplexor systems
with gapped transmit clocks. The CS61535A provides a
matched, constant impedance output stage to insure
signal quality on mismatched, poorly terminated lines.
Both ICs use a digital Delay-Locked-Loop clock and
data recovery circuit which is continuously calibrated
from a crystal reference to provide excellent stability
and jitter tolerance.
Applications
Ordering Information
CS61535A-IP1
CS61535A-IL1
5
ACLKI
CONTROL
Crystal Semiconductor Corporation 1996
Interfacing network transmission equipment such as
SONET multiplexor and M13 to a DSX-1 cross connect.
Interfacing customer premises equipment to a CSU.
Interfacing to E1 links.
(CLKE)
TAOS
1
(All Rights Reserved)
RECOVERY
CLOCK &
28
DATA
LOS
MONITOR
QUALITY
SIGNAL
LEN0
(INT)
12
23
LEN1
(SDI)
SHAPER
28 Pin Plastic DIP
28 Pin PLCC (j-leads)
PULSE
RV+
24
21
(SDO)
LEN2
RGND
CS61535A
25
22
LINE RECEIVER
TGND
LINE DRIVER
MONITOR
DRIVER
14
TV+
15
13
16
11
19
20
17
18
MAY ’96
DS40F2
TTIP
TRING
RTIP
RRING
MTIP
[RCODE]
MRING
[PCS]
DPM
[AIS]
1

Related parts for CS61535A-IL1

CS61535A-IL1 Summary of contents

Page 1

... Applications Interfacing network transmission equipment such as SONET multiplexor and M13 to a DSX-1 cross connect. Interfacing customer premises equipment to a CSU. Interfacing to E1 links. Ordering Information CS61535A-IP1 CS61535A-IL1 (CLKE) XTALIN XTALOUT MODE TAOS ...

Page 2

... Symbol Min RV+ - TV+ - (Note 1) V RGND-0.3 in (Note -65 stg Symbol Min (Note 3) RV+, TV+ 4.75 T -40 A (Notes (Notes CS61535A Max Units 6.0 V (RV+) + 0.3 V (RV 150 C Typ Max Units 5.0 5. 290 350 mW 175 - mW DS40F2 ...

Page 3

... Notes: 7. This specification guarantees TTL compatibility ( Host Mode, pin open drain output and pin tristate output. 9. Pins 17 and 18 of the CS61535A are digital inputs in the Extended Hardware Mode. 10. Output drivers will drive CMOS logic levels into a CMOS load. ...

Page 4

... MHz to 3.072 MHz Transmitter Short Circuit Current Notes: 16. Using a 0.47 F capacitor in series with the primary of a transformer recommended in the Applications Section. 17. Amplitude measured at the transformer (CS61535A-1:1 or 1:1.26) output across a 75 load for line length setting LEN2/1/0 = 0/0/0. 18. Amplitude measured at the transformer (CS61535A-1:1.26) output across a 120 load for line length setting LEN2/1/0 = 0/0/0 ...

Page 5

... TV+, RV+ = 5.0V 5%; GND = 0V) Min - - -13.6 60 (Note 24) (Note 25 (Note 26 160 (Note 27) 0.4 6.0 300 (Note 28) 0. 1.2 V and from CS61535A Typ Max Units 0. 50k - - - peak peak peak peak peak 175 190 bits - - ...

Page 6

... The maximum gap size that can pw2 t pw1 t pwl1 t pwh1 t t su1 h1 CS61535A Min Typ Max - 6.176000 pw3 - 1.544 / pw1 - 29 320 648 980 ...

Page 7

... Figure 2. Signal Rise and Fall Characteristics t h2 ACLKI Figure 3b. Alternate External Clock Characteristics CS61535A Min Typ Max f - 8.192000 pw3 - 2.048 / pw1 310 ...

Page 8

... C; TV+, RV+ = 5%; Symbol cdh (Note 38) t cch t cwh (Note 39) t cdv t cdz t su4 pcsl t cl LSB BYTE DATA Figure 4. Serial Port Write Timing Diagram CS61535A Min Typ Max 240 - - 240 - - - - 250 - - - - 200 - 100 - 50 ...

Page 9

... CS SCLK t SDO CLKE = 1 LEN0/1/2, TAOS, RLOOP, LLOOP, RCODE, TCODE Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram DS40F2 cdv Figure 5. Serial Port Read Timing Diagram PCS t su4 t pcsl VALID INPUT DATA CS61535A t cdz HIGH ...

Page 10

... Table 1. Differences in Operating Modes 10 as shown in Tables 1 and 2, Figure 7, and Figures A1-A3 of the Applications section. The CS61535A modes are Hardware Mode, Ex- tended Hardware Mode, and Host Mode. In Hardware and Extended Hardware Modes, discrete pins are used to configure and monitor the device. The Extended Hardware Mode provides a parallel ...

Page 11

... AMI CS61535A AIS LINE RECEIVER DETECT AIS HOST MODE CLKE CONTROL JITTER LINE DRIVER ATTENUATOR CS61535A DRIVER MONITOR LINE RECEIVER Figure 7. Overview of Operating Modes CS61535A TTIP TRANSMIT TRING TRANSFORMER MRING MTIP DPM RTIP RECEIVE RRING TRANSFORMER LEN0/1/2 TTIP TRANSMIT TRING TRANSFORMER ...

Page 12

... ANSI T1.403 Table 3. Line Length Selection CS61535A line driver is designed to drive a 75 equivalent load. For T1 DSX-1 applications, line lengths from 0 to 655 feet (as measured from the transmitter to the DSX-1 cross connect) are selectable. The five partition arrangement meets ANSI T1.102-1993 requirements when using ABAM cable ...

Page 13

... As this frequency deviation becomes large, the maximum jitter tolerance at high frequencies is reduced before the underflow/overflow circuitry is activated. In ap- plication unlikely that the oscillator center frequency will be precisely aligned with the CS61535A a) Minimum Attenuation Limit AT&T 62411 Requirements Measured Performance 10 ...

Page 14

... Detector Selector Continuously Calibrated Delay Line Figure 11. Receiver Block Diagram not available on the CS61535A when ACLKI is grounded. Receiver The receiver extracts data and clock from an AMI (Alternate Mark Inversion) coded signal and out- puts clock and synchronized data. The receiver is sensitive to signals over the entire range of cable lengths and requires no equalization or ALBO (Automatic Line Build Out) circuits ...

Page 15

... RCLK jitter with an amplitude of 1/13 UIpp. These single phase jumps are due to differences in frequency of the incoming data and the calibration clock input to ACLKI. For T1 operation of the CS61535A, the instantaneous period can be 14/13 * 648 ns = 698 ns (1,662,769 Hz) or 12/13 * 648 ns = 598 ns (1,425,231 Hz) when adjacent clock phases are chosen ...

Page 16

... Theoretically, this would give a jitter tolerance of 0.46 UI. The ac- tual jitter tolerance of the CS61535A is only slightly less than the ideal. In the event of a maximum jitter hit, the RCLK clock period immediately adjusts to align itself ...

Page 17

... PCS low period. The control inputs are ignored when PCS is high. Power On Reset / Reset Upon power-up, the CS61535A is held in a static state until the supply crosses a threshold of ap- CS61535A LEN 2/1/0 ...

Page 18

... SCLK. For CLKE = 1, data bit D7 is held to the falling edge of the 16th clock cycle; for CLKE = 0, data bit D7 is held to the rising edge of the 17th clock cycle. SDO goes to a high LSB, first bit Table 7. Address/Command Byte CS61535A ...

Page 19

... The first bit of the ad- dress/command byte determines whether a read or a write is requested. The next six bits contain the address. The CS61535A responds to address 16 (0010000). The last bit is ignored. The data register, shown in Table 8, can be writ- ten to the serial port. Data is input on the eight clock cycles immediately following the ad- dress/command byte ...

Page 20

... Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering CS61535A DS40F2 ...

Page 21

... LOS MTIP 12 17 TTIP TRING 13 16 TGND TV top 8 view DPM LOS TTIP CS61535A TAOS LLOOP RLOOP LEN2 25 LEN1 24 LEN0 23 22 RGND 21 RV RRING RTIP MRING MTIP TRING TV+ 21 ...

Page 22

... LOS RCODE 12 17 TTIP TRING 13 16 TGND TV BPV top 8 view AIS LOS TTIP CS61535A TAOS LLOOP RLOOP LEN2 25 LEN1 24 LEN0 23 22 RGND 21 RV RRING RTIP PCS RCODE TRING TV+ DS40F1 ...

Page 23

... MRING 11 18 LOS MTIP 12 17 TTIP TRING 13 16 TGND TV top 8 view DPM LOS TTIP CS61535A CLKE SCLK CS SDO 25 SDI 24 INT 23 22 RGND 21 RV RRING RTIP MRING MTIP TRING TV+ 23 ...

Page 24

... Control ACLKI - Alternate External Clock Input, Pin 1. The CS61535A does not require a clock signal to be input on ACLKI when a crystal is connected between pins 9 and 10 clock is not provided on ACLKI, this input must be grounded. If ACLKI is grounded, the oscillator in the jitter attenuator is used to calibrate the clock recovery circuit and TAOS is not available ...

Page 25

... Inputs on RTIP and RRING are ignored. MODE - Mode Select, Pin 5. Driving the MODE pin high puts the CS61535A line interface in the Host Mode. In the host mode, a serial control port is used to control the CS61535A line interface and determine its status. Grounding the MODE pin puts the CS61535A line interface in the Hardware Mode, where configuration and status are controlled by discrete pins ...

Page 26

... TNEG input causes a negative pulse to be transmitted. TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. In the CS61535A, this output is designed to drive a 75 load. A 1:1, 1:1.15 or 1:1.26 transformer is required as shown in Figure A1. ...

Page 27

... MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) These pins are normally connected to TTIP and TRING and monitor the output of a CS61535A. If the INT pin in the host mode is used, and the monitor is not used, writing "Clear DPM" to the serial interface will prevent an interrupt from the driver performance monitor ...

Page 28

... DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. B D2/ pin E1 Plastic DIP 28-pin PLCC MILLIMETERS E E1 DIM MIN A 4.20 A1 2.29 B 0.33 D/E 12.32 D1/E1 11.43 D1 D2/ CS61535A MILLIMETERS INCHES DIM MIN NOM MAX MIN 3.94 4.32 A 5.08 0.155 A1 0.51 0.76 1.02 0.020 B 0.36 0.46 0.56 0.014 B1 1.02 1.27 1.65 0.040 C 0.20 0.25 0.38 0.008 36.45 36.83 D 37.21 1.435 E1 13.72 13 ...

Page 29

... The blocking capacitor will keep DC current from flowing in the transformer. Selecting an Oscillator Crystal Specific crystal parameters are required for proper operation of the CS61535A recom- mended that the CXT6176 from Crystal CS61535A +5V 100 k ...

Page 30

... IN LOS 11 EXTENDED AIS HARDWARE 5 MODE MODE 20 4 RRING TCODE 7 RDATA 8 RCLK 3 TDATA 16 TRING 2 TCLK 13 TTIP 9 XTALIN 10 XTALOUT RGND TGND 22 14 CS61535A Line Length Setting CT 2:1 R1 RECEIVE LINE R2 0.47 F TRANSMIT LINE Line Length Setting CT 2:1 R1 RECEIVE LINE R2 0.47 F TRANSMIT LINE DS40F2 ...

Page 31

... CS61535A RCLK duty cycle and instantaneous frequency vary with received jitter and may ex- hibit 1/13 UIpp quantization jitter even when the incoming signal is jitter free. 5) The CS61535A requires setup time on TPOS and TNEG before the falling edge of TCLK and hold time on these inputs af- CS61535A ...

Page 32

... CS61534. Using the CS61535A for SONET The CS61535A can be applied to SONET VT1.5 and VT2.0 interface circuits as shown in Fig- ure A5. The SONET data rate is 51.84 MHz, and has 6480 bits per frame (125 us per frame). An individual T1 frame (193 bits per frame) or PCM- 51 ...

Page 33

... CS61535A. Refer to the "Telecom Trans- former Selection Guide" for detailed schematics which show how to connect the line interface IC with a particular transformer. In applications with the CS61535A where it is ad- vantageous to use a single transmitter transformer for both 75 transforer may be used. Although transmitter re- ...

Page 34

... RX &TX: 1:2CT T1 1:1.15 RX &TX: 1:2CT 1:1.26 E1 (75 & 120 1 1:2CT T1 & E1 TX: 1:1.26 1:1 E1 (75 & 120 ) Table A3. Recommended Transformers For The CS61535A 34 Manufacturer Part Number Pulse Engineering PE-65351 Schott 67129300 Bel Fuse 0553-0013-HC Pulse Engineering PE-65388 Schott 67129310 Bel Fuse 0553-0013-RC Pulse Engineering ...

Page 35

... I/O. Two LED indicators monitor de- vice alarm conditions. The board supports all line interface operating modes. ORDERING INFORMATION: CDB61534, CDB6158, CDB61574A, CDB61575, CDB61304A, CDB61305A +5V 0V Reset Circuit CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A or CS61305A coax E1, or 120 twisted-pair E1 operation. CDB61535. CDB61535A, ...

Page 36

... Mode selection is accomplished with slide switch SW1 and jump- ers JP2, JP6, and JP7. The CS61535A, CS61574A, CS61575, CS61577, CS61304A, and CS61305A support the Hardware, Extended Hardware, and Host operating modes. The CS61534, CS61535, and CS61574 support the Hardware and Host operating modes ...

Page 37

... Table 2) R2 4.4 (Used only for E1 75 LOS applications with the CS61534, 12 CS61535, CS6158, CS61574, RV+ OR CS61577) LOS Q2 Q1 2N2222 2N2222 U1: CS61534, CS61535, LED LED CS61535A, CS6158 CS6158A, CS61574 CS61574A, CS61575, 470 470 CS61577, CS61304A, OR CS61305A RV+ T2 RTIP 2:1 RRING TTIP JP5 E ...

Page 38

Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Extended Hardware Mode In the Extended Hardware operating mode, the line interface is configured using DIP switch S2. The digital control ...

Page 39

The evaluation board supports 100 T1, 75 coax E1, and 120 eration. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The ...

Page 40

A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match ...

Page 41

TRANSFORMER 1,2 (Turns Ratio) PE-65351 (1:2CT) Schott 12930 (1:2CT) PE-65388 (1:1.15) Schott 12931 (1:1.15) PE-65389 (1:1:1.26) Schott 12932 (1:1:1.26) PE-64951 (dual 1:2CT) Schott 11509 (dual 1:2CT) PE-65565 (dual 1:1.15 & 1:2CT) Schott 12531 (dual 1:1.15 & 1:2CT) PE-65566 (dual 1:1:1.26 ...

Page 42

Figure 2. Silk Screen Layer (NOT TO SCALE) LINE INTERFACE EVALUATION BOARD DS40DB3 ...

Page 43

Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS40DB3 LINE INTERFACE EVALUATION BOARD 43 ...

Page 44

Figure 4. Bottom Trace Layer (NOT TO SCALE) 44 LINE INTERFACE EVALUATION BOARD DS40DB3 ...

Page 45

Notes • ...

Page 46

Notes • ...

Page 47

Notes • ...

Page 48

TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...

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