CY7C1041BL-15ZXC Cypress Semiconductor Corporation., CY7C1041BL-15ZXC Datasheet

no-image

CY7C1041BL-15ZXC

Manufacturer Part Number
CY7C1041BL-15ZXC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05142 Rev. *A
Features
Functional Description
The CY7C1041B is a high-performance CMOS static RAM
organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
• High speed
• Low active power
• Low CMOS standby power (L version)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
A
A
A
A
A
A
A
A
A
Logic Block Diagram
0
1
2
3
4
5
6
7
8
— t
— 1540 mW (max.)
— 2.75 mW (max.)
AA
= 12 ns
INPUT BUFFER
1024 x 4096
DECODER
COLUMN
256K x 16
ARRAY
3901 North First Street
I/O
I/O
0
8
–I/O
–I/O
BHE
WE
CE
OE
BLE
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041B is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
7
15
17
). If Byte High Enable (BHE) is LOW, then data
San Jose
8
256K x 16 Static RAM
through I/O
Pin Configuration
0
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
V
WE
CE
CC
A
A
A
A
A
A
A
A
A
A
SS
to I/O
,
0
1
2
3
4
0
1
2
3
4
5
6
7
5
6
7
8
9
CA 95134
0
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
Top View
through I/O
TSOP II
7
. If Byte High Enable (BHE) is
15
SOJ
0
) is written into the location
through A
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Revised March 24, 2005
NC
15
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
A
A
A
A
A
CY7C1041B
SS
CC
17
16
15
14
13
12
11
10
) are placed in a
0
15
14
13
12
11
10
9
8
17
through I/O
).
408-943-2600
8
to I/O
15
. See
7
), is
0
[+] Feedback

Related parts for CY7C1041BL-15ZXC

CY7C1041BL-15ZXC Summary of contents

Page 1

Features • High speed — • Low active power — 1540 mW (max.) • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic ...

Page 2

Selection Guide Maximum Access Time Maximum Operating Current Com’l Ind’l Maximum CMOS Standby Com’l Current Com’l Ind’l Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient ...

Page 3

Electrical Characteristics Over the Operating Range (continued) Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH [1] V Input LOW Voltage IL I Input Load Current IX I Output Leakage OZ Current ...

Page 4

Switching Characteristics [4] Over the Operating Range Parameter Description Read Cycle t V (typical) to the First Access power CC t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE ...

Page 5

Switching Characteristics Over the Operating Range (continued) Parameter Description Read Cycle t V (typical) to the First Access power CC t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t ...

Page 6

Data Retention Waveform Switching Waveforms [12, 13] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [13, 14] Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE OE t BHE, BLE t LZOE t DBE ...

Page 7

Switching Waveforms (continued) [15, 16] Write Cycle No. 1 (CE Controlled) ADDRESS BHE, BLE DATAI/O Write Cycle No. 2 (BLE or BHE Controlled) ADDRESS t SA BHE, BLE WE CE DATAI/O Notes: 15. Data I/O is ...

Page 8

Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS BHE, BLE DATA I/O Truth Table BLE BHE High Data ...

Page 9

... Ordering Information Speed (ns) Ordering Code 12 CY7C1041B-12VC CY7C1041B-12VXC CY7C1041B-12ZC CY7C1041B-12ZXC 15 CY7C1041B-15VC CY7C1041B-15VXC CY7C1041BL-15VC CY7C1041B-15ZC CY7C1041B-15ZXC CY7C1041BL-15ZC CY7C1041BL-15ZXC 17 CY7C1041B-17VC CY7C1041BL-17VC CY7C1041B-17ZC CY7C1041BL-17ZC 20 CY7C1041B-20VC CY7C1041B-20VXC CY7C1041BL-20VC CY7C1041BL-20VXC CY7C1041B-20ZC CY7C1041B-20ZXC CY7C1041BL-20ZC 25 CY7C1041B-25VC CY7C1041BL-25VC CY7C1041B-25ZC CY7C1041BL-25ZC 15 CY7C1041B-15ZI CY7C1041B-15ZXI CY7C1041B-15VI CY7C1041B-15VXI 17 CY7C1041B-17ZI CY7C1041B-17VI 20 CY7C1041B-20ZI CY7C1041B-20ZXI CY7C1041B-20VI CY7C1041B-20VXI ...

Page 10

Package Diagrams All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05142 Rev. *A © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress ...

Page 11

Document History Page Document Title: CY7C1041B 256K x 16 Static RAM Document Number: 38-05142 Issue Orig. of REV. ECN NO. Date Change ** 109886 09/15/01 SZV *A 341401 See ECN AJU Document #: 38-05142 Rev. *A Description of Change Change ...

Related keywords