E28F320J3A-110 Intel Corporation, E28F320J3A-110 Datasheet
E28F320J3A-110
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E28F320J3A-110 Summary of contents
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Volt Intel StrataFlash™ Memory 28F128J3A, 28F640J3A, 28F320J3A (x8/x16) Product Features High-Density Symmetrically-Blocked Architecture — 128 128-Kbyte Erase Blocks (128 M) — 4 128-Kbyte Erase Blocks (64 M) — 32 128-Kbyte Erase Blocks (32 M) High Performance Interface Asynchronous ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1999–2001 *Other names and brands may be claimed as the property of others. Preliminary ...
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Contents 1.0 Product Overview 2.0 Principles of Operation 2.1 Data Protection...................................................................................................... 6 3.0 Bus Operations 3.1 Read...................................................................................................................... 8 3.2 Output Disable....................................................................................................... 8 3.3 Standby ................................................................................................................. 8 3.4 Reset/Power-Down ............................................................................................... 8 3.5 Read Query ........................................................................................................... 9 3.6 Read Identifier Codes............................................................................................ 9 ...
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Buffers or Transceivers39 5.5 VCC, VPEN, RP# Transitions ............................................................................. 39 5.6 Power-Up/Down Protection................................................................................. 39 5.7 Power Dissipation ............................................................................................... 40 6.0 Electrical Specifications 6.1 Absolute Maximum Ratings ................................................................................ 40 6.2 Operating Conditions .......................................................................................... 41 6.3 Capacitance ........................................................................................................ 41 ...
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Revision History Date of Revision 07/07/99 08/03/99 09/07/99 12/16/99 03/16/00 06/26/00 2/15/01 04/13/01 Preliminary 28F128J3A, 28F640J3A, 28F320J3A Version -001 Original Version -002 A –A indicated on block diagram 0 2 -003 Changed Minimum Block Erase time,I Mode currents. Modified RP# ...
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Product Overview The 0.25 µ 3 Volt Intel StrataFlash memory family contains high-density memories organized as 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be ...
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Additionally, the configuration command allows the STS pin to be configured to pulse on completion of programming and/or block erases. Three ...
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Table 1. Lead Descriptions Symbol Type BYTE-SELECT ADDRESS: Selects between high and low byte when the device mode. This A INPUT address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A ...
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Figure 2. 3 Volt Intel StrataFlash™ Memory Easy BGA Package GND ...
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Figure 3. 3 Volt Intel StrataFlash™ Memory 56-Lead TSOP (32/64/128 Mbit) Offers an Easy Migration from the 32-Mbit Intel StrataFlash Component (28F320J5) or the 16-Mbit FlashFile™ Component (28F160S3) 3 Volt Intel StrataFlash Memory 28F160S3 28F320J5 32/64/128M ( ...
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Principles of Operation The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program, and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power supplies during block erasure, program, lock-bit ...
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Bus Operations The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Figure 4. Memory Map A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: ...
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Read Information can be read from any block, query, identifier codes, or status register independent of the V voltage. PEN Upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read ...
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As with any automated device important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, ...
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Figure 5. Device Identifier Code Memory Map NOTE not used in either x8 or x16 modes when obtaining these identifier codes. Data is always given on the low byte in 0 x16 mode (upper byte ...
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Table 3. Bus Operations Mode Notes RP# Read Array 4,5 Output Disable V IH Standby V IH Reset/Power-Down V Mode Read Identifier Codes V IH Read Query V IH Read Status (WSM off Read Status (WSM ...
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Table 4. Intel StrataFlash™ Memory Command Set Definitions Scalable or Basic Command Command (2) Set Read Array SCS/BCS Read Identifier Codes SCS/BCS Read Query SCS Read Status Register SCS/BCS Clear Status Register SCS/BCS Write to Buffer ...
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Write Buffer = where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H 1FH and for word ...
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In all of the following tables, addresses and data are represented in hexadecimal notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always “00h,” the leading “00” has ...
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Table 7. Query Structure Offset 00h 01h (BA+2)h (2) Block Status Register 04-0Fh Reserved 10h CFI Query Identification String 1Bh System Interface Information 27h Device Geometry Definition Primary Intel-Specific Extended (3) P Query Table NOTES: 1. Refer to the ...
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Table 9. CFI Identification Offset Length 17h 2 Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists 19h 2 Secondary algorithm Extended Query Table address. 0000h means none exists 4.2.5 ...
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Device Geometry Definition This field provides critical details of the flash device geometry. Table 11. Device Geometry Definition Offset Length 27h 1 “n” such that device size = 2 28h 2 Flash device interface: x8 async x16 async x8/x16 ...
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Primary-Vendor Specific Extended Query Table Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information. Table 12. Primary Vendor-Specific Extended Query (1) Offset Length P = 31h ...
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Table 13. Protection Register Information (1) Offset Length P = 31h (P+E)h 1 (P+F)h (P+10)h 4 (P+11)h (P+12)h NOTE: 1. The variable pointer which is defined at CFI offset 15h. Table 14. Burst Read Information (1) Offset ...
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Table 15. Identifier Codes Code Manufacture Code Device Code Block Lock Configuration Block Is Unlocked Block Is Locked Reserved for Future Use NOTES not used in either x8 or x16 modes when obtaining the ...
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Table 16. Status Register Definitions WSMS ESS ECLBS bit 7 bit 6 bit 5 High Z When Status Register Bits Busy? SR.7 = WRITE STATE MACHINE STATUS Ready 0 = Busy Yes SR.6 = ERASE SUSPEND STATUS ...
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Clear Status Register Command Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions ...
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Program Resume command allows continuing of the suspended programming operation. To resume the suspended erase, the user must wait for the programming operation to complete before issuing the Block Erase Resume command. The only other valid commands while ...
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Byte/Word Program Commands Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 40H or alternate 10H) is written followed by a second write that specifies the address and data (latched on the ...
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Read Configuration The device will support both asynchronous page mode and standard word/byte reads. No configuration is required. Status register and identifier only support standard word/byte single read operations. Table 18. Read Configuration Register Definition ...
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Table 19. Configuration Coding Definitions Reserved 7– STS Pin Configuration Codes 1– default, level mode RY/BY# (device ready) indication 01 = pulse on Erase complete 10 = ...
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Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock- bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while the WSM is ...
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The allowable addresses are shown in Table 20 on page 37 Any attempt to address Protection Program commands outside the defined protection register address space ...
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Table 20. Word-Wide Protection Register Addressing Word Use LOCK Both 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User NOTE: 1. All address lines not specified in the above table must be 0 ...
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Figure 7. Write to Buffer Flowchart Start Set Time-Out Issue Write to Buffer Command E8H, Block Address Read Extended Status Register XSR.7 = Write Word or Byte Count, Block Address Write Buffer Data, Start Address X = ...
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Figure 8. Byte/Word Program Flowchart Start Write 40H, Address Write Data and Address Read Status Register SR Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR ...
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Figure 9. Program Suspend/Resume Flowchart Start Write B0H Read Status Register SR SR Write FFH Read Data Array Done Reading Yes Write D0H Programming Resumed 32 Bus Operation Write Read Standby Standby 0 ...
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Figure 10. Block Erase Flowchart Start Issue Single Block Erase Command 20H, Block Address Write Confirm D0H Block Address Read Status Register SR Full Status Check if Desired Erase Flash Block(s) Complete Preliminary 28F128J3A, 28F640J3A, 28F320J3A Bus Operation ...
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Figure 11. Block Erase Suspend/Resume Flowchart Start Write B0H Read Status Register SR.7 = SR.6 = Read Read or Program? Read Array Data Done? Write D0H Block Erase Resumed 34 Bus Operation Write Read Standby Standby 0 ...
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Figure 12. Set Block Lock-Bit Flowchart Start Write 60H, Block Address Write 01H, Block Address Read Status Register SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 ...
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Figure 13. Clear Lock-Bit Flowchart Start Write 60H Write D0H Read Status Register SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 = ...
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Figure 14. Protection Register Programming Flowchart Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See ...
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Design Considerations 5.1 Three-Line Output Control The device will often be used in large memory arrays. Intel provides five control inputs ( OE#, and RP#) to accommodate multiple memory connections. This control provides for: ...
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Input Signal Transitions - Reducing Overshoots and Undershoots When Using Buffers or Transceivers As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory devices, overshoots and undershoots can sometimes cause input signals to exceed ...
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Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is ...
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Operating Conditions Table 22. Temperature and V Symbol Parameter T Operating Temperature Supply Voltage (2.7 V 3.6 V) CC1 CC1 V V Supply Voltage (3.0 V 3.6 V) CC2 CC2 V V Supply Voltage (2.7 V ...
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DC Characteristics Symbol Parameter I Input and V Load Current LI PEN I Output Leakage Current LO I Output Leakage Current Standby Current CCS Power-Down Current CCD ...
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DC Characteristics, Continued Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V Lockout during Program, PEN V PENLK Erase and Lock-Bit Operations V during Block Erase, ...
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Figure 16. Transient Equivalent Testing Load Circuit NOTE: C Includes Jig Capacitance L Test Configuration 3.0 V 3.6 V CCQ 2.7 V 3.6 V CCQ CC 44 1.3V ...
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AC Characteristics— Read-Only Operations Versions (All units in ns unless otherwise noted) # Sym Parameter R1 t Read/Write Cycle Time AVAV R2 t Address to Output Delay AVQV Output Delay X ELQV R4 t OE# ...
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Figure 17. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations ADDRESSES [ ADDRESSES [ Disabled (V CE [E] X Enabled (V OE# [G] WE# [W] DATA [D/ ...
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AC Characteristics— Write Operations # Symbol RP# High Recovery to WE# (CE PHWL PHEL (WE#) Low to WE# (CE ELWL WLEL Write Pulse Width ...
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Block Erase, Program, and Lock-Bit Configuration Performance # Sym Write Buffer Byte Program Time W16 (Time to Program 32 bytes/16 words) t Byte Program Time (Using Word/Byte Program WHQV3 W16 t Command) EHQV3 Block Program Time ...
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Figure 18. AC Waveform for Write Operations ADDRESSES [A] Disabled ( (WE#) [E(W)] X Enabled (V OE# [G] Disabled (V WE#, (CE ) [W(E)] X Enabled (V DATA [D/Q] STS [R] RP# [ PENLK V [V] ...
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Figure 19. AC Waveform for Reset Operation V STS ( RP# (P) V NOTE: STS is shown in its default mode (RY/BY#). Reset Specifications # Sym RP# Pulse Low Time P1 t (If RP# is ...
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... These speeds are for either the standard asynchronous read access times or for the first access of a page- mode read sequence. VALID COMBINATIONS 56-Lead TSOP E28F128J3A-150 E28F640J3A-120 E28F320J3A-110 Preliminary 28F128J3A, 28F640J3A, 28F320J3A Access Speed (ns) ...
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Additional Information Order Number 298130 290668 292237 Note 3 290606 290608 290609 290429 290598 290597 297859 292222 292221 292218 292205 292204 292202 298161 Note 4 NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 ...