HY57V641620HGT-S Hynix Semiconductor, HY57V641620HGT-S Datasheet
HY57V641620HGT-S
Manufacturer Part Number
HY57V641620HGT-S
Description
4 banks x 1M x 16Bit synchronous DRAM, 3.3V, LVTTL, 100 MHz
Manufacturer
Hynix Semiconductor
Datasheet
1.HY57V641620HGT-S.pdf
(12 pages)
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.5/Jun.01
DESCRIPTION
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
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•
•
•
•
•
O R D E R I N G I N F O R M A T I O N
N o t e : V D D ( M in ) o f H Y 5 7 V 6 4 1 6 2 0 H G ( L ) T - 5 /5 5 / 6 i s 3 . 1 3 5 V
H Y 5 7 V 6 4 1 6 2 0 H G L T - 5 / 5 5 / 6 / 7
H Y 5 7 V 6 4 1 6 2 0 H G T - 5 / 5 5 / 6 / 7
Single 3.3
A l l d e v i c e p i n s a r e c o m p a t i b l e w i t h L V T T L i n t e r f a c e
J E D E C s t a n d a r d 4 0 0 m i l 5 4 p i n T S O P - I I w i t h 0 . 8 m m
o f p i n p i t c h
A l l i n p u t s a n d o u t p u t s r e f e r e n c e d t o p o s i t i v e e d g e o f
s y s t e m c l o c k
D a t a m a s k f u n c t i o n b y U D Q M o r L D Q M
I n t e r n a l f o u r b a n k s o p e r a t i o n
H Y 5 7 V 6 4 1 6 2 0 H G L T - H
H Y 5 7 V 6 4 1 6 2 0 H G L T - K
H Y 5 7 V 6 4 1 6 2 0 H G L T - 8
H Y 5 7 V 6 4 1 6 2 0 H G L T - P
H Y 5 7 V 6 4 1 6 2 0 H G L T - S
H Y 5 7 V 6 4 1 6 2 0 H G T - H
H Y 5 7 V 6 4 1 6 2 0 H G T - K
H Y 5 7 V 6 4 1 6 2 0 H G T - 8
H Y 5 7 V 6 4 1 6 2 0 H G T - P
H Y 5 7 V 6 4 1 6 2 0 H G T - S
P a r t N o .
0 . 3 V p o w e r s u p p l y
2 0 0 / 1 8 3 / 1 6 6 / 1 4 3 M H z
2 0 0 / 1 8 3 / 1 6 6 / 1 4 3 M H z
C l o c k F r e q u e n c y
N o t e )
1 3 3 M H z
1 3 3 M H z
1 2 5 M H z
1 0 0 M H z
1 0 0 M H z
1 3 3 M H z
1 3 3 M H z
1 2 5 M H z
1 0 0 M H z
1 0 0 M H z
L o w p o w e r
P o w e r
N o r m a l
•
•
•
•
A u t o r e f r e s h a n d s e l f r e f r e s h
4 0 9 6 r e f r e s h c y c l e s / 6 4 m s
P r o g r a m m a b l e B u r s t L e n g t h a n d B u r s t T y p e
P r o g r a m m a b l e C A S L a t e n c y ; 2 , 3 C l o c k s
- 1 , 2 , 4 , 8 o r F u l l p a g e f o r S e q u e n t i a l B u r s t
- 1 , 2 , 4 o r 8 f o r I n t e r l e a v e B u r s t
4 B a n k s x 1 M b i t s
Organization
4 Banks x 1M x 16Bit Synchronous DRAM
x 1 6
Interface
L V T T L
4 0 0 m i l 5 4 p i n T S O P I I
HY57V641620HG
P a c k a g e
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HY57V641620HGT-S Summary of contents
Page 1
DESCRIPTION The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16. HY57V641620HG is offering fully synchronous operation referenced to ...
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