HY5DU283222BFP-28 Hynix Semiconductor, HY5DU283222BFP-28 Datasheet
HY5DU283222BFP-28
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HY5DU283222BFP-28 Summary of contents
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... HY5DU283222BF(P) 128M(4Mx32) GDDR SDRAM HY5DU283222BF(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Jul. 2005 1 ...
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Revision History No. 0.1 1) Defined Target Spec. 0.2 1) Added 200MHz speed bin 1) Changed Cas Latency to 4 clock from 5 clock at 300Mhz/275Mhz/ 0.3 250Mhz speed bin 1) Changed IDD & 500Mhz speed bin insert, 0.4 2) ...
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... Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials. We'll add "P" character after "F" for Lead free product. For example, the part number of 300MHz Lead free product is HY5DU283222BFP-33. Rev. 1.2 / Jul. 2005 rising and falling edges of the data strobe • ...
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PIN CONFIGURATION (Top View) Auto Precharge Flag Rev. 1.2 / Jul. 2005 ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh 1HY5DU283222BF(P) 4Mx32 4banks A0 ~ A11 BA0, ...
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PIN DESCRIPTION PIN TYPE CK, /CK Input CKE Input /CS Input BA0, BA1 Input A0 ~ A11 Input /RAS, /CAS, /WE Input DM0 ~ DM3 Input DQS0 ~ DQS3 I/O DQ0 ~ DQ31 I Supply ...
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FUNCTIONAL BLOCK DIAGRAM 4Banks x 1Mbit x 32 I/O Double Data Rate Synchronous DRAM CLK /CLK CKE /CS Command Decoder /RAS /CAS /WE DM(0~3) Register A0-11 Address Buffer BA0,BA1 Rev. 1.2 / Jul. 2005 Write Data Register 2-bit Prefetch Unit ...
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SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self ...
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WRITE MASK TRUTH TABLE Function CKEn-1 Data Write H Data-In Mask H Note : 1. Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data. 2. DM0 corresponds to the data ...
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OPERATION COMMAND TRUTH TABLE - I Current /CS /RAS State IDLE ROW L H ...
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OPERATION COMMAND TRUTH TABLE - II Current /CS /RAS State WRITE READ WITH L H AUTOPRE CHARGE ...
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OPERATION COMMAND TRUTH TABLE - III Current /CS /RAS State ROW L H ACTIVATING WRITE L ...
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OPERATION COMMAND TRUTH TABLE - IV Current /CS /RAS State WRITE MODE L H REGISTER ACCESSING ...
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CKE FUNCTION TRUTH TABLE Current CKEn- CKEn State SELF REFRESH POWER DOWN ...
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SIMPLIFIED STATE DIAGRAM MODE REGISTER SET POWER DOWN READ WRITE READAP WRITE WRITEAP PRE(PALL) Rev. 1.2 / Jul. 2005 MRS SREF IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE ...
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF ...
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Power-Up Sequence VDD VDDQ tVTD VTT VREF /CLK CLK tIS tIH LVCMOS Low Level CKE CMD NOP DM ADDR A10 BA0, BA1 DQS DQ'S T=200usec Power UP VDD and CK stable Rev. 1.2 / Jul. 2005 PRE MRS EMRS NOP ...
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MODE REGISTER SET (MRS) The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is program via MRS command. This command is ...
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BURST DEFINITION Burst Length Starting Address (A2,A1,A0 BURST LENGTH & TYPE Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column ...
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CAS LATENCY The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed ...
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EXTENDED MODE REGISTER SET (EMRS) The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func- tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended ...
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ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Voltage on V relative to V DDQ SS Output Short Circuit Current Power Dissipation Soldering Temperature ...
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DC CHARACTERISTICS II Sym Parameter bol One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs Operating Current I DD0 changing twice per clock cycle; address and control inputs changing once per clock cycle Burst length=2, One bank active ...
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AC OPERATING CONDITIONS Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note ...
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AC CHARACTERISTICS - I Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay for Read Row Address to Column Address Delay for Write Row Active to Row Active Delay Column Address ...
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Parameter Data-In Hold Time to DQS-In (DQ & DM) Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any ...
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AC CHARACTERISTICS - I (continue) Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay for Read Row Address to Column Address Delay for Write Row Active to Row Active Delay Column ...
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Parameter Data-In Hold Time to DQS-In (DQ & DM) Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any ...
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AC CHARACTERISTICS - II Frequency CL tRC 500MHz (2.0ns) 5 450MHz (2.2ns) 5 400MHz (2.5ns) 5 350MHz (2.8ns) 4 300MHz (3.3ns) 4 275MHz (3.6ns) 4 250MHz (4.0ns) 4 200MHz(5ns) 3 Rev. 1.2 / Jul. 2005 tRFC tRAS tRCDRD 23 25 ...
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CAPACITANCE o (T =25 C, f=1MHz ) A Parameter Input Clock Capacitance Input Capacitance Input / Output Capacitance Note : min. to max 2.3V to 2.7V DDQ 2. Pins not under test are ...
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PACKAGE INFORMATION 12mm x 12mm, 144ball Fine-pitch Ball Grid Array 12mm±0.1mm 8.8mm [ Ball Location ] Ball existing Optional (Thermal ball, NC, No ball) Depopulated ball Rev. 1.2 / Jul. 2005 1HY5DU283222BF(P) 1.2mm±0.1mm 0.86mm±0.05 12mm±0.1mm 0.35mm±0.05 0.8mm Detailed "A" 8.8mm ...