HY5DU573222AFM-33 Hynix Semiconductor, HY5DU573222AFM-33 Datasheet

no-image

HY5DU573222AFM-33

Manufacturer Part Number
HY5DU573222AFM-33
Description
Manufacturer
Hynix Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HY5DU573222AFM-33
Manufacturer:
RENESAS
Quantity:
104
HY5DU573222AFM
256M(8Mx32) GDDR SDRAM
HY5DU573222AFM
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon-
sibility for use of circuits described. No patent licenses are implied.
Rev. 0.5 / Aug. 2003
1

Related parts for HY5DU573222AFM-33

HY5DU573222AFM-33 Summary of contents

Page 1

... GDDR SDRAM This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon- sibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / Aug. 2003 HY5DU573222AFM HY5DU573222AFM 1 ...

Page 2

... Changed tCK_max value of HY5DU573222AFM-33/36/4 from 6ns to 10ns 5) Typo corrected 1) Changed VDD_min value of HY5DU573222AFM-33 from 2.375V to 2.2V 0.3 2) Changed VDD_min value of HY5DU573222AFM-36 from 2.2V to 2.375V 1) Changed CAS Latency of HY5DU573222AFM-28 from CL5 to CL4 2) Changed VDD_min value of HY5DU573222AFM-28/25 from 2.66V to 2.55V ...

Page 3

... Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) ORDERING INFORMATION Part No. Power Supply HY5DU573222AFM- HY5DU573222AFM-28 DDQ HY5DU573222AFM-33 V HY5DU573222AFM-36 V DDQ HY5DU573222AFM-4 Rev. 0.5 / Aug. 2003 power supply • Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe • ...

Page 4

... BA1 A2 A11 A9 BA0 ROW and COLUMN ADDRESS TABLE Items Organization 4banks x 2chip Row Address Column Address Bank Address Refresh Chip Selection HY5DU573222AFM DQ29 DQ28 VSSQ DM3 DQS3 DQ30 VDDQ NC VDDQ DQ27 VSSQ VSSQ VSSQ ...

Page 5

... DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31 Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DU573222AFM 5 ...

Page 6

... Colum n Address Colum n Address Counter Counter DS DS Colum n Address Colum n Address Mode Register Mode Register DLL DLL Counter Counter CLK_DLL CLK_DLL Block Block CLK, /CLK CLK, /CLK HY5DU573222AFM 32bit 32bit 64bit 64bit DS DS 32bit 32bit 64bit 64bit DQ[0:31] ...

Page 7

... HY5DU573222AFM A8/ CAS WE ADDR code code ...

Page 8

... Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data. 2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31. Rev. 0.5 / Aug. 2003 /CS0, /CS1, /RAS, CKEn /CAS, / HY5DU573222AFM A8/ DM(0~3) BA ADDR Note ...

Page 9

... OPCODE BA, CA, AP READ/READAP* BA, CA, AP WRITE/WRITEAP*13 HY5DU573222AFM Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS *12 Mode Register Set ...

Page 10

... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU573222AFM Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL ...

Page 11

... OPCODE BA, CA, AP READ/READAP HY5DU573222AFM Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL ...

Page 12

... H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU573222AFM Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ...

Page 13

... HY5DU573222AFM /ADD Action X INVALID X Exit self refresh, enter idle after tSREX* X Exit self refresh, enter idle after tSREX* X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle* ...

Page 14

... AUTOPRE- CHARGE CHARGE CHARGE CHARGE CHARGE CHARGE PRE- PRE- PRE- CHARGE CHARGE CHARGE POWER-UP POWER-UP POWER-UP POWER APPLIED POWER APPLIED POWER APPLIED HY5DU573222AFM SREF SREF SREF SELF SELF SELF REFRESH REFRESH REFRESH SREX SREX SREX AUTO AUTO AUTO REFRESH REFRESH REFRESH ...

Page 15

... Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. Rev. 0.5 / Aug. 2003 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ HY5DU573222AFM < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 15 ...

Page 16

... CODE CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command HY5DU573222AFM AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...

Page 17

... Yes CAS Latency Reserved Reserved Reserved Reserved Reserved HY5DU573222AFM Burst Length Burst Length Sequential Reserved Reserved Reserved ...

Page 18

... HY5DU573222AFM Interleave ...

Page 19

... This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to- point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength. Rev. 0.5 / Aug. 2003 HY5DU573222AFM 19 ...

Page 20

... All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 0.5 / Aug. 2003 RFU HY5DU573222AFM DLL A0 DLL enable 0 Enable 1 Diable A1 Output Driver Impedance Control 0 RFU* 1 Half (60%) 0 RFU* 1 Weak (40%) 0 RFU* 1 Semi Half (50%) 0 ...

Page 21

... V TT REF V 0.49*V 0.5*V REF DDQ . DD may not exceed ± the DC value. o (TA Voltage referenced to V Symbol Min 0. =0V HY5DU573222AFM Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Max Unit 2.5 2.625 V 2.5 2.625 V 2.8 2.95 V 2.5 2.625 V 2.5 2.625 V 2.8 2.95 V ...

Page 22

... VIL CK 70 (min), /CS ≥ V (min 170 (max), t =min IL CK 100 (min), /CS ≥ IH =min, Input signals CK 270 820 (min), RFC 700 6 1100 HY5DU573222AFM = 0V) SS Speed 240 220 210 200 260 240 230 220 150 120 120 120 ...

Page 23

... C, Voltage referenced to V Symbol Min 0.35 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V -0.2 IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V HY5DU573222AFM = 0V) SS Max Unit Note 0.35 V REF V + 0.6 V DDQ 0.5*V +0.2 V DDQ Value Unit V x 0.5 V DDQ ...

Page 24

... DRL DAL CL 0. DQSCK -0.6 t DQSQ - tHPmin t QH -tQHS tCH min t QHS - t 0. 0.75 t DQSH 0.4 t DQSL 0.4 t DQSS 0. 0.35 HY5DU573222AFM 28 Max Min Max - 100K 10 100K - 2.8 6 0.55 0.45 0.55 0.55 0.45 0.55 0.6 -0.6 0.6 0.6 -0.6 0.6 0.35 - 0.35 tHPmin - - -tQHS tCH/L ...

Page 25

... DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. Rev. 0.5 / Aug. 2003 25 Symbol Min Max t 0.9 1.1 RPRE t 0.4 0.6 RPST t WPRES WPREH 0. WPST 0.4 0 MRD t XSC 200 - 2tCK t - PDEX + tIS t - 7.8 REFI HY5DU573222AFM 28 Unit Note Min Max CK 0.9 1.1 CK 0 0.4 0 200 - 4 2tCK tIS us - 7.8 25 ...

Page 26

... CK CL=3 4 0.45 0.55 t 0.45 0. -0.6 0 DQSCK -0.6 0.6 t DQSQ - 0.35 tHPmin -tQHS tCH min t QHS - 0. DQSH 0.4 0.6 t DQSL 0.4 0.6 t DQSS 0.85 1. 0.35 - HY5DU573222AFM 36 4 Min Max Min Max 100K 8 100K 3 4.5 10 4.5 10 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 -0 ...

Page 27

... Signal transitions through the DC region must be monotonic. Rev. 0.5 / Aug. 2003 33 Symbol Min Max Min t 0.9 1.1 0.9 RPRE t 0.4 0.6 0.4 RPST t WPRES WPREH 0.35 - 0.35 t WPST 0.4 0.6 0 MRD t XSC 200 - 200 2tCK 1tCK t - PDEX + tIS + tIS t - 7.8 - REFI HY5DU573222AFM 36 4 Unit Note Max Min Max CK 1.1 0.9 1.1 CK 0.6 0 0.6 0.4 0 200 - 1tCK tIS us 7 ...

Page 28

... Rev. 0.5 / Aug. 2003 tRFC tRAS tRCDRD HY5DU573222AFM tRCDWR tRP tDAL Unit tCK tCK tCK tCK tCK 28 ...

Page 29

... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 0.5 / Aug. 2003 Pin CK, /CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50Ω T Zo=50Ω V REF C =30pF L HY5DU573222AFM Symbol Min Max Unit C 1.5 5 1.5 5 5.5 9 ...

Page 30

... Detailed “A” Detailed “A” 8.8mm 8.8mm 0.12mm 0.12mm (MO 205- JEDEC) (MO 205- JEDEC) HY5DU573222AFM Detailed “A” Detailed “A” 0.5mm Diameter 0.5mm Diameter 0.55Max 0.55Max 0.45Min 0.45Min 30 ...

Related keywords