HY5DU573222F-28 Hynix Semiconductor, HY5DU573222F-28 Datasheet
HY5DU573222F-28
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HY5DU573222F-28 Summary of contents
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... HY5DU573222F(P) 256M(8Mx32) GDDR SDRAM This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / May. 2005 HY5DU573222F(P) 1 ...
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... Changed IDD & 500Mhz speed bin insert, 0.5 2) Changed tRCDWR, tWR at 450Mhz speed bin 1.0 Changed Cas Latency to 4 clock from 5 clock at 350MHz speed bin 1.1 Added 200Mhz Speed Bin Rev. 1.1 / May. 2005 History 1HY5DU573222F(P) Draft Date Remark Aug. 2003 Feb. 2004 Jun. 2004 Sep. 2004 Oct. 2004 Feb. 2005 May ...
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... Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials. We'll add "P" character after "F" for Lead free product. For example, the part number of 300MHz Lead free product is HY5DU573222FP-33. Rev. 1.1 / May. 2005 • ...
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... PIN CONFIGURATION (Top View) Auto Precharge Flag Rev. 1.1 / May. 2005 ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh 1HY5DU573222F(P) 8Mx32 4banks A0 ~ A11 A0 ~ A7, A9 BA0, BA1 ...
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... DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31 Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. 1HY5DU573222F(P) 5 ...
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... Rev. 1.1 / May. 2005 Write Data Register 2-bit Prefetch Unit Bank 2Mx32/Bank0 Control 2Mx32 /Bank1 2Mx32 /Bank2 2Mx32 /Bank3 Mode Row Decoder Column Decoder Column Address Counter CLK, /CLK Block Mode Register 1HY5DU573222F( Data Strobe CLK_DLL Transmitter Data Strobe DS Receiver DLL DS DQ[0:31] DQS(0~3) 6 ...
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... 1HY5DU573222F(P) A8/ CAS WE ADDR code code ...
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... Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data. 2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31. Rev. 1.1 / May. 2005 /CS, /RAS, CKEn /CAS, / 1HY5DU573222F(P) A8/ DM(0~3) BA ADDR Note ...
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... OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP 1HY5DU573222F(P) Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE 1HY5DU573222F(P) Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL ...
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... OPCODE BA, CA, AP READ/READAP 1HY5DU573222F(P) Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL ...
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... H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE 1HY5DU573222F(P) Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ...
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... 1HY5DU573222F(P) /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle ...
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... IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED 1HY5DU573222F(P) SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 14 ...
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... Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. Rev. 1.1 / May. 2005 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ 1HY5DU573222F(P) < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 15 ...
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... CODE CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command 1HY5DU573222F(P) AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
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... Yes CAS Latency Reserved Reserved Reserved Reserved Reserved 1HY5DU573222F( Burst Length Burst Length Sequential Reserved Reserved Reserved ...
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... Interleave ...
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... This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to- point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength. Rev. 1.1 / May. 2005 1HY5DU573222F(P) 19 ...
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... All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 1.1 / May. 2005 RFU 1HY5DU573222F( DLL A0 DLL enable 0 Enable 1 Diable Output Driver Impedance Control Full Half RFU* Weak 20 ...
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... DC level of the same. DDQ ± the DC value. o (TA Voltage referenced to V Symbol Min 0. =0V 1HY5DU573222F(P) Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Max Unit 2.5 2.7 V 2.5 2 0.3 V DDQ ...
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... IL CK (min), /CS ≥ V (min 340 320 (min), I =0mA OL 850 800 (min), 600 600 8 8 1100 1000 900 1HY5DU573222F(P) = 0V) SS Speed 310 290 270 260 250 250 350 330 310 300 290 280 250 ...
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... C, Voltage referenced to V Symbol Min 0.35 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V -0.2 IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V 1HY5DU573222F(P) = 0V) SS Max Unit Note 0.35 V REF V + 0.6 V DDQ 0.5*V +0.2 V DDQ Value Unit V x 0.5 V DDQ ...
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... DQSCK -0.6 0.6 -0.6 t DQSQ - 0.35 - tHPmin tHPmin -tQHS -tQHS tCH/L tCH min min t QHS - 0. 0 0.6 - 0.75 t DQSH 0.4 0.6 0.4 t DQSL 0.4 0.6 0.4 t 0.85 1.15 0.85 DQSS t 0.35 - 0.35 DS 1HY5DU573222F( Max Min Max Min Max - 100K 12 100K 11 100K - 2 ...
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... Symbol Min Max Min Max t 0. 0.9 1.1 0.9 1.1 RPRE t RPST 0.4 0.6 0.4 0.6 t WPRES WPREH 0.35 - 0.35 t 0.4 0.6 0.4 0.6 WPST t MRD XSC 200 - 200 2tCK 2tCK t PDEX - + tIS + tIS t REFI - 7.8 - 1HY5DU573222F( Min Max Min Max - 0.35 - 0.35 - 0.9 1.1 0.9 1.1 0.4 0.6 0.4 0 0.35 - 0.35 - 0.4 0.6 0.4 0 200 - 200 - 2tCK 2tCK - - - + tIS + tIS 7.8 - 7.8 - 7.8 Unit Note ...
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... CL t -0.6 0.6 -0 DQSCK -0.6 0.6 -0.6 t DQSQ - 0.35 - tHPmin tHPmin -tQHS -tQHS tCH/L tCH min min t QHS - 0. 0. 0.75 - 0.75 t DQSH 0.4 0.6 0.4 t DQSL 0.4 0.6 0.4 t 0.85 1.15 0.85 DQSS t 0.35 - 0.4 DS 1HY5DU573222F( Max Min Max Min Max - 100K 7 100K - ...
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... Rev. 1.1 / May. 2005 33 36 Symbol Min Max Min t 0. 0.9 1.1 0.9 RPRE t RPST 0.4 0.6 0.4 t WPRES WPREH 0.35 - 0.35 t 0.4 0.6 0.4 WPST t MRD XSC 200 - 200 2tCK 1tCK t PDEX - + tIS + tIS t REFI - 7.8 - 1HY5DU573222F( Max Min Max Min Max - 0.4 - 0.4 - 1.1 0.9 1.1 0.9 1.1 0.6 0.4 0.6 0.4 0 0.35 - 0.35 - 0.6 0.4 0.6 0.4 0 200 - 200 - 1tCK 1tCK - - - + tIS + tIS 7 ...
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... Rev. 1.1 / May. 2005 tRFC tRAS tRCDRD 1HY5DU573222F(P) tRCDWR tRP tDAL Unit 13 tCK 11 tCK ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 1.1 / May. 2005 Pin CK, /CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50Ω T Zo=50Ω V REF C =30pF L 1HY5DU573222F(P) Symbol Min Max Unit ...
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... Fine-pitch Ball Grid Array 12mm±0.1mm 8.8mm [ Ball Location ] Ball existing Optional (Thermal ball, NC, No ball) Depopulated ball Rev. 1.1 / May. 2005 1HY5DU573222F(P) 1.2mm±0.1mm 0.86mm±0.05 12mm±0.1mm 0.35mm±0.05 0.8mm Detailed "A" 8.8mm ...