HYB18L256160BF-7.5 Infineon Technologies AG, HYB18L256160BF-7.5 Datasheet
HYB18L256160BF-7.5
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HYB18L256160BF-7.5 Summary of contents
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... Edition 2004-04-30 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2004. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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... HYB18L256160BF-7.5, HYE18L256160BF-7.5, HYB18L256160BC-7.5, HYE18L256160BC-7.5 Revision History: V1 Table 20: removed T 47 Table 23: driver characteristics for half drive and full drive merged Previous Version: V1.3 (Preliminary Datasheet) 12 power-up sequence: 2 instead of 8 ARF commands required 47 Table 22: IDD6 specification modified: typ. and max. values given Previous Version: V1 ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Standard Ballout 256-Mbit Mobile-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview 1.1 Features 4 banks • 4 Mbit 16 organization • Fully synchronous to positive clock edge • Four internal banks for concurrent operation • Programmable CAS latency • Programmable burst length ...
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... Table 3 Ordering Information 1) Type Package Commercial Temperature Range HYB18L256160BC-7.5 P-VFBGA-54-2 HYB18L256160BF-7.5 P-VFBGA-54-2 Extended Temperature Range HYE18L256160BC-7.5 P-VFBGA-54-2 HYE18L256160BF-7.5 P-VFBGA-54-2 1) HYB / HYE: Designator for memory products (HYB: standard temp. range; HYE: extended temp. range) 18L: 1.8V Mobile-RAM 256: 256 MBit density 160: 16 bit interface width ...
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Description The HY[B/E]18L256160B[C/ high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. The HY[B/E]18L256160B[C/F] achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and ...
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Pin Definition and Description Table 4 Pin Description Ball Type Detailed Function CLK Input Clock: all inputs are sampled on the positive edge of CLK. CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, ...
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Functional Description The 256-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location ...
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At first, device core power (V and V are driven from a single power converter output. DDQ Assert and hold CKE and DQM to a HIGH level. 2. After V and V are stable and CKE is HIGH, apply ...
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Burst Length READ and WRITE accesses to the Mobile-RAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. ...
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Read Latency The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be programmed ...
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Temperature Compensated Self Refresh (TCSR) with On-Chip Temperature Sensor DRAM devices store data as electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored information. This refresh requirement heavily depends on the die ...
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State Diagram Power On Power applied Precharge All PREALL Mode Register Set Clock CKEL Suspend CKEH WRITE WRITEA Clock CKEL Suspend CKEH WRITEA PRE PREALL = Precharge All Banks REFS = Enter Self Refresh REFSX = Exit Self Refresh ...
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Commands Table 6 Command Overview Command NOP DESELECT NO OPERATION ACT ACTIVE (Select bank and row) RD READ (Select bank and column and start read burst) WR WRITE (Select bank and column and start write burst) BST BURST TERMINATE ...
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Table 7 Inputs Timing Parameters Parameter Clock cycle time Clock frequency Clock high-level width Clock low-level width Address and command input setup time Address and command input hold time 2.4.1 NO OPERATION (NOP) CLK CKE (High) CS RAS CAS WE ...
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MODE REGISTER SET CLK CKE (High) CS RAS CAS WE A0-A12 Code BA0,BA1 Code = Don't Care Figure 7 Mode Register Set Command CLK Command Address Code = Mode Register / Extended Mode Register selection Figure 8 Mode Register ...
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ACTIVE CLK CKE (High) CS RAS CAS WE A0-A12 RA BA0,BA1 BA = Don't Care BA = Bank Address RA = Row Address Figure 9 ACTIVE Command CLK Command ACT A0-A12 ROW BA0, BA1 BA x Figure 10 Bank ...
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READ CLK CKE (High) CS RAS CAS WE A0-A8 CA Enable AP A10 AP Disable AP BA0,BA1 BA = Don't Care BA = Bank Address CA = Column Address AP = Auto Precharge Figure 11 READ Command CLK DQM ...
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Table 10 Timing Parameters for READ Parameter Access time from CLK DQ low-impedance time from CLK DQ high-impedance time from CLK Data out hold time DQM to DQ High-Z delay (READ Commands) ACTIVE to ACTIVE command period ACTIVE to READ ...
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CLK t RCD Command ACT NOP NOP Ba A, Address Row x A10 (AP) Row Col n = bank A, column Data Out from column n Burst Length = 4 in the ...
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CLK Command READ READ Address Col n Col a CL Col n etc. = Bank A, Column n etc etc. = Data Out from column n etc. Burst Length ...
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READ Burst Termination Data from any READ burst may be truncated using the BURST TERMINATE command (see that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE command must ...
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READ - DQM Operation DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing parameters as listed in Table 10 will continue as programmed. CLK Command READ Ba A, Address ...
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READ to PRECHARGE A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that Auto Precharge was not activated. This is shown in The PRECHARGE command should be issued x clock ...
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WRITE CLK CKE (High) CS RAS CAS WE A0-A8 CA Enable AP A10 AP Disable AP BA0,BA1 BA = Don't Care BA = Bank Address CA = Column Address AP = Auto Precharge Figure 23 WRITE Command CLK DQM ...
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Table 11 Timing Parameters for WRITE Parameter DQ and DQM input setup time DQ and DQM input hold time DQM write mask latency ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE to PRECHARGE command period WRITE ...
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Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. A WRITE command can be issued on any positive edge of clock ...
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WRITE Burst Termination Data from any WRITE burst may be truncated using the BURST TERMINATE command (see that Auto Precharge was not activated. The input data provided coincident with the BURST TERMINATE command will be ignored. This is shown ...
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WRITE - DQM Operation DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be performed. The generic timing parameters as listed in in progress is not affected and ...
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WRITE to PRECHARGE A WRITE burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that Auto Precharge was not activated. This is shown in The PRECHARGE command should be issued the WRITE ...
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PRECHARGE CLK CKE (High) CS RAS CAS WE A0-A9 A11,A12 All Banks A10 One Bank BA0,BA1 BA = Don't Care BA = Bank Address (if A10 = L, otherwise Don't Care) Figure 36 PRECHARGE Command 2.4.8.1 AUTO PRECHARGE Auto ...
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CONCURRENT AUTO PRECHARGE A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE command issued to a different bank. Figure 37 shows a READ with Auto Precharge to bank n, interrupted ...
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CLK Command WR-AP Bank n Address Col WR-AP = Write with Auto Precharge; READ = Read with or without Auto Precharge and Burst Length = 4 in the case shown Write with Auto ...
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AUTO REFRESH and SELF REFRESH The Mobile-RAM requires a refresh of all rows in a rolling interval. Each refresh is generated in one of two ways explicit AUTO REFRESH command internally timed event in ...
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SELF REFRESH CLK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care Figure 43 SELF REFRESH Entry Command CLK t RP CKE Command PRE NOP Address A10 (AP) Pre All High-Z DQ Self Refresh Entry Command Figure 44 ...
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POWER DOWN CLK CKE CS RAS CAS WE A0-A12 BA0,BA1 = Don't Care Figure 45 Power Down Entry Command CLK CKE Command PRE Address A10 (AP) Pre All DQ Precharge Power Down mode shown: all banks are idle and ...
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Function Truth Tables Table 14 Current State Bank n - Command to Bank n Current State CS RAS CAS WE Command / Action Any Idle ...
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The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when SDRAM ...
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Current state definitions: Idle: The bank has been precharged, and Row Active: A row in the bank has been activated, and accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not ...
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Electrical Characteristics 3.1 Operating Conditions Table 17 Absolute Maximum Ratings Parameter Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Attention: Stresses above those ...
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Table 19 Electrical Characteristics Parameter Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current (comm.); ...
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AC Characteristics Table 20 AC Characteristics Parameter Clock cycle time Clock frequency Access time from CLK Clock high-level width Clock low-level width Address, data and command input setup time Address, data and command input hold time MODE REGISTER SET ...
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Operating Currents Table 21 Maximum Operating Currents Parameter & Test Conditions Operating current: one bank: active / read / precharge Precharge power-down standby current: V all banks idle CKE IHmin inputs changing once every ...
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Table 22 Self Refresh Currents Parameter & Test Conditions Self Refresh Current: Self refresh mode, full array activation (PASR = 000) Self Refresh Current: Self refresh mode, half array activation (PASR = 001) Self Refresh Current: Self refresh mode, quarter ...
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Package Outlines 0 Marking Ballside 2) Die Sort Fiducial 3) Bad Unit Marking (BUM) 4) Middle of Packages Edges 5) Middle of Ball Matrix Figure 47 P-VFBGA-54-2 (Plastic Very Thin Fine Ball Grid Array Package) You ...
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... Published by Infineon Technologies AG ...