HYB18T512160AF-3.7 Infineon Technologies AG, HYB18T512160AF-3.7 Datasheet
HYB18T512160AF-3.7
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HYB18T512160AF-3.7 Summary of contents
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... HYB18T512400AF HYB18T512800AF HYB18T512160AF 512-Mbit DDR2 SDRAM DDR2 SDRAM RoHS Compliant Products Rev. 1. ...
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... Edition 2005-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2005. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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... HYB18T512400AF HYB18T512800AF HYB18T512160AF 512-Mbit DDR2 SDRAM DDR2 SDRAM RoHS Compliant Products Rev. 1. ...
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5] Revision History: 2005-01 Previous Version: 2004-09 (Rev. 1.2) Page Subjects (major changes since last revision 113 Added , derating for Single-Ended DQS for DDR2-400 and DDR2-533 DS1 DH1 All Added 50 Ohm support All Document contains green ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.3 DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 High Performance DDR667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 54 Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C . . . . . . . . . . . . . . . . . . . . . . . 101 Table 55 ...
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List of Figures Figure 1 Pin Configuration for ×4 components, P-TFBGA-60 (top view ...
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List of Figures Figure 54 Self Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... RoHS Compliant Products –3 –3S DDR2–667C 4–4–4 DDR2–667D 5–5–5 f 333 333 CK5 f 333 266 CK4 f 200 200 CK3 RCD RAS HYB18T512400AF HYB18T512800AF HYB18T512160AF 1) Unit — MHz MHz MHz Rev. 1.3, 2005-01 09112003-SDM9-IQ3P ...
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Table 2 High Performance for DDR2–400B and DDR2–533C Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time 1.2 Description The 512-Mb DDR2 DRAM ...
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... DDR2–667 4–4–4 ×4 HYB18T512800AF–3 ×8 HYB18T512160AF–3 ×16 HYB18T512400AF–3S ×4 HYB18T512800AF–3S ×8 HYB18T512160AF–3S ×16 1) CAS: Column Adress Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge Note: For product nomenclature see Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 1) ...
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Pin Configuration and Block Diagrams The pin configuration of a DDR2 SDRAM is listed by function in Type columns are explained in Table 5 depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16. ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Buffer Type Type Control Signals ×16 organization K7 RAS I SSTL L7 CAS I SSTL SSTL SSTL Address Signals ×4/×8 organizations G2 BA0 I ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Buffer Type Type SSTL SSTL SSTL SSTL SSTL SSTL ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Buffer Type Type G8 DQ0 I/O SSTL G2 DQ1 I/O SSTL H7 DQ2 I/O SSTL H3 DQ3 I/O SSTL H1 DQ4 I/O SSTL H9 DQ5 I/O SSTL F1 DQ6 I/O ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Buffer Type Type SSTL Data Mask ×16 organization B3 UDM I SSTL F3 LDM I SSTL Power Supplies ×4/×8/×16 organizations A9,C1,C3,C7, V PWR – DDQ C9 A1 ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Buffer Type Type Not Connected ×16 organization A2, E2, L1, R3 – R7, R8 Other Pins ×4/×8 organizations F9 ODT I SSTL Other Pins ×16 organization K9 ODT ...
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TFBGA Ball Out Diagrams $ $ $ $ $ $ $ $ Figure 1 Pin Configuration for ×4 components, P-TFBGA-60 (top view) Note and V are power and ground for the DDL SSDL DLL.They are isolated on ...
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Figure 2 Pin Configuration for ×8 components, P-TFBGA-60 (top view) Note: 1. RDQS / RDQS are enabled by EMRS(1) command RDQS / RDQS is enabled, the DM function is disabled ...
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Figure 3 Pin Configuration for ×16 components, P-TFBGA-84 (top view) Note: 1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0] 2. LDM is ...
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Mbit DDR2 Addressing Table 7 512 Mbit DDR2 Addressing Configuration 128 Bank Address BA[1:0] Number of Banks 4 Auto-Precharge A10 / AP Row Address A[13:0] Column Address A11, A[9:0] Number of Column 11 Address Bits ...
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Block Diagrams Figure 4 Block Diagram 32 Mbit × 4 I/O ×4 Internal Memory Banks Note: 1. 128Mb × 4 Organisation with 14 Row, 2 Bank and 11 Column External Adresses 2. This Functional Block Diagram is intended to ...
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Figure 5 Block Diagram 16 Mbit × 8 I/O ×4 Internal Memory Banks Note: 1. 64Mb × 8 Organisation with 14 Row, 2 Bank and 10 Column External Adresses 2. This Functional Block Diagram is intended to facilitate user understanding ...
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Figure 6 Block Diagram 8 Mbit × 16 I/O ×4 Internal Memory Banks Note: 1. 32Mb × 16 Organisation with 13 Row, 2 Bank and 10 Column External Adresses 2. This Functional Block Diagram is intended to facilitate user understanding ...
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Functional Description 3.1 Simplified State Diagram Figure 7 Simplified State Diagram Note: This Simplified State Diagram is intended to provide a floorplan of the possible state transitions and the commands to control them. In particular situations involving more than ...
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Basic Functionality Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of ...
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Programming the Mode Register and Extended Mode Registers For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) Additionally, ...
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Table 8 Mode Register Definition (BA[2:0] = 000B) 1) Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0 B BA1 15 Bank Address [ ...
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Table 8 Mode Register Definition (BA[2:0] = 000B) 1) Field Bits Type Description Burst Type 0 BT, Sequential B 1 BT, Interleaved B BL [2:0] w Burst Length Note: All other bit combinations are illegal. 010 BL, ...
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Table 9 Extended Mode Register Definition (BA[2:0] = 001B) 1) Field Bits Type Description A13 13 w Address Bus[13] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0 A13, Address bit 13 B Qoff 12 ...
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A0 is used for DLL enable or disable used for enabling half-strength data-output driver. A2 and A6 enables On-Die termination (ODT) and sets the Rtt value. A[5:3] are used for additive latency settings and A[9:7] enables the OCD ...
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Extended Mode Register EMR(2) The Extended Mode Registers EMR(2) and EMR(3) are reserved for future use and must be programmed when setting the mode register during initialization.The extended mode register EMR(2) is written by asserting LOW on CS, RAS, ...
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Extended Mode Register EMR(3) The Extended Mode Register EMR(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during Table 12 EMR(3) Programming Extended Mode Register ...
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Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of the sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before any other OCD Impedance ...
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Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS(1) mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMR(1) bit enabling ...
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For proper operation of adjust mode clocks and should be met as shown Figure 10. Input data pattern for adjustment, DT[0:3] is fixed ...
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On-Die Termination (ODT) On-Die Termination (ODT new feature on DDR2 components that allows a DRAM to turn on/off termi- nation resistance for each DQ, DQS, DQS, DM for ×4 and DQ, DQS, DQS, DM, RDQS (DM/RDQS share ...
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ODT Truth Tables The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and A11 in the EMRS(1) for all three device Table 15 ODT Truth Table Input Pin x4 ...
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ODT timing modes Depending on the operating mode asynchronous or synchronous ODT timings apply Asynchronous ODT timings ( , AOFPD the on-die DLL is disabled. These modes are CK, CK CKE t IS ODT tAOND ...
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CK, CK "low" CKE ODT tAONPD,min tAONPD,max Figure 14 ODT Timing for Precharge Power-Down and Active Power-Down Mode Note: Asynchronous ODT timings apply for Precharge Power-Down Mode and “Slow Exit” Active ...
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T-5 T-4 CK, CK CKE ODT turn-off, tANPD >= 3 tck : ODT ODT turn-off, tANPD <3 tck : ODT ODT turn-on, tANPD >= 3 tck : ODT ODT turn-on, tANPD < 3 tck : ODT Figure 15 ODT Mode ...
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Mode exit t As long as the timing parameter AXPD.MIN when ODT is turned on or off after exiting these power- down modes, synchronous timing parameters can CK CKE ODT turn-off, tAXPD >= tAXPDmin: ...
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Bank Activate Command The Bank Activate command is issued by holding CAS and WE HIGH with CS and RAS LOW at the rising edge of the clock. The bank addresses BA[1:0] are used to select the desired bank. The ...
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Read and Write Commands and Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS HIGH, CS and CAS LOW at the clock’s rising edge. WE must ...
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Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a Read or Write command to be issued immediately after the bank ...
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CK, CK Activate CMD Bank A DQS, DQS tRCD DQ Figure 21 Read to Write Timing Example: Read followed by a write to the same bank t Activate to Read delay = : ...
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Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence ...
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Read Command The Read command is initiated by having CS and CAS LOW while holding RAS and WE HIGH at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay ...
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CMD DQ's Figure 26 Read Operation ...
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CK, CK Posted CAS Posted CAS NOP CMD READ A READ B DQS, DQS Figure 28 Seamless Read Operation Example ...
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Write Command The Write command is initiated by having CS, CAS and WE LOW while holding RAS HIGH at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by ...
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CK, CK Posted CAS CMD NOP NOP WRITE A <= t DQSS DQS, DQS DIN A0 Figure 32 Write Operation Example ( 3), ...
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CK, CK Posted CAS Posted CAS CMD NOP WRITE B WRITE A DQS, DQS Figure 34 Seamless Write Operation Example ...
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Write Data Mask One write data mask input (DM) for ×4 and ×8 components and two write data mask inputs (LDM, UDM) for ×16 components are supported on DDR2 SDRAM’s, consistent with the implementation on DDR SDRAM’s. It has ...
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Burst Interruption Interruption of a read or write burst is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions Read Burst can only be interrupted by another Read ...
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Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are LOW and CAS is HIGH at the rising edge of the ...
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CK, CK CMD Posted CAS NOP NOP READ BL/2 clks DQS, DQS >=tRAS first 4-bit prefetch Figure 41 Read Operation Followed by Precharge Example ...
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CK, CK Posted CAS CMD NOP NOP READ BL/2 clocks DQS, DQS >=tRAS Figure 43 Read Operation Followed by Precharge Example (AL = ...
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CK, CK Posted CAS CMD NOP NOP WRITE A DQS, DQS Figure 45 Write followed by Precharge Example ( ...
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Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre- charge Command or the Auto-Precharge function. When a Read or a Write Command is given to ...
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ste A10 ="high" BL ...
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ste A10 ="high" ...
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Write with Auto-Precharge If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins operation after the completion of the write burst plus the write recovery time delay ...
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Read or Write to Precharge Command Spacing Summary The following table summarizes the minimum command delays between Read, Read w/AP, Write, Write w/AP to the Precharge commands to the same banks and Precharge-All commands. Table 18 Minimum Command Delays ...
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Concurrent Auto-Precharge DDR2 devices support the “Concurrent Precharge” feature. A Read with Auto-Precharge enabled Write with Auto-Precharge enabled, may be followed by any command to the other bank, as long as that command does not interrupt the ...
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CK, CK "high" CKE > CMD Figure 53 Auto Refresh Timing 3.24.2 Self-Refresh Command The Self-Refresh command can be used to ...
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CK/CK CKE tis tAOFD ODT CMD Figure 54 Self Refresh Timing Note: 1. Device must be in the “All banks idle” state before entering Self Refresh mode (≥ 200 ) has to be satisfied ...
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Power-Down Entry Active Power-down mode can be entered after an Activate command. Precharge Power-down mode can be entered after a Precharge, Precharge-All or internal precharge command also allowed to enter power- mode after an Auto-Refresh command or MRS ...
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BL ...
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...
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Auto Refresh CKE can go low one clock after an Auto-Refresh command When tRFC expires the DRAM is in Precharge Power-Down Mode Figure 60 Auto-Refresh command ...
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Input Clock Frequency Change During operation the DRAM input clock frequency can be changed under the following conditions: • During Self-Refresh operation • DRAM is in Precharge Power-down mode and ODT is completely turned off. In the Precharge Power-down ...
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Truth tables Table 20 Command Truth Table Function CKE Previous Cycle (Extended) Mode H Register Set Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single Bank Precharge H Precharge all Banks H Bank Activate H Write H Write with ...
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Table 21 Clock Enable (CKE) Truth Table for Synchronous Transitions 1) Current State CKE 6) Previous Cycle Current Cycle (N-1) (N) Power-Down Self Refresh Bank( Active All Banks Idle H ...
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AC & DC Operating Conditions 5.1 Absolute Maximum Ratings Table 23 Absolute Maximum Ratings Symbol Parameter V Voltage on V pin relative Voltage on V pin relative to DDQ DDQ V Voltage on V pin ...
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DC Characteristics Table 25 Recommended DC Operating Conditions (SSTL_18) Symbol Parameter V Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF V Termination Voltage tracks ...
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DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...
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Table 30 Differential DC and AC Input and Output Logic Levels Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID(ac differential cross point input IX(ac) voltage V ...
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Output Buffer Characteristics Table 31 SSTL_18 Output DC Current Drive Symbol Parameter I Output Minimum Source DC Current OH I Output Minimum Sink DC Current 1 1. – DDQ ...
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Full Strength Output V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS(1) bits A[9:7] =’111’. Figure 66 Table 34 Full Strength Default Pull-up Driver Characteristics Voltage (V) Pull-up Driver ...
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Figure 66 Full Strength Default Pull-up Driver Diagram Table 35 Full Strength Default Pull–down Driver Characteristics Voltage (V) Pull-down Driver Current [mA] 1) Min. Nominal Default low 0.0 0.00 0.00 0.1 4.30 5.65 0.2 8.60 11.30 0.3 12.90 16.50 0.4 ...
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Figure 67 Full Strength Default Pull–down Driver Diagram 5.5.1 Calibrated Output Driver V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure outlined in the Off-Chip Driver (OCD) Impedance Adjustment. The ...
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Table 36 Full Strength Calibrated Pull-down Driver Characteristics Voltage (V) Calibrated Pull-down Driver Current [mA] 1) Nominal Minimum (21 Ohms) 0.2 9.5 0.3 14.3 0.4 18.7 1) The driver characteristics evaluation conditions are Nominal Minimum 95 ° The ...
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Reduced Output Drive Characteristics A driver mode with reduced output drive characteristics can be selected by setting address bit A1 in the EMRS(1) extended mode register to 1. Table 38 Reduced Strength Default Pull-up Driver Characteristics Voltage (V) Pull-up ...
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Figure 68 Reduced Strength Default Pull-up Driver Diagram Table 39 Reduced Strength Default Pull–down Driver Characteristics Voltage (V) Pull-down Driver Current [mA] 1) Min. IBIS Target low 0.0 0.00 0.00 0.1 1.72 ...
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Figure 69 Reduced Strength Default Pull–down Driver Diagram 5.7 Input / Output Capacitance Table ...
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Power & Ground Clamp V-I Characteristics Power and Ground clamps are provided on address (A[13:0], BA[11:0]), RAS, CAS, CS, WE, and ODT pins. Table 41 Power & Ground Clamp V-I Characteristics Voltage across clamp (V) Minimum Power Clamp Current ...
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VDD VSS Figure 70 AC Overshoot / Undershoot Diagram for Address and Control Pins Table 43 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area 0.9 Maximum peak amplitude ...
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Currents Measurement Specifications and Conditions Table 44 I Measurement Conditions DD Parameter Operating Current - One bank Active - Precharge CK(IDD) RC RC(IDD) RAS RAS.MIN(IDD) commands. Address ...
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Table 44 I Measurement Conditions DD Parameter Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and Other control and address inputs are floating, Data bus inputs are floating. Operating Bank Interleave Read Current I ...
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Table 46 I Specification for DDR2–667C and DDR2-667D DD Product Type Speed Code –3 Speed Grade DDR2–667C Symbol Max DD0 DD1 110 I 50 DD2N I 5 DD2P I 40 DD2Q I 50 DD3N I ...
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Table 47 I Specification for DDR2–533C and DDR2–400B DD Product Type Speed Code –3.7 Speed Grade DDR2–533C Symbol Max DD0 DD1 DD2N I 4 DD2P I 30 DD2Q I 40 DD3N I ...
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Test Conditions I DD For testing the I parameters, the following timing parameters are used: DD Table 48 I Measurement Test Conditions for DDR2–667C and DDR2–667D DD Parameter CAS Latency Clock Cycle Time Active to Read or Write delay ...
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On Die Termination (ODT) Current The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & the EMRS(1) a full or reduced termination can be selected. ...
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Electrical Characteristics 7.1 Speed Grade Defenitions Table 51 Speed Grade Definition Speed Bins for DDR667 Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active ...
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Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended ...
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Table 53 Timing Parameter by Speed Grade - DDR2-667 Parameter Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Read preamble Read postamble Active bank A to Active bank B ...
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MIN ( , ) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i. this value can be greater than the minimum specification ...
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Table 54 Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Parameter Symbol t DQ output access time from CAS A to CAS B command period t CK, CK high-level width CKE minimum high and low ...
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Table 54 Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C (cont’d) Parameter Symbol t Address and control input setup time t DQ low-impedance time from DQS low-impedance from Mode register set command ...
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Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings ...
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ODT AC Electrical Characteristics Table 55 ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD ...
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AC Timing Measurement Conditions 8.1 Reference Load for Timing Measurements Figure 72 represents the timing reference load used in defining the relevant timing parameters of the device not intended to either a precise representation of the typical ...
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Input and Data Setup and Hold Time 8.3.1 Definition for Input Setup ( Address and control input setup time ( from the input signal crossing at the rising signal and V for a falling signal applied to the IL(ac) ...
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Definition Data Setup ( Data input setup time ( t ) with single-ended data DS1 strobe enabled MR[bit10]=1, is referenced from the V input signal crossing at the level to the single- IH(ac) V ended data strobe crossing IH/L(dc) ...
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Slew Rate Definition for Input and Data Setup and Hold Times Setup ( t & nominal Slew Rate for a rising signal defined as the Slew Rate between the last crossing ...
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Figure 77 Slew Rate Definition Tangent Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM AC Timing Measurement Conditions 109 09112003-SDM9-IQ3P Rev. 1.3, 2005-01 ...
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Setup ( t ) and Hold ( IS 1. For all input signals the total input setup time and input hold time required is calculated by adding the data sheet value to the derating value respectively Example: ...
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Table 58 Derating Values for Input Setup and Hold Time (DDR2-400 & DDR2-533) Command / Address Slew Rate CK, CK Differential Slew Rate (V/ns) 2.0 V/ns ∆ 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 ...
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Table 59 Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-667) DQS, DQS Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns ∆ ∆ ∆ ∆ ∆ ...
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Table 61 Derating Values for Data Setup and Hold Time of Single-ended DQS (DDR2-400 & -533) DQS, DQS Single-ended Slew Rate 2.0 V/ns 1.5 V/ns 1.0 V/ns ∆ ∆ ∆ ∆ ∆ DS1 DH1 DS1 ...
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Package Dimensions Figure 78 Package Pinout PG-TFBGA-60 (top view) Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM Package Dimensions 114 09112003-SDM9-IQ3P Rev. 1.3, 2005-01 ...
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Figure 79 Package Pinout PG-TFBGA-84 (top view) Data Sheet HYB18T512[40/80/16]0AF–[3/3S/3.7/5] 512-Mbit DDR2 SDRAM Package Dimensions 115 09112003-SDM9-IQ3P Rev. 1.3, 2005-01 ...
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Product Namenclature Table 62 Nomenclature Fields and Examples Example for Field Number 1 2 DDR2 DRAM HYB 18 Table 63 DDR2 Memory Components Field Description 1 INFINEON Component Prefix 2 Interface Voltage [V] 3 DRAM Technology 4 Component Density ...
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... Published by Infineon Technologies AG ...