HYB25D256160BC-6 Infineon Technologies AG, HYB25D256160BC-6 Datasheet
HYB25D256160BC-6
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HYB25D256160BC-6 Summary of contents
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... Edition 2004-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2004. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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HYB25D256400B[T/C](L), HYB25D256800B[T/C](L), HYB25D256160B[T/C](L) Revision History: Rev. 1.2 Previous Version: V1.1 Page Subjects (major changes since last revision) Rev 1.2 All Added Products HYB25D256800BT-5, HYB25D256160BT-5, HYB25D256400BC-5 62-66 Corrected AC Timing values in table 19 and conform with Jedec ...
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Mbit Double Data Rate SDRAM DDR SDRAM 1 Overview 1.1 Features • Double data rate architecture: two data transfers per clock cycle. • Bidirectional data strobe (DQS) is transmitted and received with data used in capturing data ...
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The 256Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every ...
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... HYB25D256400BC(L)-8 u4 HYB25D256800BC(L)-8 u8 HYB25D256160BC(L)-8 u16 1) HYB: designator for memory components, 25D: DDR-I SDRAMs at Vddq=2.5V, 256: 256Mb density, 400/800/160: Product variations x4, x8 and x16, B: Die revision B, C/T: Package type FBGA and TSOP, L: Low power version (optional) - these components are specifically selected for low IDD6 Self Refresh currents. ...
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Pin Configuration VSSQ NC VSS A VDD NC VDDQ DQ3 B NC VSSQ VDDQ DQ2 D NC VSSQ DQS E VREF VSS DM F CLK CLK G A12 CKE H RAS A11 A9 ...
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DQ0 DQ0 V V DDQ DDQ NC DQ1 NC DQ0 DQ1 DQ2 V V SSQ SSQ NC NC DQ3 NC DQ2 DQ4 V V DDQ DDQ NC NC DQ5 DQ1 DQ3 DQ6 V V SSQ ...
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Table 3 Input/Output Functional Description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of ...
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CKE CAS RAS Mode 13 Registers 13 2 A0-A12, 15 BA0, BA1 2 Column-Address 11 Counter/Latch Figure 3 Block Diagram (64Mb u 4) Notes: 1. This Functional Block Diagram is intended to facilitate user understanding of ...
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CKE CAS RAS Mode 13 Registers 13 2 A0-A12, 15 BA0, BA1 2 Column-Address 10 Counter/Latch Figure 4 Block Diagram (32Mb u 8) Notes: 1. This Functional Block Diagram is intended to facilitate user understanding of ...
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CKE CAS RAS Mode 13 Registers 13 2 A0-A11, 15 BA0, BA1 2 Column-Address 9 Counter/Latch N Thi Figure 5 Block Diagram (16Mb u 16) Notes: 1. This Functional Block Diagram is ...
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Functional Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268, 435, 456 bits. The 256Mb DDR SDRAM is internally configured as a quad-bank DRAM. The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve ...
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Mode Register Definition The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The ...
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Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write ...
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Notes: 1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the ...
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Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register ...
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Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled via the bits shown in the Extended ...
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Commands Deselect The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to ...
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Auto Precharge Auto Precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write ...
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Table 5 Truth Table 1a: Commands Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge ...
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Operations 3.5.1 Bank/Row Activation Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened” (activated). This is accomplished via the Active command and addresses A0-A13, ...
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Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a Read command, as shown on The starting column and bank addresses are provided with the Read command and ...
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CK CK Read Command Address BA a,COL n DQS Read Command Address BA a,COL n DQS DQ DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length ...
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CK CK Read Command Address BAa, COL n DQS Read NOP Command Address BAa, COL n CL=2.5 DQS DQ DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 ...
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CK CK Read Command Address BAa, COL n BAa, COL x DQS Read Command Address BAa, COL n BAa, COL x DQS DQ DO a-n, etc. = data out from bank a, column n etc. n' etc. ...
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Note that part of the row precharge time is hidden during the access of the last data RP elements. In the case of a Read being executed to completion, a Precharge command issued at the ...
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CK CK Read Command Address BAa, COL n DQS Command Read Address BAa, COL n DQS a-n = data out from bank a, column a-b = data in to bank ...
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CK CK Read Command Address BA a, COL n DQS Read Command Address BA a, COL n DQS DQ DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 ...
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Writes Write bursts are initiated with a Write command, as shown on The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or disabled for that access. If Auto Precharge is ...
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CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 BA0, BA1 Figure 17 Write Command Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM HIGH DIS column address BA ...
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Write Command BA a, COL b Address DQS Write Command BA a, COL b Address DQS a-b = data in for bank a, column b. 3 subsequent elements of ...
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Write Command Address BAa, COL b t DQSS DQS Write Command Address BA, COL b DQS a-b = data in for bank a, column b, etc. 3 subsequent elements ...
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Write Command Address BAa, COL b t DQS a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. ...
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Write Command Address BAa, COL b t DQSS DQS Write Command Address BAa, COL b t (min) DQSS DQS a-b, etc. = data in for bank a, column b, ...
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Write Command Address BAa, COL b t DQSS DQS Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. 3 subsequent elements of ...
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Write Command BAa, COL b Address t DQSS DQS Write Command BAa, COL b Address DQS a-b = data in for bank a, column b. An interrupted burst is ...
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Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied ...
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Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied ...
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Command Write Address BA a, COL b t DQSS DQS Write Command BA a, COL b Address DQS a-b = data in for bank a, column b. 3 subsequent ...
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Write Command Address BA a, COL b t DQSS DQS Write Command BA a, COL b Address DQS a-b = data in for bank a, column b. An interrupted ...
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Write Command Address BA a, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 1 data element is written referenced from the first positive ...
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Write Command BA a, COL b Address DQS a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is ...
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Precharge The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( issued. Input A10 ...
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Power-Down Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row ...
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Table 7 Truth Table 2: Clock Enable (CKE) Current State CKE n-1 CKEn Previous Current Cycle Cycle Self Refresh L L Self Refresh L H Power Down L L Power Down L H All Banks Idle H L All Banks ...
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This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes ...
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Table 9 Truth Table 4: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Any Idle Row Activating Active, or ...
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Current state definitions: Idle: The bank has been precharged, and Row Active: A row in the bank has been activated, and accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not ...
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Simplified State Diagram Power Applied Power On Precharge PREALL MRS EMRS Active Power Down Write Write A Write A PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self ...
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Electrical Characteristics 4.1 Operating Conditions Table 11 Absolute Maximum Ratings Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply relative Voltage on ...
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Table 13 Electrical Characteristics and DC Operating Conditions Parameter Symbol Device Supply Voltage V DD Device Supply Voltage Output Supply Voltage DDQ V Output Supply Voltage DDQ V Supply Voltage, I/O Supply , SS Voltage V SSQ ...
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Normal Strength Pull-down and Pull-up Characteristics 1. The nominal pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve. 2. The full variation in driver pulldown ...
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Table 14 Normal Strength Pull-down and Pull-up Currents Voltage (V) Pulldown Current (mA) Nominal Nominal Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 ...
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Weak Strength Pull-down and Pull-up Characteristics 1. The weak pulldown V-I curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve 2. The weak pullup V-I curve for ...
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Table 16 Weak Strength Driver Pull-down and Pull-up Characteristics Voltage (V) Pulldown Current (mA) Nominal Nominal Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 ...
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AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I Specifications and Conditions, and Electrical Characteristics and AC Timing.) DD Notes All voltages referenced ...
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Table 18 AC Operating Conditions Parameter Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK ...
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Table 19 AC Timing - Absolute Specifications for DDR333 and DDR400B Parameter DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time DQS input low (high) pulse width (write cycle) DQS falling edge to CK ...
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Table 19 AC Timing - Absolute Specifications for DDR333 and DDR400B Parameter Exit self-refresh to read command Average Periodic Refresh Interval 2 0 DDQ (DDR400) ...
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Table 20 AC Timing - Absolute Specifications DDR266A, DDR266 and DDR200 Parameter Symbol Control and Addr. input t IPW pulse width (each input) DQ and DM input pulse t DIPW width (each input) t Data-out high-impedance HZ time from CK/CK ...
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Table 20 AC Timing - Absolute Specifications DDR266A, DDR266 and DDR200 Parameter Symbol Active to Read or Write t RCD delay Precharge command t RP period t Active to Autoprecharge RAP delay t Active bank A to Active RRD bank ...
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Table 21 I Conditions DD Parameter Operating Current: one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; ...
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Table 22 I Specifications DD Symbol DDR200 DDR266A -8 -7 typ. max. typ. max. typ 100 DD0 105 I 80 100 90 110 DD1 83 105 94 115 ...
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I Current Measurement Conditions Operating Current: One Bank Operation DD1 1. Only one bank is accessed with tRC(min) , Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = ...
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Timing Diagrams DQS Data In for column n. 3 subsequent elements of data in are applied in programmed order following DI n. Figure 38 Data Input (Write), Timing Burst Length = 4 DQS DQ ...
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Figure 40 Initialize and Mode Register Sets Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 70 02102004-TSR1-4ZWW Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 41 Power Down Mode Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 71 02102004-TSR1-4ZWW Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 42 Auto Refresh Mode Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 72 02102004-TSR1-4ZWW Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 43 Self Refresh Mode Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 73 02102004-TSR1-4ZWW Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 44 Read without Auto Precharge (Burst Length = 4) Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 74 09222003-A8PO-81BB Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 45 Read with Auto Precharge (Burst Length = 4) Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 75 09222003-A8PO-81BB Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 46 Bank Read Access (Burst Length = 4) Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 76 09222003-A8PO-81BB Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 47 Write without Auto Precharge (Burst Length = 4) Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 77 09222003-A8PO-81BB Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 48 Write with Auto Precharge (Burst Length = 4) Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 78 09222003-A8PO-81BB Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 49 Bank Write Access (Burst Length = 4) Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 79 09222003-A8PO-81BB Timing Diagrams Rev. 1.2, 2004-02 ...
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Figure 50 Write DM Operation (Burst Length = 4) Data Sheet HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM 80 09222003-A8PO-81BB Timing Diagrams Rev. 1.2, 2004-02 ...
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Package Outlines 3) ø0 Marking Ballside 2) A1 Marking Chipside 3) Dummy Pads without Ball 4) Bad Unit Marking (BUM) 5) Middle of Packages Edges Figure 51 P-TFBGA-60-2 (Plastic Thin Fine-Pitch Ball Grid Array Package) Data Sheet ...
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Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include plastic protrusion of 0.25 max. per side 3) Does not include dambar protrusion of 0.13 ...
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... Published by Infineon Technologies AG ...