HYB25D256160CC-6 Infineon Technologies AG, HYB25D256160CC-6 Datasheet
HYB25D256160CC-6
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HYB25D256160CC-6 Summary of contents
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... Edition 2006-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2006. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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HYB25D256[40/80/16]0CE(L) Revision History: 2006-02, Rev. 2.1 Previous Version: 2005-11, Rev. 2.0 Page Subjects (major changes since last revision) 11 Added HYB25D256160CEL-6 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Pin Configuration P-TFBGA-60 Top View, see the balls throught the package . . . . . . . . . . . . . . . 16 Figure 2 Pin Configuration P-TSOPII-66 ...
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List of Figures Figure 54 Package Outline of P-TFBGA-60-12 (non-green/green ...
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List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview This chapter lists all main features of the product family HYB25D256[16/40/80]0C[E/C/F/T](L) and the ordering information. 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with ...
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... HYB25D256800CT–6 ×8 HYB25D256800CTL–6 ×16 HYB25D256160CT–6 ×4 HYB25D256400CT–7 ×4 HYB25D256400CC–5 ×8 HYB25D256800CC–5 ×16 HYB25D256160CC–5 ×4 HYB25D256400CC–6 ×8 HYB25D256800CC–6 ×16 HYB25D256160CC–6 Data Sheet Clock CAS-RCD-RP Latencies (MHz) Latencies 3-3-3 200 2.5-3-3 2.5-3-3 166 2-3-3 143 3-3-3 200 2.5-3-3 2.5-3-3 166 ...
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Table 3 Ordering Information for Lead free (RoHS 2) Product Type Org. ×8 HYB25D256800CE–5A ×16 HYB25D256160CE–5A ×8 HYB25D256800CE–5 ×16 HYB25D256160CE–5 ×8 HYB25D256800CE–6 ×8 HYB25D256800CEL–6 ×16 HYB25D256160CE–6 ×16 HYB25D256160CEL-6 ×4 HYB25D256400CE–7 ×4 HYB25D256400CF–5 ×8 HYB25D256800CF–5 ×16 HYB25D256160CF–5 ×4 HYB25D256400CF–6 ×8 HYB25D256800CF–6 ...
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Pin Configuration The pin configuration of a DDR SDRAM is listed by function in Pin#/Buffer# column are explained in in Figure 1 and that of the TSOP package in Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type K3, ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type A8, 2 DQ0 I/O B7, 5 DQ1 I/O C7, 8 DQ2 I/O D7, 11 DQ3 I/O D3, 56 DQ4 I/O C3, 59 DQ5 I/O B3, 62 DQ6 I/O A2, ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type Data Mask ×16 organization F3, 47 UDM I F7, 20 LDM I Power Supplies V F1 REF V A9, B2, C8, PWR DDQ D2, E8 ...
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Table 4 Pin Configuration of DDR SDRAM Ball#/Pin# Name Pin Type E9 F7 F9, 14, 17, 19 25,43, 50, 53 Table 5 Abbreviations for Pin Type Abbreviation Description I Standard input-only pin. ...
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Figure 1 Pin Configuration P-TFBGA-60 Top View, see the balls throught the package Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM ...
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Figure 2 Pin Configuration P-TSOPII-66-1 Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 17 Pin Configuration Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Block Diagram 16 Mbit × 4 I/O × 4 Internal Memory Banks Figure 3 Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 18 Pin Configuration Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Block Diagram 8 Mbit × 8 I/O × 4 Internal Memory Banks Figure 4 Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 19 Pin Configuration Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Block Diagram 4 Mbit × 16 I/O × 4 Internal Memory Banks Figure 5 Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 20 Pin Configuration Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Functional Description The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. The 256 Mbit Double-Data-Rate SDRAM is internally configured as a quad-bank DRAM. The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to ...
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Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4- A6 specify the CAS latency, and A7-A12 specify the operating mode. The Mode Register must be loaded when all banks are idle, ...
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When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a ...
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Operating Mode The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register ...
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Field Bits Type DLL MODE [12: write only register bit 3.3.1 DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning ...
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Mode Register Set The mode registers are loaded via inputs A0-A12, BA0 and BA1. See mode register descriptions in The Mode Register Set command can only be issued when all banks are idle and no bursts are in progress. A ...
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Burst Terminate The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most recently registered Read command prior to the Burst Terminate command is truncated, as shown in Auto Refresh Auto Refresh is used during ...
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A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”. 7) This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW. 8) Internal ...
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CK CK ACT Command A0-A12 ROW BA x BA0, BA1 t t Figure 8 and Definition RCD RRD 3.5.2 Reads Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a ...
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In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as described above) provides the same operation that would result from the same Read burst with Auto Precharge enabled. The disadvantage of ...
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CK CK Command Read Address BA a,COL n DQS Command Read BA a,COL n Address DQS DQ DO a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). When burst length ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements ...
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CK CK Command Read Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n, etc. = data out from bank a, column n etc. n' etc. = odd or even complement of ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS DQ DO a-n = data out from bank a, column n. Cases shown are bursts of 8 terminated after 4 data ...
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CK CK Read Command Address BAa, COL n DQS Read Command Address BAa, COL n DQS a-n = data out from bank a, column a-b = data in to bank ...
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CK CK Read Command Address BA a, COL n DQS Read Command Address BA a, COL n DQS DQ DO a-n = data out from bank a, column n. Cases shown are either uninterrupted bursts of 4 ...
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DQS ( clock cycle), so most of the Write diagrams that follow are drawn for the two extreme cases (i. Figure 18 shows the two extremes of DQSS(max) no other commands have been ...
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CK CK CKE CS RAS CAS WE x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 A10 BA0, BA1 Figure 17 Write Command Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM HIGH DIS column address BA = ...
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CK CK Write Command BA a, COL b Address DQS Command Write BA a, COL b Address DQS a-b = data in for bank a, column b. 3 subsequent elements of data in ...
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Write Command Address BAa, COL b t DQS Write Command Address BA, COL b DQS a-b = data in for bank a, column b, etc. 3 subsequent elements of ...
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Write Command Address BAa, COL b DQS a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following DI a-b. 3 ...
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Write Command Address BAa, COL b DQS Write Command Address BAa, COL b t DQSS DQS a-b, etc. = data in for bank a, column b, etc. b', etc. ...
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Command Write Address BAa, COL b DQS Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. 3 subsequent elements of data in ...
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Command Write Address BAa, COL b DQS Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 4 ...
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Command Write Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied ...
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Write Command Address BAa, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied ...
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Write Command Address BA a, COL b t DQS Write Command Address BA a, COL b DQS a-b = data in for bank a, column b. 3 subsequent elements ...
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CK CK Write Command Address BA a, COL b DQS Command Write Address BA a, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, ...
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Write Command Address BA a, COL b DQS a-b = data in for bank a, column b. An interrupted burst is shown, 1 data element is written referenced from the first positive ...
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Write Command Address BA a, COL b DQS a-b = Data In for bank a, column b. An interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is ...
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Precharge The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( issued. Input A10 ...
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Power-Down Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row ...
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COMMAND n is the command registered at clock edge n, and ACTION result of COMMAND n. 4. All states and sequences not shown are illegal or reserved. Table 11 Truth Table 3: Current State Bank n ...
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The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when DDR ...
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This table applies when CKE n-1 was HIGH and CKE n is HIGH (see has been met (if the previous state was self refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is ...
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Input Clock Frequency Change DDR SDRAM Input clock frequency cannot be changed during normal operation. Clock frequency change is only permitted during Self Refresh or during Power Down. In the latter case the following conditions must be met: DDR ...
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Implified State Diagram Power Applied Power On Precharge PREALL MRS EMRS Write A PREALL = Precharge All Banks MRS = Mode Register Set EMRS = Extended Mode Register Set REFS = Enter Self Refresh REFSX = Exit Self Refresh ...
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Electrical Characteristics 4.1 Operating Conditions Table 14 Absolute Maximum Ratings Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply relative Voltage on supply relative to ...
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Table 16 Electrical Characteristics and DC Operating Conditions Parameter Symbol V Device Supply Voltage DD V Device Supply Voltage DD V Output Supply Voltage DDQ V Output Supply Voltage DDQ V Supply Voltage, I/O Supply , SS V Voltage SSQ ...
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Normal Strength Pull-down and Pull-up Characteristics The nominal pull-down - curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the V inner bounding lines of the - 2. The full variation in ...
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Table 17 Normal Strength Pull-down and Pull-up Currents Voltage (V) Pulldown Current (mA) Nominal Nominal Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 ...
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The weak pull-up - curve for DDR SDRAM devices is expected, but not guaranteed, to lie within the inner V I bounding lines of the - curve. 3. The full variation in driver pull-up current from minimum ...
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Table 19 Weak Strength Driver Pull-down and Pull-up Characteristics Voltage (V) Pulldown Current (mA) Nominal Nominal Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 ...
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AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating I Conditions, Specifications and Conditions, and Electrical Characteristics and AC Timing.) DD Notes V 1. All voltages referenced ...
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Table 20 AC Operating Conditions Parameter Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK ...
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Table 21 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol –5 t DQS falling edge hold time from CK (write cycle) t DQS falling edge to CK setup time (write cycle) t Clock Half Period t Data-out ...
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Table 21 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol –5 t Internal write to read command delay t Exit self-refresh to non-read command t Exit self-refresh to read command 1) 0 °C ≤ T ≤ 70 ...
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Table 22 AC Timing - Absolute Specifications for PC2700 (cont’d) Parameter DQS-DQ skew (DQS and associated DQ signals) st Write command to 1 DQS latching transition DQ and DM input setup time DQS falling edge hold time from CK (write ...
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Table 22 AC Timing - Absolute Specifications for PC2700 (cont’d) Parameter Write recovery time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command V = 2.5 V ± 0 +2.5 ...
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Table 23 I Conditions DD Parameter Operating Current: one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; ...
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I Table 24 Specification DD Symbol –5 DDR400B Typ. Max 100 DD4R 100 120 I 90 105 DD4W 100 130 I 140 190 DD5 I 1.4 3.0 DD6 — — I 210 250 DD7 210 250 1) Test ...
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I 4.5 Current Measurement Conditions DD Legend Activate Read Read with Autoprecharge Precharge NOP or DESELECT I : Operating Current: One Bank Operation DD1 1. General test condition a) Only ...
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Timing Diagrams The timing diagrams in this chapter give an overview of possible and recommended command sequences. 5.1 Write Command: Data Input Timing Figure 39 shows DQS versus DQ and DM Timing during write burst. DQS ...
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Read Command: Data Output Timing Figure 40 shows DQS versus DQ Timing during read burst. DQS DQ t (Data output hold time from DQS and t are only shown once and are shown referenced to different edges ...
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Initialization and Mode Register Set Command Figure 41 shows the timing diagram for initialization and Mode Register Sets. Figure 41 Initialize and Mode Register Sets Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 74 Timing Diagrams Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Power: Power Down Mode Command Figure 42 shows the timing diagram for Power Down Mode. Figure 42 Power Down Mode Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 75 Timing Diagrams Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Refresh: Auto Refresh Mode Command Figure 43 shows the timing diagram for Auto Refresh Mode. Figure 43 Auto Refresh Mode Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 76 Timing Diagrams Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Refresh: Self Refresh Mode Command Figure 44 shows the timing diagram for Self Refresh Mode. Figure 44 Self Refresh Mode Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 77 Timing Diagrams Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Read: Without Auto Precharge Command Figure 45 shows the timing diagram for Read without Auto Precharge. Figure 45 Read without Auto Precharge (Burst Length = 4) Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 78 Timing Diagrams Rev. 2.1, 2006-02 ...
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Read: With Auto Precharge Command Figure 46 shows the timing diagram for Read with Auto Precharge. Figure 46 Read with Auto Precharge (Burst Length = 4) Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 79 Timing Diagrams Rev. 2.1, 2006-02 ...
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Read: Bank Read Access Command Figure 47 shows the timing diagram for Read Bank Read Access. Figure 47 Bank Read Access (Burst Length = 4) Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 80 Timing Diagrams Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Write: Without Auto Precharge Command Figure 48 shows the timing diagram for Write without Auto Precharge. Figure 48 Write without Auto Precharge (Burst Length = 4) Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 81 Timing Diagrams Rev. 2.1, 2006-02 ...
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Write: With Auto Precharge Command Figure 49 shows the timing diagram for Write with Auto Precharge. Figure 49 Write with Auto Precharge (Burst Length = 4) Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 82 Timing Diagrams Rev. 2.1, 2006-02 ...
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Write: Bank Write Access Command Figure 50 shows the timing diagram for Bank Write Access. Figure 50 Bank Write Access (Burst Length = 4) Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 83 Timing Diagrams Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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Write: DM Operation Figure 51 shows the timing diagram for DM Operation. Figure 51 Write DM Operation (Burst Length = 4) Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 84 Timing Diagrams Rev. 2.1, 2006-02 08012003-8754-PAQX ...
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System Characteristics for DDR SDRAMs The following specification parameters are required in systems using DDR400, DDR333 & DDR266 devices to ensure proper system performance. These characteristics are for system simulation purposes and are not subject to production test - ...
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Output Slew Rate Characteristrics (×4, ×8 Devices only) Table 29 Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Pullup Slew Rate 1.2 – 2.5 Pulldown Slew Rate 1.2 – 2.5 Table 30 Output Slew Rate Characteristics (×16 Devices only) Slew ...
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Package Outlines There are two package types used for this product family each in lead-free and lead-containing assembly: • P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package Table 32 TFBGA Common Package Properties (non-green/green) Description Ball Size Recommended Landing ...
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Lead 1 Figure 55 Package Outline of P-TSOPII-66-1 (non-green/green) Data Sheet HYB25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM Gage Plane 0.65 Basic 0.805 REF +0.1 0.1 0.35 -0.05 Seating Plane 22.22 ±0.13 88 Package Outlines 10.16 ±0.13 0.5 ±0.1 11.76 ±0.2 GPX09261 ...
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... Published by Infineon Technologies AG ...