HYB25L256160AF-7.5 Infineon Technologies AG, HYB25L256160AF-7.5 Datasheet
HYB25L256160AF-7.5
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HYB25L256160AF-7.5 Summary of contents
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2. Memory Products D a ...
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... Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Edition 2003-04-16 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2003. © ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Mobile-RAM Mobile-RAM 1 Overview 1.1 Features • 16 Mbits 16 organisation • Fully synchronous to positive clock edge • Four internal banks for concurrent operation • Data mask (DM) for byte control with write and read data • Programmable ...
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A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. The Mobile-RAM is housed in a FBGA “chip-size” package. ...
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Pin Configuration 1 2 VSS DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 NC UDQM CLK A12 A11 A8 A7 VSS A5 Figure 1 Pin Configuration P-TFBGA-54 (16 Mb Data Sheet 3 VSSQ A VDDQ B VSSQ C VDDQ ...
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Table 3 Input/Output Signals Pin Symbol Type Polarity Function F2 CLK Input Positive Edge F3 CKE Input Active High G9 CS Input Active Low F8 RAS Input Active Low F7 CAS BA1 Input Active High G7 BA0 ...
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Table 3 Input/Output Signals (cont’d) Pin Symbol Type Polarity Function A2 DQ15 Input/ Active Output High B1 DQ14 B2 DQ13 C1 DQ12 C2 DQ11 D1 DQ10 D2 DQ9 E1 DQ8 E9 DQ7 D8 DQ6 D9 DQ5 C8 DQ4 C9 DQ3 ...
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Column Address Counter Row Decoder Memory Array Bank 0 8192 x 512 x 16 Bit Input Buffer DQ0 - DQ15 Figure 2 Block Diagram (16 Mbit Note: 1. This Functional Block Diagram is intended to facilitate user understanding of the ...
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Functional Description The 256-Mbit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized as 4 banks 4 Mbit 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves high speed data transfer rates by ...
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MR Mode Register Definition BA1 BA0 A12 A11 0 0 reg. addr Field Bits Type Description BL [2:0] w Burst Length Number of sequential bits per DQ related to one read/write command; see Note: All other bit combinations are RESERVED. ...
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Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined ...
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Extended Mode Register The Extended Mode Register controls functions beyond those controlled by the Mode Register. These additional functions are unique to Mobile RAMs and includes a refresh period field (TCSR) for Temperature Compensated Self Rrefresh and a Partial ...
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EMR Extended Mode Register Definition BA1 BA0 A12 A11 1 0 reg. addr Field Bits Type PASR [2:0] w TCSR [4:3] w MODE [12: All other bit combinations are RESERVED. Data Sheet (BA[1: A10 ...
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Commands All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Table 5 Operation ...
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Deselect The Deselect function prevents new commands from being executed by the 256-Mbit Mobile-RAM. Operations already in progress are not affected. No Operation (NOP) The No Operation (NOP) command is used to perform a NOP to a 256-Mbit Mobile-RAM. This ...
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The Write command is used to initiate a burst write access to an active (open) row. The value on the BA1 and BA0 inputs selects the bank, and the address provided on inputs A9-A0 for x16 selects the starting column ...
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Auto Refresh Auto Refresh is used during normal operation of the 256-Mbit Mobile-RAM and is analogous to CAS Before RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent must be issued each time a refresh is ...
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Simplified State Diagram Power On Power applied Precharge All PREALL Mode Register Set Clock CKEL Suspend CKEH WRITE WRITEA Clock CKEL Suspend CKEH WRITEA PRE PREALL = Precharge All Banks REFS = Enter Self Refresh REFSX = Exit Self ...
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Electrical Characteristics 4.1 Operating Conditions Table 7 Absolute Maximum Ratings Parameter V Voltage on I/O pins relative Voltage on I/O pins relative Voltage on supply relative Voltage on supply relative ...
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Table 9 Input and Output Capacitances Parameter Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance These values are guaranteed by design and are tested on a sample base only ...
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Table 10 AC Timing Characteristics Parameter Refresh Cycle Refresh period Self refresh exit time Read Cycle Data output hold time Data output from high to low impedance Data output from low to high impedance DQM data output disable latency Write ...
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Current Specification I Table 11 Specification and Conditions DD Parameter Operating current Single bank access cycles Precharge standby current Power down mode Precharge standby current Non power down mode Non operating current Active state of 1 upto 4 banks, ...
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I Table 12 Programmable Self Refresh Current DD6 Parameter Self refresh current Self refresh mode, full array activations = all banks Self refresh current Self refresh mode, half array activations = bank Self refresh current Self refresh ...
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Timing Diagrams Figure 5 Bank Activate Command Cycle Figure 6 Burst Read Operation Figure 7 Read Interrupted by a Read Read to Write Interval – Figure 8 Read to Write Interval – Figure 9 Minimum Read to Write Interval ...
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T0 T1 CLK Bank B Address Row Addr. Bank B Command NOP Activate "H" or "L" Figure 5 Bank Activate Command Cycle (Burst Length = 4, CAS latency = CLK Command Read ...
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Length = 4, CAS latency = CLK Command Read A Read B CAS latency = DQ’s CK2 CAS latency = DQ’s CK3 Figure 7 Read Interrupted by a Read ...
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Length = 4, CAS latency = CLK DQM Command NOP NOP CAS latency = DQ’s CK2 "H" or "L" Figure 9 Minimum Read to Write Interval Data Sheet ...
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Length = 4, CAS latency = CLK DQM Command NOP Read A CAS latency = DQ’s CK2 CAS latency = DQ’s CK3 "H" or "L" Figure 10 Non-Minimum Read ...
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Write and Read Interrupt (Burst Length = 4, CAS latency = CLK Command NOP Write A 1 Clk Interval DQ’s DIN A0 Figure 12 Write Interrupted by a Write (Burst Length = 4, CAS latency = ...
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Burst Write and Read with Auto Precharge (Burst Length = 2, CAS latency = CAS Latency = ...
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AC Parameters CK2 CKS ...
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CLK CK2 t CL CKE CKS RAS CAS RAx t AS Addr. RAx DQM Hi-Z DQ Activate Command Bank A Figure 17 AC ...
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CLK CKE t CS RAS CAS dres Addr ...
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CLK CKE High Level is required CS RAS CAS Addr. DQM t RP Hi-Z DQ Precharge Command All Banks Inputs must be 1st Auto Refresh stable for 200 s Command Figure 19 ...
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Clock Suspension (Using CKE CLK t CK2 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A Figure 20 Clock Suspension During Burst ...
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CLK t CK3 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ Activate Read Command Command Bank A Bank A Figure 21 Clock Suspension During Burst Read CAS Latency = ...
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CLK t CK2 CKE CS RAS CAS RAx Addr. RAx CAx DQM Hi-Z DQ DAx0 Activate Clock Command Suspend Bank A 1 Cycle Write Command Bank A Figure 22 Clock Suspension During ...
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CLK t CK3 CKE CS RAS CAS WE BA A8/AP RAx Addr. RAx CAx DQMx Hi-Z DQ DAx0 Activate Command Suspend Bank A Write Command Bank A Figure 23 Clock Suspension During Burst Write CAS ...
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CLK t t CK2 CKE CS RAS CAS RAx Addr. RAx DQM Hi-Z DQ Activate Active Command Standby Bank A Clock Suspend Clock Suspend Mode Entry Mode Exit Figure 24 Power Down ...
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CLK CKE t CKS CS RAS CAS Addr. DQM Hi-Z DQ All Banks Self Refresh must be idle Entry Figure 25 Self Refresh (Entry and Exit) Data Sheet ...
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CK2 ...
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Random Column Read (Page within same Bank CLK t CK2 CKE CS RAS CAS RAw Addr. RAw CAw DQM Activate Read Command Command Bank A Bank A Figure 27 CAS ...
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CLK t CK3 CKE CS RAS CAS RAw Addr. RAw CAw DQM Activate Read Command Command Bank A Bank A Figure 28 CAS Latency = 3 Data Sheet T5 ...
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Random Column write (Page within same Bank CK2 RBw ...
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CLK t CK3 CKE CS RAS CAS RBz Addr. RBz CBz DQM DBw0 Activate Write Command Command Bank B Bank B Figure 30 CAS Latency = 3 Data Sheet ...
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Random Row Read (Interleaving Banks) with Precharge CK2 ...
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CLK t CK3 CKE High CS RAS CAS RBx Addr. RBx CBx t RCD DQM Hi-Z DQ Activate Read Command Command Bank B Bank B Figure 32 CAS Latency = 3 Data ...
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Random Row Write (Interleaving Banks) with Precharge CK2 H igh ...
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CLK t CK3 CKE High CS RAS CAS RAx Addr. RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 Activate Write Command Command Bank A Bank A Figure 34 CAS Latency = ...
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Precharge termination of a Burst CLK t CK2 CKE High CS RAS CAS RAx Addr. RAx CAx DQM DAx0 DAx1 DAx2 Activate Write Command Command Bank A Bank A ...
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Deep Power Down Mode CLK CKE CS WE CAS RAS Addr. DQM DQ input DQ output Normal Mode Figure 36 Deep Power Down Mode Entry Note: The deep power down mode has to be maintained for a minimum of 100µs. ...
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CLK RAS CAS WE 200 s Deep Power Do wn All banks prec harge exi t Figure 37 Deep Power Down Exit Note: The deep power down mode is exited by asserting CKE high. After the exit, ...
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Package Outline P-TFBGA-54 (Plastic Thin Small Outline Package Type II) tolerance 0.1mm for length and width Figure 38 Package Outline You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. ...
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... Published by Infineon Technologies AG ...