HYB39L256160AC-7.5 Infineon Technologies AG, HYB39L256160AC-7.5 Datasheet
HYB39L256160AC-7.5
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HYB39L256160AC-7.5 Summary of contents
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... Auto Refresh (CBR) and Self Refresh operation are supported. The device operates with a single 3.3V ± 0.3V power supply. Compared to conventional SDRAM the self-refresh current is further reduced. The Mobile-RAM devices are available in FBGA “chip-size” or TSOPII packages. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM • Automatic and Controlled Precharge Command • Programmable Burst Length and full page • ...
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... WE Write Enable A0 - A12, Row Addresses Column Addresses BA0, BA1 Bank Select INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Description 133 MHz 4B ´ 4M x16 LP-SDRAM 100 MHz 4B ´ 4M x16 LP-SDRAM 133 MHz 4B ´ 4M x16 LP-SDRAM 100 MHz 4B ´ 4M x16 LP-SDRAM DQ Data Input/Output LDQM, UDQM ...
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... DQ13 DDQ V DQ12 DQ11 SSQ V DQ10 DQ9 DDQ V DQ8 NC SS UDQM CLK CKE A12 A11 INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM DQ0 DDQ DQ2 DQ1 SSQ V C DQ4 DQ3 DDQ V D DQ6 DQ5 SSQ V E ...
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... A10 TSOPII-54 (10. 22.22 mm, 0.8 mm pitch) INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 16Mb N.C. DQ7 DQ15 SSQ SSQ SSQ 51 N.C. N.C. ...
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... Bank 0 Bank 1 8192 x 512 8192 x 512 x 16 Bit x 16 Bit Input Buffer Output Buffer DQ0 - DQ15 Block Diagram: 16Mb x16 SDRAM ( addressing) INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Row Addresses A0 - A12, BA0, BA1 Row Address Refresh Counter Buffer Row Row Decoder ...
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... BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input Level – Bank Select Inputs. Selects which bank active. DQx Input Level – Data Input/Output pins operate in the same manner as on Output conventional DRAMs. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM (Page Length: 512bits) 6 2002-12-20 ...
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... SDRAM. V Supply – – Power and ground for the input buffers and the core logic Supply – – Isolated power supply and ground for the output buffers to DDQ V provide improved noise immunity. SSQ INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 7 2002-12-20 ...
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... This is the state of the banks designated by BA0, BA1 signals. 4. Address Input for Mode Set (Mode Register Operation) 5. Power Down Mode can not be entered during a burst cycle. When this command is asserted during a burst cycle the device enters Clock Suspend Mode. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM CKEn DQM BA0 ...
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... Reserved Reserved Reserved INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Address Bus (Ax) CAS Latency BT Burst Length Mode Register (Mx) Burst Type Mode M3 Type Burst Read/ 0 Sequential Burst Write 1 Interleave Burst Read/ ...
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... I/O organisation and column addressing. Full page burst operation do not self terminate once the burst length has been reached. In other words, unlike burst length and 8, full page burst continues until it is terminated using another command. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM t , from the RAS timing used to define either ...
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... The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock edge. The mode restores word line after the refresh and no external precharge INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Interleave Burst ...
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... If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The Mobile-RAM automatically enters the precharge operation after time) following the last data in. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM t delay is required prior to RC ...
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... Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM from the last data out to apply the precharge command. 13 ...
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... V may overshoot to V +2.0V for pulse width of <4ns with IH DDQ V may undershoot to –2.0V for pulse width <4.0ns with IL Pulse width measured at 50% points with amplitude measured peak to DC reference. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Symbol Limit Values Unit Notes min. max. V 2.7 3.6 V ...
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... Input signals are changed once during maximum operation frequency, these current values are reduced. 4. These parameters are measured with continuous data stream during read access and all DQ toggling and used and the V current is excluded. DDQ INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Symbol Values min. max ...
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... Power Down Mode Entry Time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Activate(a) to Activate(b) Command Period CAS(a) to CAS(b) Command Period Refresh Cycle INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Symbol Values Unit -7.5 -8 min. max. min. max. 7.5 – ...
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... Read Cycle Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency Write Cycle Write Recovery Time DQM Write Mask Latency INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Symbol Values Unit -7.5 -8 min. max. min. max. t – ...
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... For all memory operation frequencies higher than 72MHz two clock cycles for INFINEON recommends to use two clock cylces for the write recovery time in all applications. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM with the AC output load circuit ...
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... Random Column Write ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 19 2002-12-20 ...
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... Length = 4, CAS latency = CLK Command Read A NOP NOP CAS latency = 2 DOUT DQ’s CK2 CAS latency = DQ’s CK3 INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Bank B Bank A Col. Addr. Row Addr. t RRD Write B Bank A NOP with Auto Activate Precharge ...
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... Length = 4, CAS latency = CLK Minimum delay between the Read and Write Commands = cycles DQMx Command NOP Read A NOP DQ’s "H" or "L" INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM NOP NOP NOP NOP NOP DOUT B3 DOUT A0 DOUT B0 DOUT B1 ...
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... CLK DQM Command NOP Read A NOP CAS latency = DQ’s CK2 CAS latency = DQ’s CK3 "H" or "L" INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM DQW t DQZ 1 Clk Interval NOP Read A Write A NOP NOP Must be Hi-Z before the Write Command ...
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... Length = 4, CAS latency = CLK Command NOP Write A NOP DQ’s DIN A0 DIN A1 The first data element and the Write are registered on the same clock edge. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM NOP NOP NOP NOP NOP don’t care DIN A2 DIN A3 Extra data is ignored after termination of a Burst ...
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... Read B CAS latency = 2 DIN A0 don’t care t , DQ’s CK2 CAS don’t care latency = 3 DIN DQ’s CK3 Input data for the Write is ignored. INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM NOP NOP NOP NOP NOP DIN B1 DIN B2 DIN ...
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... ith DOUT INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM ...
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... W rite w ith arge A uto P rec INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM ...
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... AH AP RAx t AS Addr. RAx CAx t RRD DQM t RCD Hi-Z DQ Activate Read Command Command Bank A Bank A INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 2, CAS Latency = T10 T11 t CKH Begin Auto Precharge Bank B RBx RAy RBx RBx RAy t RAS t RC ...
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... Addr. P rec INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM ...
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... AP Addr. DQM t RP Hi-Z DQ Precharge Command All Banks Inputs must be 1st Auto Refresh stable for 200 Command µs INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 2 Clock min. Address Key t RC 8th Auto Refresh ...
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... CSL t CSL Hi-Z DQ Ax0 Ax1 Activate Read Clock Command Command Suspend Bank A Bank A 1 Cycle INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 4, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CSL Ax2 Ax3 ...
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... Addr. RAx CAx t DQM CSL Hi-Z DQ Ax0 Activate Read Command Command Suspend Bank A Bank A 1 Cycle INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 4, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t CSL t CSL t HZ ...
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... DAx1 DAx2 Activate Clock Clock Command Suspend Suspend Bank A 1 Cycle 2 Cycles Write Command Bank A INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 4, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAx3 Clock Suspend ...
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... DAx0 DAx1 Activate Clock Clock Command Suspend Suspend Bank A 1 Cycle 2 Cycles Write Command Bank A INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 4, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAx2 DAx3 Clock ...
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... Active Read Clock Mask Command Standby Command Bank A Bank A Clock Suspend Clock Suspend Mode Entry Mode Exit INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 4, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t HZ ...
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... BS AP Addr. t SREX DQM Hi-Z DQ All Banks Self Refresh must be idle Entry Self Refresh Exit Command issued (async.) INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t CKS t RC Begin Self Refresh ...
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... Inte rval i recharge A uto R efresh and and anks INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM B u rst L ength = Latency = ...
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... Aw0 Aw1 Aw2 Aw3 Activate Read Read Command Command Command Bank A Bank A Bank A INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 4, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 RAz CAy RAz CAz Ax0 Ax1 Ay0 ...
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... CAx DQM Aw0 Aw1 Activate Read Read Command Command Command Bank A Bank A Bank A INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 4, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 RAz CAy RAz Aw2 Aw3 Ax0 Ax1 ...
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... W rite INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM ...
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... Z DQ DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 Activate Write Write Command Command Command Bank B Bank B Bank B INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 4, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 RBz CBy RBz DBy0 DBy1 ...
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... A ctiva ank B B ank B B ank A INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM B u rst ...
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... RCD DQM Hi-Z DQ Bx0 Bx1 Bx2 Activate Read Activate Command Command Command Bank B Bank B Bank A INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 8, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RBy CAx RBy CBy t ...
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... A c tiv INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM ...
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... Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 Activate Write Activate Command Command Command Bank A Bank A Bank B INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 8, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 RAy CBx RAy CAy ...
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... Command Command Command Bank A Bank A Bank A Precharge Termination Activate of a Write Burst. Command Write Data is masked. Bank A INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM Burst Length = 8 or Full Page, CAS Latency = T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 RAz ...
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... Package Outline 1 Plastic Package, P-TFBGA-54 0.8 mm ball pitch, 3 depopulated rows) Thin Fine pitch Ball Grid Array, SMD tolerance ± 0.1mm for length and width INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM 46 2002-12-20 ...
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... Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side 2) Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM ±5˚ 2) 10.16 ±0.13 0.5 ±0.1 11.76 ±0.2 ±5˚ 0.1 54x 0 ...
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... SPT03919-3 p. 46: TFBGA package outline moved to end of data sheet p. 46: TFBGA outline now eps format, added “tolerance ± 0.1mm for length and width” p. 47: TSOP package outline moved to end of data sheet INFINEON Technologies AG HYB39L256160AC/T 256MBit 3.3V Mobile-RAM ...