K4D553235F-GC33 Samsung, K4D553235F-GC33 Datasheet

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K4D553235F-GC33

Manufacturer Part Number
K4D553235F-GC33
Description
Manufacturer
Samsung
Datasheet

Specifications of K4D553235F-GC33

Case
TSOP

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K4D553235F-GC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
Samsung Electronics reserves the right to change products or specification without notice.
256Mbit GDDR SDRAM
Revision 1.6
March 2005
- 1 -
256M GDDR SDRAM
Rev 1.6 (May 2005)

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K4D553235F-GC33 Summary of contents

Page 1

... K4D553235F-GC 256Mbit GDDR SDRAM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. ...

Page 2

... Added a couple of note below AC timing table. Revision 1.1 (December 14, 2004) • Removed K4D553235F-GC20 from the specification. • Dualized the 400MHz part’s part number by its operating voltage. Newly added -GJ25 operating voltage is equal to 2.0V(typical) which is in mass pro- duction now. The 400MHz part with VDD & VDDQ= 1.8V(typical) which represented as -GC25 will be available by the 2nd quarter of ’05 • ...

Page 3

... Differential clock input ORDERING INFORMATION Part NO. K4D553235F-GC25 K4D553235F-GC2A K4D553235F-GC33 * K4D553235F-VC is the Lead Free package part number. GENERAL DESCRIPTION FOR 2M x 32Bit x 4 Bank DDR SDRAM The K4D553235F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized 2,097,152 words by 32 bits, fabricated with SAMSUNG extremely high performance ...

Page 4

... K4D553235F-GC PIN CONFIGURATION DQS0 DM0 VSSQ C DQ4 VDDQ NC D DQ6 DQ5 VSSQ E DQ7 VDDQ VDD F DQ17 DQ16 VDDQ G DQ19 DQ18 VDDQ H DQS2 DM2 NC J DQ21 DQ20 VDDQ DQ22 DQ23 VDDQ K CAS WE VDD L RAS BA0 N NOTE: 1. RFU1 is reserved for A12 2 ...

Page 5

... K4D553235F-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK*1 Input CKE Input CS Input RAS Input CAS Input WE Input DQS ~ DQS Input/Output Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply ...

Page 6

... K4D553235F-GC BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 32 Intput Buffer CK, CK Data Input Register Serial to parallel 64 2Mx32 2Mx32 2Mx32 2Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...

Page 7

... K4D553235F-GC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...

Page 8

... K4D553235F-GC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...

Page 9

... K4D553235F-GC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...

Page 10

... K4D553235F-GC ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...

Page 11

... K4D553235F-GC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I CC2 in Power-down mode Precharge Standby Current I CC2 in Non Power-down mode Active Standby Current I CC3 power-down mode Active Standby Current I CC3 in Non Power-down mode ...

Page 12

... K4D553235F-GC AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Note case of differential clocks(CK and CK ), input reference voltage for clock and CK’s crossing point. ...

Page 13

... K4D553235F-GC AC CHARACTERISTICS (I) Parameter CL=3 CL=4 CK cycle time CL=5 CL=6 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble ...

Page 14

... K4D553235F-GC Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...

Page 15

... K4D553235F-GC AC CHARACTERISTICS (II) Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Pre- charge ...

Page 16

... K4D553235F-GC AC CHARACTERISTICS (II) K4D553235F-GC25 Frequency Cas Latency 400MHz ( 2.5ns ) 5 K4D553235F-GC2A Frequency Cas Latency 350MHz ( 2.86ns ) 5 300MHz ( 3.3ns ) 4 K4D553235F-GC33 Frequency Cas Latency 300MHz ( 3.3ns ) 4 tRC tRFC tRAS tRCDRD tRCDWR tRC tRFC tRAS tRCDRD tRCDWR tRC tRFC tRAS ...

Page 17

... K4D553235F-GC Simplified Timing( CK, CK BA[1:0] BAa BAa Ra Ra A8/AP ADDR (A0~A7 A9,A10) WE DQS DQ Da0 Da1 Da2 Da3 DM COMMAND ACTIVEA WRITEA tRCD tRAS Normal Write Burst (@ BL= BAa BAa Ra Ra PRECH ACTIVEA tRP tRC tRRD Multi Bank Interleaving Write Burst ...

Page 18

... K4D553235F-GC PACKAGE DIMENSIONS (144-Ball FBGA) 0.45 0.35 1.40 A1 INDEX MARK 12.0 <Top View> 0.8x11=8.8 0.10 Max 0 ± 0. ± 0.05 Max <Bottom View> 256M GDDR SDRAM 12.0 A1 INDEX MARK 0.8 0.40 0.40 Rev 1.6 (May 2005) Unit : mm ...

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