K4J55323QI-BC14 Samsung, K4J55323QI-BC14 Datasheet
K4J55323QI-BC14
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K4J55323QI-BC14 Summary of contents
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... K4J55323QI 256Mbit GDDR3 SDRAM Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4J55323QI Revision History Revision Month Year 0.0 March 2006 0.1 November 2006 1.0 January 2007 1.1 February 2007 1.2 March 2007 1.3 May 2007 - Target Spec - Changed speed bin organization - Final Spec - Added current data and IBIS data - Added Power dissipation data on page 48. - Added comment on page 23. ...
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... ORDERING INFORMATION Part NO. K4J55323QI-BJ1A K4J55323QI-BJ11 K4J55323QI-BC12 K4J55323QI-BC14 3.0 GENERAL DESCRIPTION FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM The K4J55323QI is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized 2,097,152 words by 32 bits, fab- ricated with SAMSUNG high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor- ’ ...
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... K4J55323QI 4.0 PIN CONFIGURATION Normal Package (Top View VDDQ VDD B VSSQ DQ0 C VDDQ DQ2 D VSSQ WDQS0 E VDDQ DQ4 F VDD DQ6 G VSS VSSQ H VREF A1 J VSSA RFU1 K VDDA A10 L VSS VSSQ M VDD DQ24 N VDDQ DQ26 P VSSQ WDQS3 R VDDQ DQ28 T VSSQ DQ30 V VDDQ ...
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... K4J55323QI 5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive CK, CK Input edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CK, CK should be maintained stable, except self-refresh mode Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers ...
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... K4J55323QI 6.0 BLOCK DIAGRAM (2Mbit x 32I Bank) Bank Select iCK ADDR LCKE LRAS LCBR iCK CKE * iCK : internal clock WDQS Input Buffer Input Buffer Data Input Register Serial to parallel Column Decoder Latency & Burst Length ...
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... K4J55323QI 7.0 FUNCTIONAL DESCRIPTION 7.1 Simplified State Diagram Power Applied Power On Precharge PREALL MRS EMRS Write A REFS REFSX MRS Idle CKEH Active ACT Power Down CKEH CKEL Row Active Write Write A Read A Write Read Write Read A PRE Write A PRE PRE Precharge PRE PREALL ...
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... K4J55323QI 7.2 INITIALIZATION GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. 1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined) - Apply VDD and VDDQ simultaneously - Apply VDDQ before Vref. ( Inputs are not recognized as valid until after V ...
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... K4J55323QI 7.3 MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS latency, address- ing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for the proper opera- tion ...
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... K4J55323QI PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and Vss. The value of the resistor must be six times of the desired output impedance. ...
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... K4J55323QI CAS LATENCY (READ LATENCY) The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 7~12 clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m ...
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... K4J55323QI WRITE LATENCY The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data. The latency can be set from clocks depending in the operating frequency and desired current draw. When the write latencies are set clocks, the input receivers never turn off when the WRITE command is registered ...
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... K4J55323QI TEST MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8- A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0- A6 and A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden from the user ...
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... K4J55323QI 7.4 EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is writ- ten by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
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... K4J55323QI DLL ENABLE/DISABLE The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal oper- ation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 20K clock cycles must occur before an any command can be issued. ...
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... K4J55323QI 7.5 MANUFACTURERS VENDOR CODE AND REVISION IDENTIFICATION The Manufacturers Vendor Code selected by issuing a EXTENDED MODE REGISTER SET command with bits A10 set to one, and bits A0-A9 and A11 set to the desired values. When the V function is enabled the GDDR3 SDRAM will provide its manufacturers ...
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... K4J55323QI 7.6 Clock frequency change sequence during the device operation Both existing tCK and desired tCK are in DLL-On mode - Change frequency from existing frequency to desired frequency - Issue Precharge All Banks command - Issue MRS command to reset the DLL while other fields are valid and required 20K tCK to lock the DLL - Issue Precharge All Banks command ...
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... K4J55323QI 7.7 BOUNDARY SCAN FUNCTION GENERAL INFORMATION The 256Mb GDDR3 incorporates a modified boundary scan test mode as an optional feature. This mode doesn’t operate in accor- dance with IEEE Standard 1149.1 - 1990. To save the current GDDR3 ball-out, this mode will scan parallel data input and output and the scanned data through WDQS0 pin controlled by an add-on pin, SEN which is located 136 ball package ...
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... K4J55323QI BOUNDARY SCAN EXIT ORDER BIT# BALL BIT D-11 24 *Note : 1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. ...
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... K4J55323QI SCAN DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS PARAMETER/CONDITON Input High (Logic 1) Voltage Input Low (Logic 0) Voltage *Note : 1. The parameter applies only when SEN is asserted. 2. All voltages referenced to GND. SCK SEN LOW SSH SOE Pins under Test SCK SEN SSH SOE SOUT ...
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... K4J55323QI SCAN AC ELECTRICAL CHARACTERISTICS PARAMETER/CONDITON Clock Clock cycle time Scan Command Time Scan enable setup time Scan enable hold time Scan command setup time for SSH, SOE# and SOUT Scan command hold time for SSH, SOE# and SOUT Scan Capture Time ...
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... K4J55323QI 7.8 Mirror Function The GDDR3 SDRAM provides a mirror function (MF) ball to change the physical location of the control lines and all address lines which helps to route devices back to back. The MF ball will affect RAS, CAS, WE, CS and CKE on balls H3, F4, H9, F9 and H4 respectively and A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, BA0 and BA1 on balls K4, H2, K3, M4, K9, H11, K10, L9, K11, M9, K2, L4, G4 and G9 respectively and only detects a DC input ...
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... K4J55323QI 7.9 OPERATIONS 7.9.1 BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the t specification ...
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... K4J55323QI 7.9.2 READs READ bursts are initiated with a READ command, as below figure. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst after t the generic READ commands used in the following illustrations, auto precharge is dis- abled ...
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... K4J55323QI Data Output Timing ( DQSQ CK# CK 1.6 RDQS DQ(Last data valid) DQ(First data no longer valid) 5 All DQs and RDQS, collectively Data Output Timing ( DQSQ CK# CK 1.6 RDQS 5 All DQs and RDQS, collectively 1.6 RDQS 5 All DQs and RDQS, collectively Note : 1. t represents the skew between the 8 DQ lines and the respective RDQS pin. ...
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... K4J55323QI READ Burst T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS DQ T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS n=data-out from column n. NOTE : 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Shown with nominal t 5 ...
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... K4J55323QI Consecutive READ Bursts T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS ( data-out from column n (or column b). NOTE : 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Three subsequent elements of data-out appear in the programmed order following DQ b. ...
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... K4J55323QI Nonconsecutive READ Bursts T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS DQ T0 /CK CK COMMAND READ Bank a, ADDRESS Col RDQS ( data-out from column n (or column b). NOTE : 2. Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following DQ n. ...
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... K4J55323QI Random READ Accesses T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS DQ T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS ( data-out from column n (or column x or column x or column b or column g). NOTE : 2. Burst length = 4 3. n’ b’ or g’ indicates the next data-out following respectively 4 ...
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... K4J55323QI READ to WRITE T0 /CK CK COMMAND READ Bank ADDRESS Col n RDQS WDQS Termination data-out from column n. NOTE : data-in from column b. 3. Burst length = 4 4. One subsequent element of data-out appears in the programmed order following Data-in elements are applied following the programmed order. ...
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... K4J55323QI READ to PRECHARGE T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS DQ T0 /CK CK COMMAND READ Bank a, ADDRESS Col n RDQS DQ NOTE ( data-out from column n (or column b Burst length = 4 3. Three subsequent elements of data-out appear in the programmed order following Three subsequent elements of data-out appear in the programmed order following DQ b. ...
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... K4J55323QI 7.9.3 WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure. The starting column and bank addresses are provided with the WRITE command, and auto pre- charge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled ...
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... K4J55323QI WRITE Burst T0 /CK CK COMMAND WRITE Bank a, ADDRESS Col b t (NOM) t DQSS DQSS WDQS (MIN) t DQSS DQSS WDQS (MAX) t DQSS DQSS WDQS DQ DM NOTE data-in for column Three subsequent elements of data-in are applied in the programmed order following DI b. ...
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... K4J55323QI Consecutive WRITE to WRITE T0 T1 CK# CK COMMAND WRITE NOP Bank ADDRESS Col b t (NOM) DQSS WDQS etc. = data-in for column b, etc. NOTE : 2. Three subsequent elements of data-in are applied in the programmed order following Three subsequent elements of data-in are applied in the programmed order following DI n. ...
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... K4J55323QI Nonconsecutive WRITE to WRITE T0 T1 /CK CK COMMAND WRITE NOP Bank, ADDRESS Col b t (NOM) DQSS WDQS etc. = data-in for column b, etc. NOTE : 2. Three subsequent elements of data-in are applied in the programmed order following Three subsequent elements of data-in are applied in the programmed order following DI n. ...
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... K4J55323QI Random WRITE Cycles T0 /CK CK COMMAND WRITE NOP Bank ADDRESS Col b t (NOM) DQSS WDQS DQ DM NOTE etc. = data-in for column b, etc etc. = the next data - in following DI b. etc., according to the programmed burst order. 3. Programmed burst length = 4 cases shown. ...
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... K4J55323QI WRITE to READ T0 T1 /CK CK COMMAND WRITE NOP Bank ADDRESS Col (NOM) DQSS DQSS WDQS DQ DM RDQS t t (MIN) DQSS DQSS WDQS DQ DM RDQS t t (MAX) DQSS DQSS WDQS DQ DM RDQS data-in for column b. NOTE : 2. Three subsequent elements of data-in the programmed order following DI b. ...
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... K4J55323QI WRITE to PRECHARGE T0 T1 /CK CK COMMAND WRITE NOP Bank ADDRESS Col (NOM) DQSS DQSS WDQS (MIN) DQSS DQSS WDQS (MAX) DQSS DQSS WDQS DQ DM NOTE data-in for column Three subsequent elements of data-in the programmed order following DI b. ...
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... K4J55323QI 7.9.4 PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE command is RP issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank ...
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... K4J55323QI 8.0 IBIS : I/V Characteristics for Input and Output Buffers Pulldown Current (mA) Voltage Minimum (V) 0.1 2.8 0.2 5.5 0.3 8.1 0.4 10.8 0.5 13.3 0.6 15.8 0.7 18.2 0.8 20.5 0.9 22.8 1.0 24.9 1.1 26.9 1.2 28.8 1.3 30.6 1.4 32.2 1.5 33.7 1.6 35.2 1.7 36.3 1.8 37.7 1.9 38.7 256M GDDR3 SDRAM Maximum Minimum 3.2 -2.4 9.6 -4.7 12.8 -7.0 15.9 -9.2 19.0 -11.4 22.0 -13.4 25.1 -15.3 28.0 -17.1 31.0 -18.8 33.8 -20.3 36.7 -21.7 36.7 -22.9 39.4 -23.9 42.1 -24.8 44.7 -25.4 47.0 -26.0 49.2 -26.5 51.4 -27.0 53.3 -27 Pullup Current (mA) Maximum -3.1 -6.2 -9.2 -12.1 -14.9 -17.7 -20.3 -22.8 -25.2 -27.5 -29.6 -31.6 -33.3 -34.9 -36.3 -37.5 -38.3 -39.3 -40.0 Rev. 1.3 May 2007 ...
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... K4J55323QI -10 -15 -20 -25 -30 -35 -40 -45 Pull Down Voltage(V) Pull Up Voltage( 256M GDDR3 SDRAM Min Max Min Max ...
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... K4J55323QI 9.0 TRUTH TABLE TRUTH TABLE - Clock Enable (CKE) CKEn-1 CKEn CURRENT STATE Power-Down L L Self Refresh Power-Down L H Self Refresh All Banks Idle H L Bank(s) Active All Banks Idle Note : 1. CKEn is the logic state of CKE at clock edge n; CKEn-1was the state of CKE at the previous clock edge. ...
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... K4J55323QI Read w/ Auto-Precharge Enabled : Starts with registration of an READ command with auto precharge enabled and ends Write w/ Auto-Precharge Enabled : Starts with registration of a WRITE command with auto precharge enabled and ends 5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states ...
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... K4J55323QI 3. Current state definitions : Idle : The bank has been precharged, and t Row Active : A row in the bank has been activated, and t No data bursts/accesses and no register accesses are in progress. Read : A READ burst has been initiated, with auto precharge disabled. Write : A WRITE burst has been initiated, with auto precharge disabled. ...
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... K4J55323QI 10.0 COMMANDS Below Truth table-COMMANDs provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables appear following the operation section : these tables provide current state/next state information. TRUTH TABLE - COMMANDs Name (Function) DESELECT (NOP) NO OPERATION (NOP) ...
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... K4J55323QI READ The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 inputs select the bank, and the address provided on inputs A0-A7, A9 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto pre- charge is not selected, the row will remain open for subsequent accesses ...
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... K4J55323QI DATA TERMINATION DISABLE (BUS SNOOPING FOR READ COMMAND) The DATA TERMINATOR DISABLE COMMAND is detected by the device by snooping the bus for READ commands excluding /CS. The GDDR3 DRAM will disable its Data terminators when a READ command is detected. The terminators are disable CL-1 Clocks after the READ command is detected ...
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... Vih and Vil. DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns, timing is longer than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points. 5. VIH overshoot : VIH(max) = VDDQ + 0.5V for a pulse width VIL undershoot : VIL(min)=0.0V for a pulse width 6. K4J55323QI-BC** 7. K4J55323QI-BJ OL(DC) max for -BJ** is 0.84V Symbol V ...
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... K4J55323QI 11.3 CLOCK INPUT OPERATING CONDITIONS Recommended operating conditions ( Parameter/ Condition Clock Input Mid-Point Voltage ; CK and /CK Clock Input Voltage Level; CK and /CK Clock Input Differential Voltage ; CK and /CK Clock Input Differential Voltage ; CK and /CK Clock Input Crossing Point Voltage ; CK and /CK Note : 1. This provides a minimum of 1.16V to a maximum of 1.36V for -BC part and 1.3V ~ 1.5V for -BJ part and is always 70% of VDDQ 2 ...
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... K4J55323QI 11.4 DC CHARACTERISTICS Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I CC2 in Power-down mode Precharge Standby Current I CC2 in Non Power-down mode Active Standby Current I CC3 power-down mode Active Standby Current in I CC3 in Non Power-down mode Operating Current I CC4 ( Burst Mode) ...
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... K4J55323QI 11.6 AC CHARACTERISTICS (I-I) Parameter DQS out access time from CK CK high-level width CK low-level width CL=12 CK cycle time CL=11 CL=10 WRITE Latency DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS Active termination setup time Active termination hold time DQS input high pulse width ...
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... K4J55323QI AC CHARACTERISTICS (I-II) Parameter DQS out access time from CK CK high-level width CK low-level width CK cycle time WRITE Latency DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS Active termination setup time Active termination hold time DQS input high pulse width ...
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... K4J55323QI AC CHARACTERISTICS II-I Parameter Row active time Row cycle time Refresh row cycle time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge (PRE or Auto-PRE) tWR Last data in to Read command ...
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... K4J55323QI 11.7 PACKAGE DIMENSIONS (FBGA) 0.12 Max 0.45 ± 0.05 0.35 ± 0.05 1.20 Max 256M GDDR3 SDRAM A1 INDEX MARK 11.0 <Top View> 0.8x11=8.8 0 0.40 <Top View: See the balls through the package> Ball existing Depopulated ball ...