K6X4016C3F-TF70

Manufacturer Part NumberK6X4016C3F-TF70
ManufacturerSamsung
K6X4016C3F-TF70 datasheet
 


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DATA RETENTION WAVE FORM

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K6X4016C3F Family
TIMING WAVEFORM OF WRITE CYCLE(3)
Address
CS
UB, LB
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A wri
e occurs during the overlap(t
t
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The t
2. t
is measured from the CS going low to the end of write.
CW
3. t
is measured from the address valid to the beginning of write.
AS
4. t
is measured from the end of write to the address change. t
WR

DATA RETENTION WAVE FORM

CS controlled
V
CC
4.5V
2.2V
V
DR
CS
GND
(UB, LB Controlled)
t
WC
t
CW(2)
t
AW
t
BW
t
AS(3)
t
WP(1)
High-Z
) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
WP
is measured from the beginning of write to the end of write.
WP
applied in case a write ends as CS or WE going high.
WR
Data Retention Mode
t
SDR
CS V
- 0.2V
CC
8
CMOS SRAM
t
WR(4)
t
t
DH
DW
Data Valid
High-Z
t
RDR
Revision 1.0
September 2003