TDA8595TH/N2C,118 NXP Semiconductors, TDA8595TH/N2C,118 Datasheet
TDA8595TH/N2C,118
Specifications of TDA8595TH/N2C,118
TDA8595TH/N2C-T
TDA8595TH/N2C-T
Related parts for TDA8595TH/N2C,118
TDA8595TH/N2C,118 Summary of contents
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TDA8595 2 I C-bus controlled 4 Rev. 02 — 21 November 2007 1. General description The TDA8595 is a complementary quad Bridge Tied Load (BTL) audio power amplifier made in BCDMOS technology. It contains four independent amplifiers in BTL configuration. ...
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... NXP Semiconductors I Selectable information on the DIAG and STB pins: N The STB pin can be programmed/multiplexed with second clip detection N Clip information of each channel can be directed separately to the DIAG pin or the STB pin N Independent enabling of thermal, clip or load fault detection (short across ground) on DIAG pin 3 ...
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... NXP Semiconductors 5. Block diagram 2 (29) STANDBY/ STB FAST MUTE 12 (6) IN1 16 (12) IN3 13 (7) IN2 15 (11) IN4 V P The pin numbers in parenthesis represent TDA8595TH. Fig 1. Block diagram TDA8595_2 Product data sheet ADSEL SDA SCL (28) 26 (26) 23 (22 C-BUS CLIP DETECT/DIAGNOSTIC INTERFACE MUTE ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration TDA8595J and TDA8595SD TDA8595_2 Product data sheet 2 I C-bus controlled 4 ADSEL 1 STB 2 3 PGND2 4 OUT2 DIAG 5 OUT2 OUT1 8 PGND1 9 OUT1 SVR IN1 12 IN2 13 TDA8595J 14 SGND TDA8595SD 15 IN4 IN3 16 ACGND 17 18 OUT3 ...
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... NXP Semiconductors Fig 3. Pin configuration TDA8595TH 6.2 Pin description Table 3. Symbol ADSEL STB PGND2 OUT2 DIAG OUT2 n.c. OUT1 PGND1 OUT1+ SVR IN1 IN2 n.c. SGND TDA8595_2 Product data sheet 36 TAB DIAG 33 32 OUT2 PGND2 31 OUT2 STB 28 ADSEL TDA8595TH n.c. ...
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... NXP Semiconductors Table 3. Symbol n.c. IN4 IN3 ACGND OUT3+ n.c. PGND3 OUT3 n. OUT4+ SCL OUT4 PGND4 SDA n.c. TAB [1] To keep the output pins on the front side, special reverse bending is applied. 7. Functional description The TDA8595 is a complementary quad BTL audio power amplifier made in BCDMOS technology. It contains four independent amplifi ...
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... NXP Semiconductors 7.1 Input stage The input stage is a high-impedance pseudo-differential input stage. The negative inputs of the four channels are combined on the ACGND pin. For the best performance on supply voltage ripple rejection and pop noise, the capacitor connected to the ACGND pin must be four times the value of the input capacitor (or as close to the value as possible) ...
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... NXP Semiconductors 7.6 Speaker protection To prevent damage of the speaker when one side of the speaker is connected to ground, a missing current protection is implemented. When in one channel the current in the high side power is not equal to the current in the low side power, a fault condition is assumed and the channel will be switched off. The speaker protection will be activated under the following conditions: • ...
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... NXP Semiconductors When the amplifier is switched off by pulling the STB pin LOW, the amplifier is first muted (fast mute) and then the capacitor on the SVR pin is discharged. With an SVR capacitor the standby current is reached 1 second after the STB pin is switched to zero (see ...
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... NXP Semiconductors V P DIAG DB2 bit D7 POR IB1 bit D0 start enable t wake STB SVR t t amp_on amplifier output t d(mute_off) Fig 5. Start-up and shut-down timing with DC load active in I TDA8595_2 Product data sheet load t d(soft_mute) 2 Rev. 02 — 21 November 2007 2 I C-bus controlled power amplifi ...
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... NXP Semiconductors V P DIAG DB2 bit D7 POR IB1 bit D0 start enable t wake STB SVR t load t amp_on amplifier output t d(mute_off) Fig 6. Start-up and shut-down timing with low audible pop and DC load activated TDA8595_2 Product data sheet 2 I C-bus controlled 4 t d(soft_mute) Rev. 02 — 21 November 2007 TDA8595 45 W power amplifi ...
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... NXP Semiconductors V P DIAG on STB mute standby SVR t amp_on amplifier output t d(mute_off) Fig 7. Start-up and shut-down timing in legacy mode 7.9 Power-on reset and supply voltage spikes C-bus mode the supply voltage drops below 5 V (see 2 I C-bus latches cannot be guaranteed and the power-on reset will be activated. All latches are reset, the amplifi ...
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... NXP Semiconductors When the SVR capacitor has discharged, the amplifier starts up again if the V above the low V outputs of the amplifier remain low typically 5 V, results in setting bit DB2[D7]. The amplifiers will not start-up but wait for C-bus command to start-up. ...
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... NXP Semiconductors 2 V legacy and I C-bus mode O (V) 14.4 8.8 8.6 7.2 3.5 output voltage (1) Headroom protection activated: a) Fast mute b) Discharge of SVR. (2) Low V mute activated. P (3) Low V mute released. P Fig 9. Low V behavior; legacy and I P TDA8595_2 Product data sheet (2) V SVR ...
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... NXP Semiconductors C-bus mode only O (V) 14.4 8.8 8.6 7.2 5.0 3.5 output voltage 0 POR IB1 bit D0 DIAG (1) Low V mute activated. P Power-On Reset ( ( level at which POR P 2 Fig 10. Low V behavior; I C-bus mode only P 7.11 Overvoltage and load dump protection When the battery voltage V high-impedance ...
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... NXP Semiconductors G (dB) Fig 11. Temperature controlled amplifier gain 7.13 Diagnostics Diagnostic information can be read via the I DIAG pin or on the STB pin. The DIAG pin has both fixed information (power-on reset occurred, low battery and high battery) and, via the I (temperature, load fault and clip) ...
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... NXP Semiconductors Table 4. Diagnostic information Speaker protection (missing current) Offset detection Load detection Overvoltage 7.14 Offset detection The offset detection can be performed with no input signal (for instance when the DSP is in mute after a start-up) or with an input signal output offset is performed, the I BTL output voltage is within a window with threshold of 1 ...
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... NXP Semiconductors Fig 13. DC load detection levels If the amplifier is used as line driver and the external booster has an input impedance of more than 100 DBx[D5:D4] = 10, independent of the gain setting (see Table 5. DC load bits DBx[D5 reading the I amplifier, whether a speaker or an external booster is connected. ...
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... NXP Semiconductors The interpretation of line driver and normal mode DC load bit setting for AC load detection is shown in Table 6. DBx[D4 When bit IB1[D2 the AC load detection is enabled. The AC load detection can only be performed after the amplifier has completed its start-up cycle and will not conflict with the DC load detection ...
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... NXP Semiconductors C-bus specification Table 7. Pin ADSEL Open ground ground Ground SDA SCL Fig 15. Definition of START and STOP conditions Fig 16. Bit transfer TDA8595_2 Product data sheet TDA8595 hardware address select C-bus; legacy mode S START condition SDA SCL data line stable ...
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... NXP Semiconductors 2 I C-BUS WRITE SCL 1 2 MSB MSB 1 SDA S ADDRESS 2 I C-BUS READ SCL 1 2 MSB MSB 1 SDA S ADDRESS : generated by master (microcontroller) : generated by slave S : START P : STOP A : acknowledge NA : not acknowledge R/W : read / write 2 Fig 17. I C-bus read and write modes 8.1 Instruction bytes ...
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... NXP Semiconductors Table 8. Bit Table 9. Bit D7 and TDA8595_2 Product data sheet Instruction byte IB1 …continued Description channel 4 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin channel 2 clip information on DIAG or STB pin 0 = clip information on DIAG pin 1 = clip information on STB pin ...
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... NXP Semiconductors Table 9. Bit D0 Table 10. Bit 8.2 Data bytes 2 I C-bus mode: • the TDA8595 sends four data bytes to the microprocessor: DB1, DB2, DB3 and DB4 • All bits except DB1[D7] and DB3[D7] are latched • All bits except DBx[D4] and DBx[D5] are reset after a read operation. Bit DBx[D2] is set after a read operation, see • ...
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... NXP Semiconductors Table 11. Bit and Table 12. Bit D7 D6 TDA8595_2 Product data sheet Data byte DB1 Description temperature pre-warning warning 1 = junction temperature too high speaker fault channel 2 (missing current missing current 1 = missing current channel 2 DC load or AC load detection if bit IB1[D2 load detection is enabled, bit D5 is don’t care, bit D4 has the ...
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... NXP Semiconductors Table 12. Bit D5 and Table 13. Bit D7 D6 TDA8595_2 Product data sheet Data byte DB2 …continued Description channel 4 DC load or AC load detection if bit IB1[D2 load detection is enabled, bit D5 is don’t care, bit D4 has the following meaning load load detected ...
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... NXP Semiconductors Table 13. Bit D5 and Table 14. Bit and D4 TDA8595_2 Product data sheet Data byte DB3 …continued Description channel 1 DC load or AC load detection if bit IB1[D2 load detection is enabled, bit D5 is don’t care, bit D4 has the following meaning load load detected ...
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... NXP Semiconductors Table 14. Bit Limiting values Table 15. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol P(r) I OSM I ORM T j(max) T stg T amb V (prot TDA8595_2 Product data sheet Data byte DB4 …continued Description channel 3 shorted load 0 = not shorted load 1 = shorted load ...
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... NXP Semiconductors Table 15. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol P tot V esd 10. Thermal characteristics Table 16. Symbol TDA8595J; TDA8595SD R th(j-c) R th(j-a) TDA8595TH R th(j-c) R th(j-a) 11. Characteristics Table 17. Characteristics Refer to test circuit (see Figure 30 specified. Tested guaranteed for T amb ...
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... NXP Semiconductors Table 17. Characteristics …continued Refer to test circuit (see Figure 30 specified. Tested guaranteed for T amb Symbol Parameter R load resistance tolerance L(tol) Mode select and second clip detection: pin STB V voltage on pin STB STB I current on pin STB STB Start-up / shut-down / mute timing ...
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... NXP Semiconductors Table 17. Characteristics …continued Refer to test circuit (see Figure 30 specified. Tested guaranteed for T amb Symbol Parameter t amplifier on time amp_on t amplifier switch-off time off t mute to on delay time d(mute-on) t soft mute delay time d(soft_mute) t fast mute delay time ...
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... NXP Semiconductors Table 17. Characteristics …continued Refer to test circuit (see Figure 30 specified. Tested guaranteed for T amb Symbol Parameter f SCL clock frequency SCL R resistance on pin ADSEL ADSEL Diagnostic V LOW-level output voltage OL(DIAG) on pin DIAG V output voltage at offset O(offset_det) detection THD total harmonic distortion ...
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... NXP Semiconductors Table 17. Characteristics …continued Refer to test circuit (see Figure 30 specified. Tested guaranteed for T amb Symbol Parameter Amplifier P output power o THD total harmonic distortion channel separation cs SVRR supply voltage ripple rejection CMRR common mode rejection ratio V maximum common mode ...
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... NXP Semiconductors Table 17. Characteristics …continued Refer to test circuit (see Figure 30 specified. Tested guaranteed for T amb Symbol Parameter Z input impedance i mute attenuation mute V RMS mute output voltage o(mute)(RMS) B power bandwidth p [1] Operation above mode with reactive load can trigger the amplifier protection. The amplifier switches off and will restart after 16 ms resulting in an ‘ ...
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... NXP Semiconductors THD (%) ( kHz. ( 100 Hz. ( kHz. Fig 19. Total harmonic distortion as a function of output power (W) (1) THD = 10 %. (2) THD = 0.5 %. Fig 20. Output power as a function of frequency; 4 TDA8595_2 Product data sheet 14 14 Rev. 02 — 21 November 2007 TDA8595 2 I C-bus controlled power amplifier ...
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... NXP Semiconductors P (W) (1) THD = 10 %. (2) THD = 0.5 %. Fig 21. Output power as a function of frequency (W) (1) P (2) THD = 10 %. (3) THD = 0.5 %. Fig 22. Output power as a function of supply voltage; 4 TDA8595_2 Product data sheet 14 kHz. . o(max) Rev. 02 — 21 November 2007 TDA8595 2 I C-bus controlled power amplifier ...
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... NXP Semiconductors P (W) (1) P (2) THD = 10 %. (3) THD = 0.5 %. Fig 23. Output power as a function of supply voltage; 2 THD (%) (1) P (2) P Fig 24. Total harmonic distortion as a function of frequency; normal mode TDA8595_2 Product data sheet 100 kHz. . o(max ( Rev. 02 — 21 November 2007 TDA8595 2 I C-bus controlled power amplifi ...
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... NXP Semiconductors THD (%) (1) V (2) V Fig 25. Total harmonic distortion as a function of frequency; line driver mode SVRR (dB) Fig 26. Supply voltage ripple rejection as a function of frequency TDA8595_2 Product data sheet ( 600 . 14 ripple Rev. 02 — 21 November 2007 TDA8595 2 I C-bus controlled power amplifier ...
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... NXP Semiconductors (dB) Fig 27. Channel separation as a function of frequency (W) Fig 28. Power dissipation as a function of output power; 4 TDA8595_2 Product data sheet 100 14 14 kHz Rev. 02 — 21 November 2007 TDA8595 2 I C-bus controlled power amplifier 001aad148 (kHz) 001aad711 (W) o load © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors (W) Fig 29. Power dissipation as a function of output power; 2 TDA8595_2 Product data sheet 100 14 kHz Rev. 02 — 21 November 2007 TDA8595 2 I C-bus controlled power amplifier 001aad712 (W) o load © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 13. Application information 8 STB 2 (29) 470 IN1 12 (6) (1) 1.8 nF 470 IN3 16 (12) (1) 1.8 nF 470 (7) IN2 (1) 1.8 nF 470 IN4 15 (11) (1) V 1.8 nF The pin numbers in parenthesis represent TDA8595TH. (1) For EMC reasons a capacitor of 1.8 nF from the input pin to the SGND is advised (optional). ...
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... NXP Semiconductors Fig 31. Beep input circuit (gain = 0 dB) to apply a microcontroller beep signal to all four Fig 32. Complex loads for measuring THD in line driver mode Fig 33. Circuit for combined STB and clip detection functions on pin STB TDA8595_2 Product data sheet 1.7 k MICRO- CONTROLLER The pin number in parenthesis represents TDA8595TH. amplifi ...
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... NXP Semiconductors 13.1 PCB layout Fig 34. PCB layout of test and application circuit for TDA8595J or TDA8595SD; copper Fig 35. PCB layout of test and application circuit for TDA8595J or TDA8595SD; copper TDA8595_2 Product data sheet top layer top layer bottom (top view) Rev. 02 — 21 November 2007 ...
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... NXP Semiconductors clip 2 mode on diag Mute off Fig 36. PCB layout of test and application circuit for TDA8595J or TDA8595SD Fig 37. PCB layout of test and application circuit for TDA8595J or TDA8595SD; 14. Test information 14.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualifi ...
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... NXP Semiconductors 15. Package outline DBS27P: plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length 6.8 mm DIMENSIONS (mm are the original dimensions) (1) UNIT 4.65 0.60 0.5 29 4.35 0.45 0.3 28.8 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height pin 1 index DIMENSIONS (mm are the original dimensions) A (1) UNIT max 3.5 0.08 0.38 mm 3.5 0.35 3.2 0.04 0.25 Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors RDBS27P: plastic rectangular-DIL-bent-SIL (reverse bent) power package; 27 leads (row spacing 2.54 mm DIMENSIONS (mm are the original dimensions) UNIT 4.65 0.60 0.5 29.2 mm 13.5 4.35 0.45 0.3 28.8 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included OUTLINE VERSION ...
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... NXP Semiconductors 16. Mounting Fig 41. SOT878-1 reflow soldering footprint 17. Abbreviations Table 18. Acronym BCDMOS BTL CMOS DMOS DSP EMC ESR NMOS PMOS POR SOAR SOI TDA8595_2 Product data sheet hole diameter min. 0.92 Dimensions in mm. Reflow soldering is the recommended soldering method. Dimension ‘1’ relates to dimension ‘e ’ ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Changed the term ‘plop’ into ‘pop’. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2.2 I C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.3 Distortion (clip-) detection ...