CY7C1041B-17VI Cypress Semiconductor Corporation., CY7C1041B-17VI Datasheet

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CY7C1041B-17VI

Manufacturer Part Number
CY7C1041B-17VI
Description
256K x 16 static RAM, 17ns
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Features
Functional Description
The CY7C1041B is a high-performance CMOS static RAM or-
ganized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
Selection Guide
Cypress Semiconductor Corporation
Maximum Access Time (ns)
Maximum Operating Current (mA) Com’l
Maximum CMOS Standby Current
(mA)
• High speed
• Low active power
• Low CMOS standby power (L version)
• 2.0V Data Retention (400 W at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
A
A
A
A
A
A
A
A
A
Logic Block Diagram
0
1
2
3
4
5
6
7
8
— t
— 1540 mW (max.)
— 2.75 mW (max.)
AA
= 12 ns
INPUT BUFFER
1024 x 4096
DECODER
COLUMN
256K x 16
ARRAY
Ind’l
Com’l
Com’l
Ind’l
0
through I/O
L
3901 North First Street
7C1041B-12
200
220
12
3
-
-
7
), is
I/O
I/O
0
8
– I/O
– I/O
BHE
WE
CE
OE
BLE
1041B–1
7C1041B-15
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041B is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
7
15
190
210
0.5
15
3
6
17
San Jose
). If Byte High Enable (BHE) is LOW, then data
7C1041B-17
256K x 16 Static RAM
0
8
to I/O
180
200
0.5
through I/O
17
3
6
Pin Configuration
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
V
WE
CE
CC
A
A
A
A
A
A
A
A
A
A
SS
7
5
6
7
8
9
0
1
2
3
4
0
1
2
3
4
5
6
7
. If Byte High Enable (BHE) is LOW,
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CA 95134
through I/O
Top View
TSOP II
7C1041B-20
15
SOJ
0
) is written into the location
through A
170
190
0.5
20
3
6
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
CY7C1041B
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
NC
A
A
A
A
A
15
17
16
15
SS
CC
14
13
12
11
10
8
) are placed in a
15
14
13
12
11
10
9
8
17
to I/O
1041B–2
March 23, 2001
).
7C1041B-25
408-943-2600
15
160
180
0.5
25
. See the
3
6
0

Related parts for CY7C1041B-17VI

CY7C1041B-17VI Summary of contents

Page 1

... TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features Functional Description The CY7C1041B is a high-performance CMOS static RAM or- ganized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable ...

Page 2

... Ind’ > > < MAX , Com’l CC – 0.3V, CC Com’l L > V – 0.3V < 0.3V Ind’ CY7C1041B [1] –0. 0.5V CC Ambient [2] Temperature + – +85 C 7C1041B-15 7C1041B-17 Max. Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0 ...

Page 3

... V – 0.3V Ind’ < 0.3V Test Conditions MHz 5. 481 5V 3.0V R2 GND 5 pF 255 INCLUDING JIG AND SCOPE (b) 1041B–3 1.73V 3 CY7C1041B 7C1041B-20 7C1041B-25 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 2 0.5 –0.5 0.8 –0.5 0.8 –1 +1 –1 +1 –1 +1 – ...

Page 4

... HZCE LZCE HZOE LZOE HZWE 4 CY7C1041B 7C1041B-15 7C1041B-17 Min. Max. Min. Max ...

Page 5

... Over the Operating Range (L version only) Conditions Com’ 3.0V > V – 0.3V > V – 0. CY7C1041B 7C1041B-25 Max. Min. Max ...

Page 6

... Address valid prior to or coincident with CE transition LOW. DATA RETENTION MODE 3.0V V > CDR OHA [13, 14 DOE t LZOE t DBE LZBE DATA VALID 50 CY7C1041B 3. 1041B–5 DATA VALID 1041B-6 t HZOE t HZCE t HZBE HIGH IMPEDANCE t PD ICC 50% ISB 1041B-7 ...

Page 7

... Data I/O is high impedance BHE and/or BLE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. [15, 16 SCE PWE PWE t SCE . IH 7 CY7C1041B 1041B 1041B-9 ...

Page 8

... Read All bits High Z Read Lower bits only Data Out Read Upper bits only Data In Write All bits High Z Write Lower bits only Data In Write Upper bits only High Z Selected, Outputs Disabled 8 CY7C1041B LZWE 1041B-10 Mode Power Standby (I Active (I ...

Page 9

... CY7C1041BL-17VC CY7C1041B-17ZC CY7C1041BL-17ZC 20 CY7C1041B-20VC CY7C1041BL-20VC CY7C1041B-20ZC CY7C1041BL-20ZC 25 CY7C1041B-25VC CY7C1041BL-25VC CY7C1041B-25ZC CY7C1041BL-25ZC 15 CY7C1041B-15ZI CY7C1041B-15VI 17 CY7C1041B-17ZI CY7C1041B-17VI 20 CY7C1041B-20ZI CY7C1041B-20VI 25 CY7C1041B-25ZI CY7C1041B-25VI Document #: 38-00938-*B Package Name Package Type V34 44-Lead (400-Mil) Molded SOJ Z44 44-Lead TSOP Type II V34 44-Lead (400-Mil) Molded SOJ V34 44-Lead (400-Mil) Molded SOJ ...

Page 10

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 44-Lead (400-Mil) Molded SOJ V34 44-Pin TSOP II Z44 CY7C1041B 51-85082-B 51-85087-A ...

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