M5M44260CTP-7S Mitsumi Electronics, Corp., M5M44260CTP-7S Datasheet

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M5M44260CTP-7S

Manufacturer Part Number
M5M44260CTP-7S
Description
Manufacturer
Mitsumi Electronics, Corp.
Datasheet

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M5M44260CJ,TP-5,-5S : Under development
DESCRIPTION
Microcomputer memory, Refresh memory for CRT
FEATURES
PIN DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs,
fabricated with the high performance CMOS process, and is ideal
for memory systems where high speed, low power dissipation, and
low costs are essential.
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is small enough for
battery back-up application.
512 cycles every 8.2ms.
XX=J,TP
APPLICATION
The use of double-layer metalization process technology and a
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
Operating power dissipation
Self refresh capability *
Extended refresh capability
Fast-page mode (512-column random access), Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, LCAS / UCAS and OE to control output buffer
impedance
512 refresh cycles every 8.2ms (A
512 refresh cycles every 128ms (A
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S
This device has 2CAS and 1W terminals with a refresh cycle of
M5M44260CXX-5,-5S
M5M44260CXX-6,-6S
M5M44260CXX-7,-7S
DQ
RAS
LCAS
UCAS
W
OE
V
A
V
Pin name
CC
0
SS
: option) only
Type name
CMOS Input level
CMOS Input level
M5M44260Cxx-5,-5S
M5M44260Cxx-6,-6S
M5M44260Cxx-7,-7S
Self refresh current
Extended refresh current
~A
1
~DQ
8
16
Lower byte control
Address inputs
Data inputs / outputs
Row address strobe input
column address strobe input
Upper byte control
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
column address strobe input
(max.ns)
access
RAS
time
70
50
60
Function
(max.ns)
access
CAS
time
13
15
20
0
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Address
(max.ns)
0
~A
access
~A
time
25
30
35
8
8
)
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
) *
(max.ns)
access
time
13
15
20
OE
(min.ns)
550µW (Max) *
Cycle
110
130
688mW (Max)
605mW (Max)
523mW (Max)
time
5.5mW (Max)
150µA (Max)
150µA (Max)
90
M5M44260CJ,TP-5,-6,-7,
(typ.mW)
dissipa-
Power
625
550
475
tion
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
PIN CONFIGURATION (TOP VIEW)
Outline 44P3W-R (400mil TSOP Nomal Bend)
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
RAS
DQ4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RAS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Outline 40P0K (400mil SOJ)
NC
NC
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
A
A
A
A
A
A
A
A
W
W
1
2
3
4
5
6
7
8
0
1
2
3
1
2
3
5
6
7
8
0
1
2
3
10
11
12
13
14
15
16
17
18
19
20
10
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
-5S,-6S,-7S
MITSUBISHI LSIs
25
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
44
43
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
23
MITSUBISHI LSIs
NC: NO CONNECTION
V
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
V
V
V
A
A
A
A
A
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
SS
SS
8
7
6
5
4
SS
SS
8
7
6
5
4
SS
SS
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
(0V)
(0V)
(0V)
(0V)
(0V)
(0V)

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M5M44260CTP-7S Summary of contents

Page 1

DESCRIPTION This is a family of 262144-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization ...

Page 2

FUNCTION In addition to normal read,write and read-modify-write operations the M5M44260CJ, TP provides a number of other functions, e.g., Table 1 Input conditions for each mode Operation Lower byte read Upper byte read Word read Lower byte write Upper byte ...

Page 3

ABSOLUTE MAXIMUM RATINGS Symbol Parameter Supply voltage V CC Input voltage Output voltage O I Output current O Power dissipation Operating temperature opr Storage temperature T stg RECOMMENDED OPERATING CONDITIONS Symbol Parameter Supply voltage ...

Page 4

V CAPACITANCE CC Parameter Symbol Input capacitance, address inputs C I (A) Input capacitance, clock inputs C I (CLK) C Input/Output capacitance, data ports SWITCHING CHARACTERISTICS Symbol t Access time from CAS CAC t Access ...

Page 5

TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Fast-Page Mode Cycles) (Ta=0~70˚C, V =5V±10%, V =0V, unless otherwise noted, see notes 6,13,14 Symbol t Refresh cycle time REF t Refresh cycle time * REF t RAS high pulse ...

Page 6

Write Cycle (Early Write and Delayed Write) Symbol Write cycle time t WC RAS low pulse width t RAS t CAS low pulse width CAS t CAS hold time after RAS low CSH RAS hold time after CAS low t ...

Page 7

Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) Symbol Fast page mode read/write cycle time t PC Fast page mode read write/read modify write cycle time t PRWC RAS low pulse width for read or write cycle t ...

Page 8

Timing Diagrams (Note 29) Read Cycle V IH RAS CRP V IH LCAS/UCAS ASR ~ (INPUTS) ...

Page 9

Byte Read Cycle V IH RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS ...

Page 10

Write Cycle (Early write RAS CRP V IH LCAS/UCAS ASR t RAH V IH ROW ADDRESS ~ ...

Page 11

Byte Write Cycle (Early write RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS ...

Page 12

Write Cycle (Delayed write RAS CRP V IH LCAS/UCAS ASR ADDRESS ~ (INPUTS) V ...

Page 13

Byte Write Cycle (Delayed write RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS ...

Page 14

Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH LCAS/UCAS ASR ~ (INPUTS ...

Page 15

Byte Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ...

Page 16

RAS-only Refresh Cycle V IH RAS CRP V IH LCAS/UCAS ASR V IH ROW ADDRESS ~ (INPUTS) V ...

Page 17

CAS before RAS Refresh Cycle, Extended Refresh Cycle * RAS CSR t RPC V IH LCAS/UCAS CPN RCH ...

Page 18

Hidden Refresh Cycle (Read RAS CRP V IH LCAS/UCAS ASR ADDRESS ~ (INPUTS) V ...

Page 19

Fast Page Mode Read Cycle V IH RAS CRP V IH LCAS/UCAS ASR t RAH V IH ROW ADDRESS ~DQ ...

Page 20

Fast Page Mode Byte Read Cycle V IH RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR t RAH V IH ROW ADDRESS V ...

Page 21

Fast Page Mode Write Cycle (Early Write RAS CRP V IH LCAS/UCAS ASR ADDRESS ~DQ 1 ...

Page 22

Fast Page Mode Byte Write Cycle (Early Write RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS V IL ...

Page 23

Fast-Page Mode Write Cycle (Delayed Write RAS CRP V IH LCAS/UCAS ASR ADDRESS ~ ...

Page 24

Fast-Page Mode Byte Write Cycle (Delayed Write RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR RAH V IH ROW ADDRESS ...

Page 25

Fast Page Mode Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH LCAS/UCAS ASR ADDRESS ~ ...

Page 26

Fast Page Mode Byte Read-Write, Read-Modify-Write Cycle V IH RAS CRP V IH UCAS (or LCAS LCAS (or UCAS ASR ADDRESS ...

Page 27

Self Refresh Cycle * (Note28 RAS RPC V IH LCAS/UCAS CPN RCH CDD V IH ...

Page 28

Note 28 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width ( RAS signal during self refresh RASS period. 1. Distributed refresh during Read/Write operation (A) Timing Diagram Read / ...

Page 29

Burst refresh during Read/Write operation (A) Timing diagram Read / Write RAS first refresh cycles Table 3 Read / Write Read / Write Cycle Self Refresh CBR burst t 8.2ms NSB refresh RAS only burst refresh (B) Definition of ...

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