MC68HC11K4BCFN4 Freescale Semiconductor, Inc, MC68HC11K4BCFN4 Datasheet

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MC68HC11K4BCFN4

Manufacturer Part Number
MC68HC11K4BCFN4
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Technical Summary
8-Bit Microcontroller
1 Features
© MOTOROLA INC., 1997
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
This document contains information on a new product. Specifications and information herein are subject to change without notice.
The M68HC11 K-series microcontroller units (MCUs) are high-performance derivatives of the
MC68HC11F1 and have several additional features. The MC68HC11K0, MC68HC11K1,
MC68HC11K3, MC68HC11K4 and MC68HC711K4 comprise the series. These MCUs, with a nonmul-
tiplexed expanded bus, are characterized by high speed and low power consumption. Their fully static
design allows operation at frequencies from 4 MHz to dc.
This document contains information concerning standard, custom-ROM, and extended-voltage devic-
es. Standard devices include those with disabled ROM (MC68HC11K1), disabled EEPROM
(MC68HC11K3), disabled ROM and EEPROM (MC68HC11K0), or EPROM replacing ROM
(MC68HC711K4). Custom-ROM devices have a ROM array that is programmed at the factory to cus-
tomer specifications. Extended-voltage devices are guaranteed to operate over a much greater voltage
range (3.0 Vdc to 5.5 Vdc) at lower frequencies than the standard devices. Refer to the device ordering
information tables for details concerning these differences.
• M68HC11 CPU
• Power Saving STOP and WAIT Modes
• 768 Bytes RAM (All Saved During Standby)
• 24 Kbytes ROM or EPROM
• 640 Bytes Electrically Erasable Programmable Read Only Memory (EEPROM)
• Optional Security Feature Protects Memory Contents
• On-Chip Memory Mapping Logic Allows Expansion to Over 1 Mbyte of Address Space
• PROG Mode Allows Use of Standard EPROM Programmer (27C256 Footprint)
• Nonmultiplexed Address and Data Buses
• Four Programmable Chip Selects with Clock Stretching (Expanded Modes)
• Enhanced 16-Bit Timer with Four-Stage Programmable Prescaler
• 8-Bit Pulse Accumulator
• Four 8-Bit or Two 16-Bit Pulse Width Modulation (PWM) Timer Channels
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog
• Clock Monitor
• Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• Enhanced Synchronous Serial Peripheral Interface (SPI)
• Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter
• Seven Bidirectional Input/Output (I/O) Ports (54 Pins)
• One Fixed Input-Only Port (8 Pins)
• Available in 84-Pin Plastic Leaded Chip Carrier (PLCC), 84-Pin Windowed Ceramic Leaded Chip
Carrier (CLCC), and 80-Pin Quad Flat Pack (QFP)
— Three Input Capture (IC) Channels
— Four Output Compare (OC) Channels
— One Additional Channel, Selectable as Fourth IC or Fifth OC
M68HC11 K Series
Order this document
by MC68HC11KTS/D

Related parts for MC68HC11K4BCFN4

MC68HC11K4BCFN4 Summary of contents

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary 8-Bit Microcontroller The M68HC11 K-series microcontroller units (MCUs) are high-performance derivatives of the MC68HC11F1 and have several additional features. The MC68HC11K0, MC68HC11K1, MC68HC11K3, MC68HC11K4 and MC68HC711K4 comprise the series. These MCUs, with a nonmul- ...

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... No ROM, No EEPROM $DF OTPROM $DF OTPROM $DF OTPROM $DF BUFFALO ROM $DD No ROM $DD No ROM $DC No ROM, No EEPROM $DC No ROM, No EEPROM Frequency MC Order Number 4 MHz MC68HC11K4BCFN4 2 MHz MC68HC11K1CFN2 3 MHz MC68HC11K1CFN3 4 MHz MC68HC11K1CFN4 2 MHz MC68HC11K1VFN2 3 MHz MC68HC11K1VFN3 4 MHz MC68HC11K1VFN4 2 MHz MC68HC11K1MFN2 3 MHz MC68HC11K1MFN3 4 MHz MC68HC11K1MFN4 2 MHz ...

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Table 1 Standard Device Ordering Information (Continued) Package Temperature 84-Pin CLCC – (Windowed) – 105 C – 125 C Table 2 Extended Voltage (3.0 Vdc to 5.5 Vdc) Device Ordering Information Package ...

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Table 3 Custom ROM Device Ordering Information Package Temperature 84-Pin PLCC – – 105 C – 125 C – – 105 C – 125 ...

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PH0/PW1 12 PH1/PW2 13 PH2/PW3 14 PH3/PW4 15 PH4/CSIO 16 PH5/CSGP1 17 PH6/CSGP2 18 PH7/CSPROG 19 1 TEST16 20 2 XIRQ/V PPE 21 1 TEST15 TEST14 25 PG7/R/W 26 PG6 27 PG5/XA18 ...

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PD3/MOSI 1 PD4/SCK 2 PD5/SS 3 PA7/PAI/OC1 4 PA6/OC2/OC1 5 PA5/OC3/OC1 6 PA4/OC4/OC1 7 PA3/OC5/IC4/OC1 8 PA2/IC1 9 PA1/IC2 10 PA0/IC3 PB7/ADDR15 14 PB6/ADDR14 15 PB5/ADDR13 16 PB4/ADDR12 17 PB3/ADDR11 18 PB2/ADDR10 19 ...

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XTAL EXTAL E * XOUT MODA/ LIR MODB/ V STBY PULSE PA7 PAI/OC1 ACCUMULATOR PA6 OC2/OC1 PA5 OC3/OC1 PA4 OC4/OC1 PA3 OC5/IC4/OC1 PA2 IC1 PA1 IC2 PA0 IC3 PB7 ADDR15 PB6 ADDR14 PB5 ADDR13 PB4 ADDR12 PB3 ADDR11 PB2 ADDR10 ...

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Section 1 Features 2 Operating Modes 2.1 Single-Chip Operating Mode ..................................................................................................... 11 2.2 Expanded Operating Mode ....................................................................................................... 11 2.3 Bootstrap Mode ......................................................................................................................... 11 2.4 Special Test Mode .....................................................................................................................11 2.5 Mode Selection .......................................................................................................................... 11 3 On-Chip Memory 3.1 Memory Map and ...

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CFORC Timer Compare Force CONFIG System Configuration Register COPRST Arm/Reset COP Timer Circuitry CSCSTR Chip Select Clock Stretch CSCTL Chip Select Control DDRA Data Direction Register for Port A DDRB Data Direction Register for Port B DDRF Data Direction Register ...

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PWCNT[4:1] Pulse-Width Modulation Timer Counter PWDTY[4:1] Pulse-Width Modulation Timer Duty Cycle PWEN Pulse-Width Modulation Timer Enable PWPER[4:1] Pulse-Width Modulation Timer Period PWPOL Pulse-Width Modulation Timer Polarity PWSCAL Pulse-Width Modulation Timer Prescaler ...

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Operating Modes The M68HC11 K-series MCUs have four modes of operation that directly affect the address space. These modes are described as follows. 2.1 Single-Chip Operating Mode In single-chip operating mode, the M68HC11 K-series MCUs are stand-alone microcontrollers with ...

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RBOOT — Read Bootstrap ROM/EPROM Valid only when SMOD is set (bootstrap or special test mode). Can only be written in special modes Bootstrap ROM disabled and not in map 1 = Bootstrap ROM enabled and in map ...

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LSBF —LSB First Enable Refer to 8 Serial Peripheral Interface. SPR2 —SPI Clock Rate Select Refer to 8 Serial Peripheral Interface. XDV[1:0] —XOUT Clock Divide Select Controls the frequency of the clock driven out of the XOUT pin XDV XOUT ...

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On-Chip Memory In general, K-series MCUs have 768 bytes RAM, 640 bytes EEPROM, and 24 Kbytes ROM/EPROM. Some devices in the series have portions of their memory resources disabled. Some have ROM and some have EPROM replacing ROM. The ...

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INIT = $00 REG @ $0000 RAM @ $0080 $0000 REGISTER BLOCK $007F $0080 RAM B $02FF $0300 RAM A $037F Figure 5 RAM and Register Mapping Table 4 M68HC11 K Series Register and Control Bit Assignments (Can be remapped ...

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Table 4 M68HC11 K Series Register and Control Bit Assignments (Continued) (Can be remapped to any 4-Kbyte boundary) Bit 7 6 $0015 Bit 7 6 $0016 Bit 15 14 $0017 Bit 7 6 $0018 Bit 15 14 $0019 Bit 7 ...

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Table 4 M68HC11 K Series Register and Control Bit Assignments (Continued) (Can be remapped to any 4-Kbyte boundary) Bit 7 6 $0058 0 X1A18 X1A17 $0059 0 X2A18 X2A17 $005A IOSA IOSB GP1SA $005B IOEN IOPL IOCSA $005C G1A18 G1A17 ...

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RAM are located at $0300 to $037F. Remapping is ac- complished by writing appropriate values to the INIT register. Refer to the register and RAM mapping examples following the memory map diagram. ...

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Clear the EPROG register to reconfigure the EPROM address and data buses for normal op- eration. In EPROM emulation mode (PROG mode), the EPROM/OTPROM is programmed as a stand-alone EPROM by adapting the MCU footprint to the 27C256-type EPROM ...

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EXCOL —Select Extra Columns 0 = User array selected 1 = User array is disabled and extra columns are accessed at bits [7:0]. Addresses use bits [11:5] and bits [4:0] are don't care. EXCOL can only be read in special ...

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ADDR0 PF0/ADDR0 ADDR1 PF1/ADDR1 ADDR2 PF2/ADDR2 ADDR3 PF3/ADDR3 ADDR4 PF4/ADDR4 ADDR5 PF5/ADDR5 ADDR6 PF6/ADDR6 ADDR7 PF7/ADDR7 ADDR8 PB0/ADDR8 ADDR9 PB1/ADDR9 ADDR10 PB2/ADDR10 ADDR11 PB3/ADDR11 ADDR12 PB4/ADDR12 ADDR13 PB5/ADDR13 ADDR14 PB6/ADDR14 GND PA0/IC3 NOTE 4 GND PA1/IC2 GND PA2/IC1 GND PA3/IC4/OC5/OC1 ...

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EEPROM The 640-byte EEPROM is initially located at $0D80 after reset, assuming EEPROM is enabled in the memory map by the EEON bit in the CONFIG register. EEPROM can be placed at any 4-Kbyte bound- ary ($xD80) by writing ...

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ODD —Program Odd Rows in Half of EEPROM (TEST) EVEN —Program Even Rows in Half of EEPROM (TEST) LVPI —Low Voltage Programming Inhibit LVPI can be read at any time and writes to LVPI have no meaning nor effect. LVPI ...

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LVPEN —Low Voltage Programming Protect Enable If LVPEN = 1, programming of the EEPROM is enabled unless the LVPI circuit detects that V fallen below a safe operating voltage, thus setting the low voltage programming inhibit bit in PPROG register ...

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CONFIG —System Configuration Register Bit 7 6 ROMAD 1 RESET: — 1 ROMAD —ROM/EPROM Mapping Control In single-chip mode ROMAD is forced to one out of reset ROM/EPROM located at $2000–$7FFF 1 = ROM/EPROM located at $A000–$FFFF Bit ...

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Output $FF on SCI transmitter. • Erase EEPROM array. • Verify that EEPROM has been erased has not, repeat erase procedure. • Write $FF to every location in RAM. • Check EPROM for data. If data is ...

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Memory Expansion and Chip Selects Two additional on-chip blocks are provided with the M68HC11 K-series MCUs. The first block imple- ments additional address lines that become active only when required by the CPU. The second block provides chip-select signals ...

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Table 5 CPU Address and Address Expansion Signals Number of Banks 8 Kbytes 2 ADDR[12:0] XA13 4 ADDR[12:0] XA[14:13] 8 ADDR[12:0] XA[15:13] 16 ADDR[12:0] XA[16:13] 32 ADDR[12:0] XA[17:13] 64 ADDR[12:0] XA[18:13] PGAR — Port G Assignment Bit 7 6 — ...

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W1SZ[1:0] —Window 1 Size These bits select the size of memory expansion window 1. WxSZ[1: MMWBR — Memory Mapping Window Base Bit 7 6 $0057 W2A15 W2A14 W2A13 RESET W2A[15:13] ...

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Bit 7 — Not implemented Always reads zero MM1CR — Memory Mapping Window 1 Control Register When a 64 Kbyte CPU address falls within window 1, the value in MM1CR is driven out from the corre- sponding expansion address lines ...

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CSIO Enable Valid Polarity Size Start Address Stretch CSPROG Enable Valid Polarity Size Start Address Stretch Priority CSGP1, Enable CSGP2 Valid Polarity Size Start Address Stretch Other 4.3.1 Program Chip Select (CSPROG) The program chip select (CSPROG) is active in ...

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General-Purpose Chip Selects (CSGP1, CSGP2) The general-purpose chip selects are the most flexible and programmable and have the most control bits. Polarity of active state, E valid or address valid, size, and starting address are all programmable. Clock stretching ...

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IOCSA —I/O Chip Select Address Valid 0 = Valid during E-clock high time 1 = Valid during address valid time IOSZ —I/O Chip Select Size Select 0 = $1000–$1FFF (4 Kbyte $0000–$1FFF (8 Kbyte) GCSPR —General-Purpose Chip Select ...

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GPCS1C —General-Purpose Chip Select 1 Control Bit 7 6 G1DG2 G1DPC RESET G1DG2 —General-Purpose Chip Select 1 Drives General-Purpose Chip Select CSGP1 does not affect CSGP2 1 = CSGP1 and CSGP2 are connected to an ...

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Bit 7 — Not implemented Always reads zero G2DPC — General-Purpose Chip Select 2 Drives Program Chip Select 0 = CSGP2 does not affect CSPROG 1 = CSGP2 and CSPROG are connected gate and driven out CSPROG ...

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BANK 0 CHIP SELECT 1 XA[15:13]= $6000 0:0:0 $01FFF $A000 INTERNAL EPROM $FFFF Figure 7 Memory Expansion Example 1 This example is a system consisting of the MCU, a single 27C512-type memory device as in the ...

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EE/REG/RAM $1000 BANK 0 $4000 XA[15:13]= CHIP SELECT 1 0:0:0 $6000 $01FFF $8000 CHIP SELECT 2 $00000 $A000 $C000 INTERNAL BANK 0 EPROM XA[17:14]= $FFFF 0:0:0:0 $03FFF PGAR = $1F XA[17:13] MMWBR = $84 WINDOW 1 @ $4000, ...

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Resets and Interrupts All M68HC11 MCUs have three reset vectors and 18 interrupt vectors. The reset vectors are as follows: • RESET, or Power-On Reset • Clock Monitor Fail • COP Failure The 18 interrupt vectors service 22 interrupt ...

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Vector Address FFC0, C1 —FFD4, D5 Reserved FFD6, D7 SCI Serial System SCI Receive Data Register Full SCI Receiver Overrun SCI Transmit Data Register Empty SCI Transmit Complete SCI Idle Line Detect FFD8, D9 SPI Serial Transfer Complete FFDA, DB ...

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CME —Clock Monitor Enable 0 = Clock monitor disabled; slow clocks can be used 1 = Slow or stopped clocks cause clock failure reset FCME —Force Clock Monitor Enable 0 = Clock monitor follows the state of the CME bit ...

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PSEL[4:0] —Priority Select Bit 4 through Bit 0 Can be written only while the I-bit in the CCR is set (interrupts disabled). These bits select one interrupt source to be elevated above all other I-bit related sources. PSELx 4 3 ...

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Parallel Input/Output M68HC11 K-series MCUs have input/output lines, depending on the operating mode. To en- hance the I/O functions, the data bus of this microcontroller is nonmultiplexed. The following table is a summary of the configuration ...

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PORTB —Port B Data Bit 7 6 PB7 PB6 S. Chip or Boot: PB7 PB6 RESET Expan. or Test: ADDR15 ADDR14 ADDR13 Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are high-impedance in- ...

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OPT2 —System Configuration Options 2 Bit 7 6 LIRDV CWOM RESET LIRDV—LIR Driven Refer to 2 Operating Modes. CWOM —Port C Wired-OR Mode 0 = Port C operates normally Port C outputs are open-drain. Bit 5 ...

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SPCR —Serial Peripheral Control Bit SPIE SPE DWOM RESET SPIE —SPI Interrupt Enable Refer to 8 Serial Peripheral Interface. SPE —SPI System Enable Refer to 8 Serial Peripheral Interface. DWOM —Port ...

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PT —Parity Type Refer to 7 Serial Communications Interface. PORTE —Port E Data Bit 7 6 PE7 PE6 RESET Alt. Pin Func.: AN7 AN6 DDRF —Data Direction Register for Port F Bit 7 6 DDF7 DDF6 RESET: 0 ...

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In expanded and special test modes, chip-select circuitry forces the I/O state output for each port H pin associated with an enabled chip select. In any mode, PWM circuitry forces the I/O state output ...

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PPAR —Port Pull-Up Assignment Bit 7 6 — — RESET Bits [7:4] —Not implemented Always read zero xPPUE —Port x Pin Pull-Up Enable Valid only when PAREN = 1. Refer to PAREN bit in the CONFIG register description. ...

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Serial Communications Interface The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is one of two independent serial I/O subsystems in M68HC11 K-series MCUs. Rearranging registers and con- trol bits used in previous M68HC11 family devices has ...

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TRANSMITTER BAUD RATE SCDR Tx BUFFER CLOCK 10 (11) - BIT Tx SHIFT REGISTER H ( SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 10 SCI Transmitter Block ...

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RECEIVER BAUD RATE CLOCK DDD0 PIN BUFFER PD0/ AND CONTROL RxD DISABLE DRIVER SCSR2 SCI STATUS 2 M WAKE-UP LOGIC SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 11 SCI Receiver Block Diagram M68HC11 K Series MC68HC11KTS/D ...

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SCBDH/L —SCI Baud Rate Control High/Low Bit $0070 BTST BSPL — RESET $0071 SBR7 SBR6 SBR5 RESET BTST —Baud Register Test (TEST) Factory test only BSPL —Baud Rate Counter Split (TEST) ...

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LOOPS —SCI LOOP Mode Enable 0 = SCI transmit and receive operate normally 1 = SCI transmit and receive are disconnected from TxD and RxD pins, and transmitter output is fed back into the receiver input WOMS —Wired-OR Mode Option ...

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RE —Receiver Enable 0 = Receiver disabled 1 = Receiver enabled RWU —Receiver Wakeup Control 0 = Normal SCI receiver 1 = Wakeup enabled and receiver interrupts inhibited SBK —Send Break 0 = Break generator off 1 = Break codes ...

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PF —Parity Error Flag PF is set if received data has incorrect parity. Clear PF by reading SCSR1 and then reading SCDR Parity correct 1 = Incorrect parity detected SCSR2 —SCI Status Register 2 Bit 7 6 — ...

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Serial Peripheral Interface The SPI allows the MCU to communicate synchronously with peripheral devices and other micropro- cessors. Data rates can be as high as 2 Mbits per second when configured as a master and 4 Mbits per second ...

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SPCR —Serial Peripheral Control Register Bit 7 6 SPIE SPE DWOM RESET SPIE —Serial Peripheral Interrupt Enable 0 = SPI interrupts disabled 1 = SPI interrupts enabled SPE —Serial Peripheral System Enable 0 = SPI off 1 = ...

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SPR[2:0] —SPI Clock Rate Selects (SPR2 is located in OPT2 register) SPR[2:0] Divide E Clock ...

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OPT2 —System Configuration Options 2 Bit 7 6 LIRDV CWOM RESET LIRDV—LIR Driven Refer to 2 Operating Modes. CWOM —Port C Wired-OR Mode Refer to 6 Parallel Input/Output. Bit 5 —Not implemented Always read zero IRVNE —Internal Read ...

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Analog-to-Digital Converter The analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution technique to convert analog signals to digital values. The A/D converter system contained in M68HC11 K-series MCUs is an 8-channel,8-bit, multiplexed-input, successive-approximation converter. It does not require external ...

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A multiplexer allows the single A/D converter to select one of 16 analog input signals. The A/D converter control logic implements automatic conversion sequences on a selected channel four times or on four channels once each. A write to the ...

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ADCTL —A/D Control/Status Bit 7 6 CCF — RESET CCF — Conversions Complete Flag 0 = Write to ADCTL is complete 1 = A/D conversion cycle is complete Bit 6 — Not implemented Always reads zero SCAN —Continuous ...

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OPTION —System Configuration Options Bit 7 6 ADPU CSEL RESET ADPU —A/D Converter Power- A/D converter powered down 1 = A/D converter powered up CSEL — Clock Select 0 = A/D and EEPROM use system E ...

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Main Timer The timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16- bit range of the counter. ...

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PRESCALER–DIVIDE BY MCU ECLK PR1 PR0 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = TOC4 (HI) ...

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CFORC —Timer Compare Force Bit 7 6 FOC1 FOC2 RESET FOC[5:1] —Force Output Compare Write ones to force compare( Not affected 1 = Output x action occurs Bits [2:0] —Not implemented Always read zero OC1M —Output ...

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TOC1–TOC4 —Timer Output Compare $0016 Bit $0017 Bit $0018 Bit $0019 Bit $001A Bit $001B Bit $001C Bit $001D ...

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TMSK1 —Timer Interrupt Mask 1 Bit 7 6 OC1I OC2I OC3I RESET OC1I–OC4I —Output Compare x Interrupt Enable If the OCxF flag bit is set while the OCxI enable bit is set, a hardware interrupt sequence is requested. ...

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Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. Bits [3:2] —Not implemented Always read zero PR[1:0] —Timer Prescaler Select In normal modes, PR1 and PR0 ...

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PEDGE —Pulse Accumulator Edge Control Refer to 11 Pulse Accumulator. Bit 3 —Not implemented Always reads zero I4/O5 —Input Capture 4/Output Compare 5 Configure TI4/O5 for input capture or output compare 0 = OC5 enabled 1 = IC4 enabled RTR[1:0] ...

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Pulse Accumulator M68HC11 K-series MCUs have an 8-bit counter that can be configured as a simple event counter or for gated time accumulation. The counter can be read or written at any time. The port A bit 7 I/O ...

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TMSK2 —Timer Interrupt Mask 2 Bit 7 6 TOI RTII RESET TOI —Timer Overflow Interrupt Enable Refer to 10 Main Timer. RTII —Real-Time Interrupt Enable Refer to 10 Main Timer. PAOVI —Pulse Accumulator Overflow Interrupt Enable 0 = ...

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PACTL —Pulse Accumulator Control Bit 7 6 — PAEN PAMOD RESET Bit 7 —Not implemented Always reads zero PAEN —Pulse Accumulator System Enable 0 = Pulse accumulator disabled 1 = Pulse accumulator enabled PAMOD —Pulse Accumulator Mode 0 ...

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Pulse-Width Modulation Timer M68HC11 K-series MCUs contains a PWM timer that is composed of a four-channel 8-bit modulator. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM provides up ...

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MCU E CLOCK 128 PCKA1 PCKA2 PCKB1 PCKB2 SELECT PCKB3 PCLK3 PCLK4 PWCNT1 RESET RESET 8 8 8-BIT COMPARE = PWPER1 8-BIT COMPARE = PWDTY1 PWCNT3 RESET RESET 8 8 8-BIT COMPARE = ...

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PWCLK —Pulse-Width Modulation Clock Select Bit 7 6 CON34 CON12 RESET CON34 —Concatenate Channels 3 and 4 Channel 3 is high-order byte, and channel 4 is the low-order byte. The resulting output is available on port H, pin ...

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PCLK3 —Pulse-Width Channel 3 Clock Select 0 = Clock B is source 1 = Clock S is source PCLK2 —Pulse-Width Channel 2 Clock Select 0 = Clock A is source 1 = Clock S is source PCLK1 —Pulse-Width Channel 1 ...

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PWPER1–PWPER4 —Pulse-Width Modulation Timer Period $0068 Bit $0069 Bit $006A Bit $006B Bit RESET PWPER1–PWPER4 Determines period of associated PWM channel PWDTY1–4 ...

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M68HC11 K Series MC68HC11KTS/D MOTOROLA 79 ...

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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