MC68HC11KA1CFN4 Freescale Semiconductor, Inc, MC68HC11KA1CFN4 Datasheet
MC68HC11KA1CFN4
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MC68HC11KA1CFN4 Summary of contents
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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary 8-Bit Microcontroller 1 Introduction The MC68HC11KA4 family of microcontrollers are enhanced derivatives of the MC68HC11F1 and, as shown in the block diagram, include many additional features. The family includes the MC68HC11KA0, MC68HC11KA1, MC68HC11KA3, MC68HC11KA4, ...
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... Kbytes OTPROM $DF 24 Kbytes OTPROM $DF 32 Kbytes OTPROM $DF 32 Kbytes OTPROM $DF 32 Kbytes OTPROM Frequency MC Order Number 4 MHz MC68HC11KA4BCFN4 2 MHz MC68HC11KA1CFN2 3 MHz MC68HC11KA1CFN3 4 MHz MC68HC11KA1CFN4 2 MHz MC68HC11KA1VFN2 3 MHz MC68HC11KA1VFN3 4 MHz MC68HC11KA1VFN4 2 MHz MC68HC11KA1MFN2 3 MHz MC68HC11KA1MFN3 4 MHz MC68HC11KA1MFN4 2 MHz MC68HC11KA0CFN2 3 MHz MC68HC11KA0CFN3 4 MHz ...
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Table 1 Standard Device Ordering Information (Continued) Package Temperature 64-Pin Quad – Flat Pack – – 105 C – 125 C – –40 to ...
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Table 1 Standard Device Ordering Information (Continued) Package Temperature 68-Pin Cerquad – – 105 C – 125 C – – 105 C – 125 ...
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Table 2 Custom ROM Device Ordering Information Package Temperature 68-Pin Plastic – Leaded Chip Carrier – 105 C – 125 C – – 105 C –40 ...
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Table 2 Custom ROM Device Ordering Information (Continued) Package Temperature 64-Pin Quad – Flat Pack – 105 C – – 105 C – –40 ...
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PB7/ADDR15 10 PB6/ADDR14 11 12 PB5/ADDR13 PB4/ADDR12 13 PB3/ADDR11 14 PB2/ADDR10 15 PB1/ADDR9 16 PB0/ADDR8 17 PH0/PW1 18 PH1/PW2 19 PH2/PW3 20 PH3/PW4 21 * XIRQ/V PPE 22 PG7/R/W 23 IRQ PE7/AN7 PPE ...
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PD1/TxD 1 PD2/MISO 2 PD3/MOSI 3 PD4/SCK 4 PD5/ PA7/PAI/OC1 9 PA6/OC2/OC1 10 PA5/OC3/OC1 11 PA4/OC4/OC1 12 PA3/OC5/IC4/OC1 13 PA2/IC1 14 PA1/IC2 15 PA0/IC3 PPE applies to ...
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XTAL EXTAL E 2 XOUT MODA/ LIR MODB/ V STBY PULSE PA7 PAI/OC1 ACCUMULATOR PA6 OC2/OC1 PA5 OC3/OC1 PA4 OC4/OC1 PA3 OC5/IC4/OC1 PA2 IC1 PA1 IC2 PA0 IC3 PB7 ADDR15 PB6 ADDR14 PB5 ADDR13 PB4 ADDR12 PB3 ADDR11 PB2 ADDR10 ...
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Section 1 Introduction 1.1 Features ...................................................................................................................................... 1 2 Operating Modes and On-Chip Memory 2.1 Operating Modes ....................................................................................................................... 11 2.2 On-Chip Memory ....................................................................................................................... 11 3 Erasable Programmable Read-Only Memory 4 Electrically Erasable Programmable Read-Only Memory 5 Resets and Interrupts 6 Parallel ...
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Operating Modes and On-Chip Memory 2.1 Operating Modes In single-chip operating mode, the MC68HC11KA4 is a stand-alone microcontroller with no external ad- dress or data bus. In expanded non-multiplexed operating mode, the MCU can access a 64 Kbyte physical ...
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EXT $1000 EXT $A000 $FFFF SINGLE EXPANDED BOOTSTRAP CHIP NOTES: 1. EPROM can be enabled in special test mode by setting the ROMON bit in the config register after reset. 2. 768 bytes RAM in MC68HC711KA4, 1024 bytes RAM ...
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EXT $1000 EXT $8000 $FFFF SINGLE EXPANDED BOOTSTRAP CHIP NOTES: 1. EPROM can be enabled in special test mode by setting the ROMON bit in the config register after reset. 2. 768 bytes RAM in MC68HC711KA4, 1024 bytes RAM ...
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INIT = $00 REG @ $0000 RAM @ $0080 $0000 REGISTER BLOCK (128 BYTES) $007F $0080 RAM B (640 BYTES) $02FF $0300 RAM A (128 BYTES) $037F Figure 6 RAM and Register Mapping for MC68HC11KA4 INIT = $00 REG @ ...
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Table 4 MC68HC11KA4 Register and Control Bit Assignments Bit 7 6 $0000 PA7 PA6 PA5 $0001 DDA7 DDA6 DDA5 $0002 DDB7 DDB6 DDB5 $0003 DDF7 DDF6 DDF5 $0004 PB7 PB6 PB5 $0005 PF7 PF6 PF5 $0006 PC7 PC6 PC5 $0007 ...
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Table 4 MC68HC11KA4 Register and Control Bit Assignments (Continued) Bit 7 6 $002C 0 0 $002D — — $002E — — $002F — — $0030 CCF 0 SCAN $0031 Bit 7 6 $0032 Bit 7 6 $0033 Bit 7 6 ...
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Table 4 MC68HC11KA4 Register and Control Bit Assignments (Continued) Bit 7 6 $0076 R8 T8 $0077 R7/T7 R6/T6 R5/T5 $0078 — — to $007B — — $007C 0 0 $007D 0 0 $007E PG7 0 $007F DDG7 0 HPRIO — ...
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INIT —RAM and I/O Register Mapping Bit 7 6 RAM3 RAM2 RESET Can be written only once in first 64 cycles out of reset in normal modes or at any time in special mode. RAM[3:0] —Internal RAM Map ...
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NOCOP — COP System Disable Resets to programmed value 0 = COP enabled (forces reset on time-out COP disabled (does not force reset on time-out) ROMON — ROM/EPROM Enable In single-chip mode, ROMON is forced to one out ...
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XDV[1:0] — XOUT Clock Divide Select These two bits control the frequency of the clock that is driven out the XOUT pin. The CLKX bit in the CONFIG register controls whether this clock off. When a clock ...
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Erasable Programmable Read-Only Memory The MC68HC711KA4 has 24 Kbytes of ROM/EPROM. The MC68HC711KA2 has 32 Kbytes of ROM/ EPROM. In all parts, the ROM/EPROM can be mapped to one of two locations in the memory map. The locations are ...
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EPGM — EPROM Program Command If ELAT = 1 then EPGM = Programming power to EPROM array switched off 1 = Power to EPROM array switched on ADDR0 PF0/ADDR0 ADDR1 PF1/ADDR1 ADDR2 PF2/ADDR2 ADDR3 PF3/ADDR3 ADDR4 PF4/ADDR4 ...
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Electrically Erasable Programmable Read-Only Memory The 640-byte on-chip EEPROM is initially located from $0D80 to $0FFF after reset in all modes. It can be mapped to any other 4 Kbyte boundary by writing to the INIT2 register. The EEPROM ...
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BPROT —Block Protect Bit 7 6 BULKP LVPEN RESET Block protect register bits can be written to zero (protection disabled) only once within 64 cycles of a reset in normal modes any time in special mode. ...
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PPROG — EEPROM Programming Control Bit 7 6 ODD EVEN RESET ODD — Program Odd Rows in Half of EEPROM (TEST) EVEN — Program Even Rows in Half of EEPROM (TEST) LVPI — Low Voltage Programming Inhibit LVPI ...
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Resets and Interrupts The MC68HC11KA4/KA2 has three reset vectors and 18 interrupt vectors. The reset vectors are as fol- lows: • RESET, or Power-On Reset • Clock Monitor Fail • COP Failure The 18 interrupt vectors service 22 interrupt ...
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Vector Address FFC0, C1 – FFD4, D5 Reserved FFD6, D7 SCI Serial System FFD8, D9 SPI Serial Transfer Complete FFDA, DB Pulse Accumulator Input Edge FFDC, DD Pulse Accumulator Overflow FFDE, DF Timer Overflow FFE0, E1 Timer Input Capture 4/Output ...
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DLY —Enable Oscillator Start-Up Delay on Exit from STOP stabilization delay on exit from STOP 1 = Stabilization delay enabled on exit from STOP CME — Clock Monitor Enable 0 = Clock monitor disabled; slow clocks can ...
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PSEL[4:0] — Priority Select Bits [4:0] Can be written only while bit I in the CCR is set (interrupts disabled). These bits select one interrupt source to be elevated above all other I-bit related sources. PSELx ...
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Bit 6 — Not implemented Always reads one CLKX — XOUT Clock Refer to 2 Operating Modes and On-Chip Memory. PAREN — Pull-Up Assignment Register Enable Refer to 6 Parallel Input/Output. NOSEC — Security Disable Refer to 2 Operating Modes ...
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Parallel Input/Output The MC68HC11KA4/KA2 has input/output lines, depending on the operating mode. To en- hance the I/O functions, the data bus of this microcontroller is non-multiplexed. The following table is a summary of the configuration and ...
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OPT2 —System Configuration Options 2 Bit 7 6 LIRDV CWOM RESET LIRDV — LIR Driven Refer to 2 Operating Modes and On-Chip Memory. CWOM — Port C Wired-OR Mode 0 = Port C operates normally Port ...
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DDRA — Data Direction Register for Port A Bit 7 6 DDA7 DDA6 RESET DDA[7:0] —Data Direction for Port Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set ...
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DDRF —Data Direction Register for Port F Bit 7 6 DDF7 DDF6 RESET DDF[7:0] — Data Direction for Port Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set ...
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DDRD — Data Direction Register for Port D Bit 7 6 — — RESET Bits [7:6] —Not implemented Always read zero DDD[5:0] — Data Direction for Port Bits set to zero to configure corresponding I/O ...
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PORTH — Port H Data Bit 7 6 — — RESET Alt. Pin — — Func.: Port H pins reset to high-impedance inputs with selectable internal pull-up resistors. DDRH — Data Direction Register for Port H Bit 7 ...
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Serial Communications Interface The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is one of two independent serial I/O subsystems in the MC68HC11KA4/KA2. Rearranging registers and con- trol bits used in previous M68HC11 family devices has enhanced ...
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TRANSMITTER SCDR Tx BUFFER BAUD RATE CLOCK 10 (11) - BIT Tx SHIFT REGISTER H ( PARITY GENERATOR SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 10 SCI Transmitter ...
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RECEIVER BAUD RATE CLOCK DDD0 PIN BUFFER PD0/ AND CONTROL RxD DISABLE DRIVER SCSR2 SCI STATUS 2 WAKE-UP SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 11 SCI Receiver Block Diagram MC68HC11KA4 MC68HC11KA4TS/D 16 DATA (8) 7 ...
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SCBDH/L —SCI Baud Rate Control High/Low Bit 7 6 $0070 BTST BSPL RESET $0071 SBR7 SBR6 RESET BTST — Baud Register Test (TEST) BSPL — Baud Rate Counter Split (TEST) Bit 5 — Not implemented Always ...
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WOMS — Wired-OR Mode for SCI Pins (PD1, PD0; See also DWOM bit in SPCR TxD and RxD operate normally 1 = TxD and RxD are open drains if operating as an output Bit 5 — Not implemented ...
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RE — Receiver Enable 0 = Receiver disabled 1 = Receiver enabled RWU — Receiver Wakeup Control 0 = Normal SCI receiver 1 = Wakeup enabled and receiver interrupts inhibited SBK — Send Break 0 = Break generator off 1 ...
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FE — Framing Error FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR1 with FE set and then reading SCDR Stop bit detected 1 = Zero ...
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Serial Peripheral Interface The SPI allows the MCU to communicate synchronously with peripheral devices and other micropro- cessors. Data rates can be as high as 2 Mbits per second when configured as a master and 4 Mbits per second ...
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SPCR —Serial Peripheral Control Register Bit 7 6 SPIE SPE RESET SPIE — Serial Peripheral Interrupt Enable 0 = SPI interrupts disabled 1 = SPI interrupts enabled SPE — Serial Peripheral System Enable 0 = SPI off 1 ...
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This figure shows transmission order when LSBF = 0 default. If LSBF = 1, data is transferred in reverse order (LSB first). SPR2, SPR1 and SPR0 — SPI Clock Rate Selects (SPR2 is located in OPT2 register) SPR[2: ...
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OPT2 —System Configuration Options 2 Bit 7 6 LIRDV CWOM RESET LIRDV— LIR Driven Refer to 2 Operating Modes and On-Chip Memory. CWOM — Port C Wired-OR Mode Refer to 6 Parallel Input/Output. Bit 5 — Not implemented ...
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Analog-to-Digital Converter The analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution technique to convert analog signals to digital values. The MC68HC11KA4/KA2 A/D converter system is an 8-channel (four channels on 64-pin version), 8-bit, multiplexed-input, successive-approximation converter. It does not ...
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Pins AV and AV provide the supply voltage to the digital portion of the A/D converter. Pins provide the reference supply voltage inputs multiplexer allows the single A/D converter to select one of 16 ...
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ADCTL —A/D Control/Status Bit 7 6 CCF — RESET CCF — Conversions Complete Flag CCF is set after an A/D conversion cycle and cleared when ADCTL is written. Bit 6 — Not implemented Always reads zero SCAN — ...
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OPTION —System Configuration Options Bit 7 6 ADPU CSEL RESET *Can be written only once in first 64 cycles out of reset in normal modes, any time in special mode. ADPU — A/D Converter Power- A/D ...
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Main Timer The timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler. A timer overflow function allows software to extend the system's timing capability beyond the counter's 16-bit range. The timer has three channels ...
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PRESCALER–DIVIDE BY MCU ECLK PR1 PR0 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = TOC4 (HI) ...
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CFORC — Timer Compare Force Bit 7 6 FOC1 FOC2 RESET FOC[5:1] — Force Output Comparison When the FOC bit associated with an output compare circuit is set, the output compare circuit immedi- ately performs the action it ...
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TOC1–TOC4 —Timer Output Compare $0016 Bit 15 14 $0017 Bit 7 6 $0018 Bit 15 14 $0019 Bit 7 6 $001A Bit 15 14 $001B Bit 7 6 $001C Bit 15 14 $001D Bit 7 6 All TOCx register pairs ...
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Table 10 Timer Control Configuration EDGxB TMSK1 — Timer Interrupt Mask 1 Bit 7 6 OC1I OC2I RESET OC1I–OC4I — Output Compare x Interrupt Enable I4/O5I — Input Capture 4 or Output Compare 5 ...
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Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. PAOVI — Pulse Accumulator Overflow Interrupt Enable Refer to 11 Pulse Accumulator. PAII — Pulse Accumulator Interrupt ...
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PACTL —Pulse Accumulator Control Bit 7 6 — PAEN RESET Bit 7 — Not implemented Always reads zero PAEN — Pulse Accumulator System Enable Refer to 11 Pulse Accumulator. PAMOD — Pulse Accumulator Mode Refer to 11 Pulse ...
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Pulse Accumulator The MC68HC11KA4/KA2 has an 8-bit counter that can be configured as a simple event counter or for gated time accumulation. The counter can be read or written at any time. The port A bit 7 I/O pin ...
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TMSK2 —Timer Interrupt Mask 2 Bit 7 6 TOI RTII RESET TOI — Timer Overflow Interrupt Enable Refer to 10 Main Timer. RTII — Real-Time Interrupt Enable Refer to 10 Main Timer. PAOVI — Pulse Accumulator Overflow Interrupt ...
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PACTL —Pulse Accumulator Control Bit 7 6 — PAEN RESET Bit 7 — Not implemented Always reads zero PAEN — Pulse Accumulator System Enable 0 = Pulse accumulator disabled 1 = Pulse accumulator enabled PAMOD — Pulse Accumulator ...
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Pulse-Width Modulation Timer The MC68HC11KA4/KA2 MCU contains a PWM timer that is composed of a four-channel 8-bit modu- lator. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM provides ...
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MCU E CLOCK 128 PCKA1 PCKA2 PCKB1 PCKB2 SELECT PCKB3 PCLK3 PCLK4 PWCNT1 RESET RESET 8 8 8-BIT COMPARE = PWPER1 8-BIT COMPARE = PWDTY1 PWCNT3 RESET RESET 8 8 8-BIT COMPARE = ...
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PWCLK —Pulse-Width Modulation Clock Select Bit 7 6 CON34 CON12 RESET CON34 —Concatenate Channels 3 and 4 Channel 3 is high-order byte, and channel 4 (port H, bit 3) is output. Clock source is determined by PCLK4. 0 ...
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PWPOL —Pulse-Width Modulation Timer Polarity Bit 7 6 PCLK4 PCLK3 RESET PCLK4 — Pulse-Width Channel 4 Clock Select 0 = Clock B is source 1 = Clock S is source PCLK3 — Pulse-Width Channel 3 Clock Select 0 ...
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PWCNT[1:4] — Pulse-Width Modulation Timer Counter $0064 Bit 7 6 $0065 Bit 7 6 $0066 Bit 7 6 $0067 Bit 7 6 RESET PWCNT[1:4] Begins count using whichever clock was selected PWPER[1:4] —Pulse-Width Modulation Timer ...
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MC68HC11KA4 MC68HC11KA4TS/D MOTOROLA 67 ...
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