MC68HC908JK3MDW Freescale Semiconductor, Inc, MC68HC908JK3MDW Datasheet

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MC68HC908JK3MDW

Manufacturer Part Number
MC68HC908JK3MDW
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
HCMOS Microcontroller Unit
MC68HRC908JK1
MC68HRC908JK3
MC68HRC908JL3
MC68HC908JK1
MC68HC908JK3
MC68HC908JL3
TECHNICAL DATA
MC68HC908JL3/H
Rev. 1.0

Related parts for MC68HC908JK3MDW

MC68HC908JK3MDW Summary of contents

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MC68HC908JK1 MC68HRC908JK1 MC68HC908JK3 MC68HRC908JK3 MC68HC908JL3 MC68HRC908JL3 HCMOS Microcontroller Unit TECHNICAL DATA MC68HC908JL3/H Rev. 1.0 ...

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Technical Data — MC68H(R)C908JL3 Section 1. General Description . . . . . . . . . . . . . . . . . . . .21 Section 2. Memory . . . . . . . . . ...

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List of Sections Technical Data 4 MC68H(R)C908JL3 List of Sections Rev. 1.0 — MOTOROLA ...

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Technical Data — MC68H(R)C908JL3 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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T able of Contents 4.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5 ...

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Section 7. System Integration Module (SIM) 7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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T able of Contents 7.8.1 7.8.2 7.8.3 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Security ...

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T able of Contents Section 11. Analog-to-Digital Converter (ADC) 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Port ...

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T able of Contents 15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 17.4.1 17.4.2 17.4.3 17.4.4 17.5 Break ...

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T able of Contents 19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Technical Data — MC68H(R)C908JL3 Figure 1-1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures Figure 7-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 84 7-12 Interrupt Status Register 1 (INT1). ...

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Figure 11-4 ADC Data Register (ADR 145 11-5 ADC Input Clock Register (ADICLK) ...

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List of Figures Figure 17-4 Break Address Register High (BRKH 188 17-5 Break Address Register Low (BRKL ...

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Technical Data — MC68H(R)C908JL3 Table 1-1 Summary of Device Variations . . . . . . . . . . . . . . . . . . . . . . . . . 21 1-2 Pin Functions . ...

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List of T ables Table 12-1 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Technical Data — MC68H(R)C908JL3 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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General Description 1.3 Features Features of the MC68H(R)C908JL3 include the following: • High-performance M68HC08 architecture • Fully upward-compatible object code with M6805, M146805, and M68HC05 Families • Low-power design; fully static with stop and wait modes • 5V and 3V ...

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System protection features: – Optional computer operating properly (COP) reset – Optional low-voltage detection with reset and selectable trip – Illegal opcode detection with reset – Illegal address detection with reset • Master reset pin with internal pull-up and ...

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CPU CONTROL CPU REGISTERS ADC[0:7]/ PTB[0:7] ADC[11:8]/ COND CODE REG PTD[0:3] 128 BYTES RAM RST, IRQ1: PIN HAS INTERNAL 30K PULL-UP PTD[6:7]: PINS HAVE 25mA OPEN-DRAIN OUTPUT & PROGRAMMABLE 5K PULL-UP PTA[0:5], PTD[2:3], PTD[6:7]: PIN HAS LED DRIVE PTA[0:6]: PINS ...

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Pin Assignments The MC68H(R)C908JL3 is available in 28-pin packages and the MC68H(R)C908JK3/JK1 in 20-pin packages. assignment for the two packages. IRQ1 PTA0 VSS OSC1 OSC2/PTA6 PTA1 VDD PTA2 PTA3 PTB7 PTB6 PTB5 PTD7 PTD6 28-PIN ASSIGNMENT MC68H(R)C908JL3 Rev. 1.0 ...

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General Description 1.6 Pin Functions Description of the pin functions are provided in PIN NAME PIN DESCRIPTION VDD Power supply. VSS Power supply ground RESET input, active low. RST With Internal pull-up and schmitt trigger input. External IRQ pin. With ...

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Technical Data — MC68H(R)C908JL3 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Memory $0000 I/O REGISTERS 64 BYTES $003F $0040 RESERVED 64 BYTES $007F $0080 RAM 128 BYTES $00FF $0100 UNIMPLEMENTED 60160 BYTES $EBFF $EC00 FLASH MEMORY MC68H(R)C908JL3/JK3 $FBFF 4096 BYTES $FC00 MONITOR ROM 512 BYTES $FDFF $FE00 BREAK STATUS REGISTER (BSR) ...

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I/O Section Addresses $0000–$003F, shown in control, status, and data registers. Additional I/O registers have the following addresses: • $FE00 (Break Status Register, BSR) • $FE01 (Reset Status Register, RSR) • $FE02 (Reserved, SUBAR) • $FE03 (Break Flag Control ...

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Memory Addr. Register Name Bit 7 Read: Port A Data Register $0000 Write: (PTA) Reset: Read: PTB7 Port B Data Register $0001 Write: (PTB) Reset: Read: $0002 Unimplemented Write: Read: PTD7 Port D Data Register $0003 Write: (PTD) Reset: Read: ...

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Addr. Register Name Bit 7 Read: $000B Unimplemented Write: $000C Read: Port A Input Pull-up PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 $000D Enable Register Write: (PTAPUE) Reset: $000E Read: Write: Unimplemented $0019 Read: Keyboard Status and $001A Control ...

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Memory Addr. Register Name Bit 7 Read: Bit15 TIM Counter Register $0021 High Write: (TCNTH) Reset: Read: Bit7 TIM Counter Register $0022 Low Write: (TCNTL) Reset: Read: TIM Counter Modulo Bit15 $0023 Register High Write: (TMODH) Reset: Read: TIM Counter ...

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Addr. Register Name Bit 7 $002B Read: Write: Unimplemented $003B Read: COCO ADC Status and Control $003C Register Write: (ADSCR) Reset: Read: AD7 ADC Data Register $003D Write: (ADR) Reset: Read: ADIV2 ADC Input Clock Register $003E Write: (ADICLK) Reset: ...

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Memory Addr. Register Name Bit 7 Read: IF14 Interrupt Status Register 2 $FE05 Write: (INT2) Reset: Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset: Read: $FE07 Reserved Write: Read: FLASH Control Register $FE08 Write: (FLCR) Reset: Read: BPR7 FLASH ...

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Vector Priority Lowest Highest MC68H(R)C908JL3 Rev. 1.0 — MOTOROLA . Table 2-1. Vector Addresses Vector Address Vector $FFDE ADC Conversion Complete Vector (High) IF15 $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Vector (High) IF14 $FFE1 Keyboard Vector (Low) IF13 ...

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Memory Technical Data 36 MC68H(R)C908JL3 Memory Rev. 1.0 — MOTOROLA ...

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Technical Data — MC68H(R)C908JL3 Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Random-Access Memory (RAM) During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may ...

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Technical Data — MC68H(R)C908JL3 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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FLASH Memory (FLASH) 4.3 Functional Description The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user vectors. The minimum size of FLASH memory that can be erased is 64 bytes; and ...

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High voltage enabled to array and charge pump High voltage disabled to array and charge pump off MASS — Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or block ...

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FLASH Memory (FLASH) 5. Wait for a time t 6. Clear the ERASE bit. 7. Wait for a time Clear the HVEN bit. 9. After time, t again. NOTE: Programming and erasing of FLASH locations cannot be performed ...

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FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program ...

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FLASH Memory (FLASH) NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 6 to step 10), must not exceed the maximum ...

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Algorithm for programming a row (32 bytes) of FLASH memory NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step ...

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FLASH Memory (FLASH) 4.9 FLASH Block Protect Register The FLASH Block Protect Register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the FLASH memory. Address: $FE09 Bit ...

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Technical Data — MC68H(R)C908JL3 Section 5. Configuration Register (CONFIG) 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Configuration Register (CONFIG) 5.3 Functional Description The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various ...

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Address: $001F Bit 7 Read: COPRS Write: Reset: COPRS — COP reset period selection bit 1 = COP reset cycle = ( COP reset cycle = (2 LVID — Low Voltage Inhibit Disable Bit 1 = Low Voltage ...

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Configuration Register (CONFIG) Technical Data 50 Configuration Register (CONFIG) MC68H(R)C908JL3 Rev. 1.0 — MOTOROLA ...

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Technical Data — MC68H(R)C908JL3 Section 6. Central Processor Unit (CPU) 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Central Processor Unit (CPU) 6.3 Features • Object code fully upward-compatible with M68HC05 Family • 16-bit stack pointer with stack manipulation instructions • 16-bit index register with x-register manipulation instructions • 8-MHz CPU internal bus frequency • 64-Kbyte program/data memory ...

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Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: Write: Reset: MC68H(R)C908JL3 Rev. 1.0 — MOTOROLA 7 0 ACCUMULATOR (A) ...

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Central Processor Unit (CPU) 6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index ...

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Bit 15 Read: Write: Reset: 0 NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, ...

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Central Processor Unit (CPU) 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Bit 7 Read: Write: Reset Indeterminate V — Overflow Flag The CPU sets the overflow flag ...

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I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU ...

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Central Processor Unit (CPU) C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such ...

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Stop Mode The STOP instruction: • Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I ...

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Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form ADC # opr ADC opr ADC opr ADC opr ,X Add with Carry ADC opr ,X ADC ,X ADC opr ,SP ADC opr ,SP ADD # opr ADD ...

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Table 6-1. Instruction Set Summary Source Operation Form BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal Branch if Greater Than or Equal To BGE opr (Signed Operands) Branch if Greater Than (Signed BGT ...

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Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form BRCLR n , opr , rel Branch if Bit Clear BRN rel Branch Never BRSET n , opr , rel Branch if Bit n in ...

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Table 6-1. Instruction Set Summary Source Operation Form CMP # opr CMP opr CMP opr CMP opr ,X Compare A with M CMP opr ,X CMP ,X CMP opr ,SP CMP opr ,SP COM opr COMA COMX Complement (One’s Complement) ...

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Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form EOR # opr EOR opr EOR opr EOR opr ,X Exclusive OR M with A EOR opr ,X EOR ,X EOR opr ,SP EOR opr ,SP INC opr ...

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Table 6-1. Instruction Set Summary Source Operation Form LSR opr LSRA LSR X Logical Shift Right LSR opr ,X LSR ,X LSR opr ,SP MOV opr,opr MOV opr, X+ Move MOV # opr,opr MOV X+ ,opr MUL Unsigned multiply NEG ...

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Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form ROR opr RORA RORX Rotate Right through Carry ROR opr ,X ROR ,X ROR opr ,SP RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine ...

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Table 6-1. Instruction Set Summary Source Operation Form SUB # opr SUB opr SUB opr SUB opr ,X Subtract SUB opr ,X SUB ,X SUB opr ,SP SUB opr ,SP SWI Software Interrupt TAP Transfer A to CCR TAX Transfer ...

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Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form A Accumulator C Carry/borrow bit CCR Condition code register dd Direct address of operand dd rr Direct address of operand and relative offset of branch instruction DD Direct ...

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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...

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Central Processor Unit (CPU) Technical Data 70 Central Processor Unit (CPU) MC68H(R)C908JL3 Rev. 1.0 — MOTOROLA ...

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Technical Data — MC68H(R)C908JL3 Section 7. System Integration Module (SIM) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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System Integration Module (SIM) 7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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STOP/WAIT CONTROL VDD CLOCK CONTROL INTERNAL PULL-UP RESET POR CONTROL PIN LOGIC RESET PIN CONTROL SIM RESET STATUS REGISTER INTERRUPT CONTROL AND PRIORITY DECODE Figure 7-1. SIM Block Diagram Table 7-1. Signal Name Conventions Signal Name 2OSCOUT Buffered clock from ...

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System Integration Module (SIM) Addr. Register Name Bit 7 Read: Break Status Register $FE00 Write: (BSR) Reset: Note: Writing a logic 0 clears SBSW. Read: POR Reset Status Register $FE01 Write: (RSR) POR: Read: $FE02 Reserved Write: Reset: Read: Break ...

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SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in OSCILLATOR OSCILLATOR 7.3.1 Bus ...

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System Integration Module (SIM) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or ...

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OSCOUT RST IAB PC 7.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 2OSCOUT cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for ...

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System Integration Module (SIM) The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 7.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on ...

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Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The ...

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System Integration Module (SIM) 7.4.2.5 LVI Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the V voltage falls to the LVI trip voltage V DD reset status register (SRSR) is set, and the external reset ...

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SIM Counter and Reset States External reset has no effect on the SIM counter. (See for details.) The SIM counter is free-running after all reset states. (See 7.4.2 Active Resets from Internal Sources internal reset recovery sequences.) 7.6 Exception ...

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System Integration Module (SIM) FROM RESET BREAK INTERRUPT? I BIT SET? YES I BIT SET? INTERRUPT? INTERRUPT? (As many interrupts as exist on chip) FETCH NEXT INSTRUCTION INSTRUCTION? INSTRUCTION? Figure 7-8. Interrupt Processing Technical Data 82 YES NO NO YES ...

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At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register ...

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System Integration Module (SIM) set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. ...

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SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software ...

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System Integration Module (SIM) 7.6.2.1 Interrupt Status Register 1 Address: $FE04 Bit 7 Read: Write: Reset IF5 — Interrupt Flags F F These flags indicate the presence of interrupt requests from the sources shown in ...

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Interrupt Status Register 3 Address: $FE06 Bit 7 Read: Write: Reset — Interrupt Flags F These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt ...

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System Integration Module (SIM) protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in ...

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If the COP disable bit, COPD, in the mask option register is logic zero, then the computer operating properly module (COP) is enabled and remains active in wait mode. IAB IDB R/W NOTE: Previous data can be ...

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System Integration Module (SIM) 7.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the ...

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INT/BREAK IAB STOP +1 Figure 7-19. Stop Mode Recovery from Interrupt or Break 7.8 SIM Registers The SIM has three memory mapped registers. mapping of these registers. Address $FE00 $FE01 $FE03 7.8.1 Break Status Register (BSR) The break status ...

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System Integration Module (SIM) SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset ...

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Address: $FE01 Bit 7 Read: POR Write: POR: POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin ...

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System Integration Module (SIM) 7.8.3 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU break state. Address: Bit 7 Read: BCFE Write: Reset: 0 ...

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Technical Data — MC68H(R)C908JL3 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Oscillator (OSC) 8.3 X-tal Oscillator (MC68HC908xxx) The X-tal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source. In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, ...

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The series resistor (R oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information. 8.4 RC Oscillator (MC68HRC908xxx) The RC oscillator circuit is designed ...

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Oscillator (OSC) 8.5 I/O Signals The following paragraphs describe the oscillator I/O signals. 8.5.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit. 8.5.2 Crystal Amplifier ...

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RC Oscillator Clock (RCCLK) RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the external R and C. shows only the logical relation of RCCLK to OSC1 and may not represent ...

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Oscillator (OSC) 8.7 Oscillator During Break Mode The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state. Technical Data 100 MC68H(R)C908JL3 Oscillator (OSC) Rev. 1.0 — MOTOROLA ...

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Technical Data — MC68H(R)C908JL3 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Monitor ROM (MON) 9.3 Features Features of the monitor ROM include the following: • Normal user-mode pin functionality • One pin dedicated to serial communication between monitor ROM and host computer • Standard mark/space non-return-to-zero (NRZ) communication with host computer ...

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RC CIRCUIT V DD (FOR MC68HRC908xxx) See Figure 18-1 values vs. frequency MC145407 + DB- NOTES: 1. X-tal circuit replaced ...

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Monitor ROM (MON) 9.4.1 Entering Monitor Mode Table 9-1 specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met ...

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entry (Table 9-1 the external clock input to OSC1. If PTB3 is high with V to IRQ1 upon monitor mode entry frequency is a divide-by-four of the external clock input to OSC1. Holding the PTB3 pin ...

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Monitor ROM (MON) Figure 9-2. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the ...

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Table 9-2 and monitor mode. Modes User Monitor Notes the high voltage (V asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register. When the host ...

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Monitor ROM (MON) 9.4.3 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See START BIT START $A5 BIT START BREAK BIT The data transmit and receive rate can be anywhere from 4800 baud ...

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Break Signal A start bit followed by nine low bits is a break signal. (See When the monitor receives a break signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal. ...

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Monitor ROM (MON) Table 9-4. READ (Read Memory) Command Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ECHO ...

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Table 9-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO ...

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Monitor ROM (MON) Table 9-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP READSP SP HIGH ECHO Table 9-9. ...

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Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD ...

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Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH ...

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Technical Data — MC68H(R)C908JL3 Section 10. Timer Interface Module (TIM) 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Timer Interface Module (TIM) 10.2 Introduction This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 10-1 10.3 Features Features ...

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Functional Description Figure 10-1 the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM ...

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Timer Interface Module (TIM) Addr. Register Name Read: TIM Status and Control $0020 Register Write: (TSC) Reset: Read: TIM Counter Register High $0021 Write: (TCNTH) Reset: Read: TIM Counter Register Low $0022 Write: (TCNTL) Reset: Read: TIM Counter Modulo $0023 ...

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Read: TIM Channel 1 $0029 Register High Write: (TCH1H) Reset: Read: TIM Channel 1 $002A Register Low Write: (TCH1L) Reset: Figure 10-2. TIM I/O Register Summary 10.5.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler ...

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Timer Interface Module (TIM) 10.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in unbuffered because changing the output compare value requires writing the new value over the old value currently in the ...

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TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel ...

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Timer Interface Module (TIM) TCHx The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) ...

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The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel ...

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Timer Interface Module (TIM) (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE: In buffered PWM signal generation, do not write new pulse width values to the ...

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Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the ...

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Timer Interface Module (TIM) If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 10.8 TIM During Break Interrupts A break interrupt stops the TIM counter. The system integration ...

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I/O Registers The following I/O registers control and monitor operation of the TIM: • TIM status and control register (TSC) • TIM control registers (TCNTH:TCNTL) • TIM counter modulo registers (TMODH:TMODL) • TIM channel status and control registers (TSC0 ...

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Timer Interface Module (TIM) overflow occurs before the clearing sequence is complete, then writing logic zero to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. ...

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PS2 PS1 10.10.2 TIM Counter Registers (TCNTH:TCNTL) The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches ...

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Timer Interface Module (TIM) Address: $0021 Bit 7 Read: Bit15 Write: Reset: Address: $0022 Bit 7 Read: Bit7 Write: Reset: Figure 10-5. TIM Counter Registers (TCNTH:TCNTL) 10.10.3 TIM Counter Modulo Registers (TMODH:TMODL) The read/write TIM modulo registers contain the modulo ...

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Address: $0023 Bit 7 Read: Bit15 Write: Reset: Address: $0024 Bit 7 Read: Bit7 Write: Reset: Figure 10-6. TIM Counter Modulo Registers (TMODH:TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers. 10.10.4 TIM Channel Status ...

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Timer Interface Module (TIM) Address: $0025 Bit 7 Read: CH0F Write: Reset: Address: $0028 Bit 7 Read: CH1F Write: Reset: Figure 10-7. TIM Channel Status and Control Registers (TSC0:TSC1) CHxF — Channel x Flag Bit When channel ...

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MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to ...

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Timer Interface Module (TIM) MSxB MSxA NOTE: Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two ...

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OVERFLOW TCHx CHxMAX 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after ...

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Timer Interface Module (TIM) Address: $0026 Bit 7 Read: Bit15 Write: Reset: Address: $0027 Bit 7 Read: Bit7 Write: Reset: Address: $0029 Bit 7 Read: Bit15 Write: Reset: Address: $02A Bit 7 Read: Bit7 Write: Reset: Figure 10-9. TIM Channel ...

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Technical Data — MC68H(R)C908JL3 Section 11. Analog-to-Digital Converter (ADC) 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Analog-to-Digital Converter (ADC) 11.3 Features Features of the ADC module include: • 12 channels with multiplexed input • Linear successive approximation with monotonicity • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • ...

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INTERNAL DATA BUS READ DDRB/DDRD WRITE DDRB/DDRD RESET WRITE PTB/PTD READ PTB/PTD ADC DATA REGISTER CONVERSION COMPLETE INTERRUPT LOGIC AIEN COCO BUS CLOCK ADIV[2:0] Figure 11-2. ADC Block Diagram 11.4.1 ADC Port I/O Pins PTB0–PTB7 and PTD0–PTD3 are general-purpose I/O ...

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Analog-to-Digital Converter (ADC) Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a ...

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Accuracy and Precision The conversion process is monotonic and has no missing codes. 11.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is ...

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Analog-to-Digital Converter (ADC) 11.7.1 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the 12 ADC channels to the ADC module. 11.8 I/O Registers These I/O registers control and monitor ADC operation: • ADC Status and ...

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AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset ...

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Analog-to-Digital Converter (ADC) Table 11-1. MUX Channel Select CH4 CH3 CH2 ...

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Address: $003D Bit 7 Read: AD7 Write: Reset: 11.8.3 ADC Input Clock Register This register selects the clock frequency for the ADC. Address: $003E Bit 7 Read: ADIV2 Write: Reset: Figure 11-5. ADC Input Clock Register (ADICLK) ADIV2:ADIV0 — ADC ...

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Analog-to-Digital Converter (ADC) ADIV2 don’t care Technical Data 146 Table 11-2. ADC Clock Divide Ratio ADIV1 ADIV0 Analog-to-Digital Converter (ADC) ADC Clock Rate ...

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Technical Data — MC68H(R)C908JL3 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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I/O Ports Addr. Register Name Bit 7 Read: Port A Data Register $0000 Write: (PTA) Reset: Read: PTB7 Port B Data Register $0001 Write: (PTB) Reset: Read: PTD7 Port D Data Register $0003 Write: (PTD) Reset: Read: Data Direction Register ...

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Port A Data Register (PTA) The port A data register (PTA) contains a data latch for each of the seven port A pins. Address: $0000 Bit 7 Read: Write: Reset: Additional Functions: PTA[6:0] — Port A Data Bits These ...

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I/O Ports 12.4.1 Data Direction Register A (DDRA) Data direction register A determines whether each port A pin is an input or an output. Writing a logic one to a DDRA bit enables the output buffer for the corresponding port ...

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READ DDRA ($0004) WRITE DDRA ($0004) WRITE PTA ($0000) READ PTA ($0000) When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on ...

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I/O Ports Address: $000D Bit 7 Read: PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE2 PTAPUE0 Write: Reset: Figure 12-5. Port A Input Pull-up Enable Register (PTAPUE) PTA6EN — Enable PTA6 on OSC2 This read/write bit configures the OSC2 pin function ...

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Port B Port 8-bit special function port that shares all eight of its port pins with the Analog-to-Digital converter (ADC) module, See 12.5.1 Port B Data Register (PTB) The port B data register contains a data ...

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I/O Ports DDRB[7:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs Corresponding port B pin configured as output 0 = Corresponding port ...

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Port D Port 8-bit special function port that shares two of its pins with Timer Interface Module, (see with Analog to Digital Conversion Module (see PTD7 each has high current drive (25mA sink) and programmable pull- ...

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I/O Ports 12.6.2 Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a logic one to a DDRD bit enables the output buffer for the corresponding port ...

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When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the ...

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I/O Ports Technical Data 158 MC68H(R)C908JL3 I/O Ports Rev. 1.0 — MOTOROLA ...

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Technical Data — MC68H(R)C908JL3 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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External Interrupt (IRQ) 13.4 Functional Description A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Figure 13-1 Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An interrupt latch remains set ...

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NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt Exception Control ACK1 RESET VECTOR FETCH DECODER V DD IRQPUD V I NTERNAL DD PULLUP DEVICE D CK IRQ1 MODE1 Addr. Register ...

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External Interrupt (IRQ) • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK1 bit in the ...

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IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ1 latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during ...

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External Interrupt (IRQ) IRQF1 — IRQ1 Flag This read-only status bit is high when the IRQ1 interrupt is pending IRQ1 interrupt pending 0 = IRQ1 interrupt not pending ACK1 — IRQ1 Interrupt Request Acknowledge Bit Writing a logic ...

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Technical Data — MC68H(R)C908JL3 Section 14. Keyboard Interrupt Module (KBI) 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Keyboard Interrupt Module (KBI) Addr. Register Name Bit 7 Read: Keyboard Status $001A and Control Register Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable $001B Write: Register (KBIER) Reset: Figure 14-1. KBI I/O Register Summary 14.4 Functional Description KBI0 . KBIE0 ...

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A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. • If the keyboard interrupt ...

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Keyboard Interrupt Module (KBI) If the MODEK bit is clear, the keyboard interrupt pin is falling-edge- sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and ...

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Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction register ...

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Keyboard Interrupt Module (KBI) ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port-A. ACKK always reads as logic 0. Reset clears ACKK. IMASKK— Keyboard Interrupt Mask Bit Writing a ...

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Wait Mode The keyboard modules remain active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 14.6 Stop Mode The keyboard module ...

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Keyboard Interrupt Module (KBI) Technical Data 172 Keyboard Interrupt Module (KBI) MC68H(R)C908JL3 Rev. 1.0 — MOTOROLA ...

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Technical Data — MC68H(R)C908JL3 Section 15. Computer Operating Properly (COP) 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Computer Operating Properly (COP) 15.3 Functional Description Figure 15-1 2OSCOUT (1) INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG1) NOTE: 1. See SIM section for ...

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NOTE: Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 the COP bit in ...

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Computer Operating Properly (COP) 15.4.5 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter. 15.4.6 COPD (COP Disable) The COPD signal reflects the state ...

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COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte ...

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Computer Operating Properly (COP) 15.8.2 Stop Mode Stop mode turns off the 2OSCOUT input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period ...

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Technical Data — MC68H(R)C908JL3 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Low Voltage Inhibit (LVI) 16.4 Functional Description Figure 16-1 after a reset. The LVI module contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to monitor V voltage. The LVI trip voltage selection bits ...

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Address: $001F Bit 7 Read: COPRS Write: Reset: Figure 16-3. Configuration Register 1 (CONFIG1) LVID — Low Voltage Inhibit Disable Bit 1 = Low voltage inhibit disabled 0 = Low voltage inhibit enabled LVIT1, LVIT0 — LVI Trip Voltage Selection ...

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Low Voltage Inhibit (LVI) Technical Data 182 MC68H(R)C908JL3 Low Voltage Inhibit (LVI) Rev. 1.0 — MOTOROLA ...

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Technical Data — MC68H(R)C908JL3 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Break Module (BREAK) 17.3 Features Features of the break module include the following: • Accessible I/O registers during the break Interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts 17.4 Functional Description When the ...

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IAB[15:0] Addr. Register Name Bit 7 Read: Break Status Register $FE00 Write: (BSR) Reset: Read: Break Flag Control BCFE $FE03 Register Write: (BFCR) Reset: Read: Break Address High Bit15 $FE0C Register Write: (BRKH) Reset: Read: Break Address low Bit7 $FE0D ...

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Break Module (BREAK) 17.4.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software ...

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Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits. Address: $FE0E Bit 7 Read: BRKE Write: Reset: Figure 17-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable ...

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Break Module (BREAK) 17.5.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: $FE0C Bit 7 Read: Bit 15 Write: Reset: Figure 17-4. Break ...

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SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW ...

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Break Module (BREAK) 17.5.4 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU break state. Address: Bit 7 Read: BCFE Write: Reset ...

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Technical Data — MC68H(R)C908JL3 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Electrical Specifications 18.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to Sections conditions. ...

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Functional Operating Range Characteristic Operating temperature range Operating voltage range 18.5 Thermal Characteristics Characteristic Thermal resistance 20-Pin PDIP 20-Pin SOIC 28-Pin PDIP 28-Pin SOIC I/O pin power dissipation Power dissipation (2) Constant Average junction temperature Maximum junction temperature NOTES: ...

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Electrical Specifications 18 Electrical Characteristics Table 18-4. DC Electrical Characteristics (5V) (1) Characteristic Output high voltage (I = –2.0mA) LOAD PTA0–PTA6, PTB0–PTB7, PTD0–PTD7 Output low voltage (I = 1.6mA) LOAD PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5 Output low ...

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Table 18-4. DC Electrical Characteristics (5V) (1) Characteristic NOTES 4.5 to 5.5 Vdc Vdc Typical values reflect average measurements at midpoint of voltage range only. 3. Run (operating) ...

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Electrical Specifications 18.8 5V Oscillator Characteristics Table 18-6. Oscillator Component Specifications (5V) Characteristic Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock (1) reference frequency (2) Crystal load capacitance (2) Crystal fixed capacitance (2) Crystal tuning capacitance Feedback bias resistor ...

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DC Electrical Characteristics Table 18-7. DC Electrical Characteristics (3V) (1) Characteristic Output high voltage (I = –1.0mA) LOAD PTA0–PTA6, PTB0–PTB7, PTD0–PTD7 Output low voltage (I = 0.8mA) LOAD PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5 Output low voltage (I ...

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Electrical Specifications Table 18-7. DC Electrical Characteristics (3V) (1) Characteristic NOTES 2.7 to 3.3 Vdc Vdc Typical values reflect average measurements at midpoint of voltage range only. 3. ...

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Oscillator Characteristics Table 18-9. Oscillator Component Specifications (3V) Characteristic Crystal frequency, XTALCLK RC oscillator frequency, RCCLK External clock (1) reference frequency (2) Crystal load capacitance (2) Crystal fixed capacitance (2) Crystal tuning capacitance Feedback bias resistor (2), (3) ...

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Electrical Specifications 18.12 Typical Supply Currents Figure 18-3. Typical Operating I 2 1.75 1.50 1.25 1 0.75 0.5 0. Figure 18-4. Typical Wait Mode I 0.5 0.4 ...

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