N80960SA-16 Intel Corporation, N80960SA-16 Datasheet
N80960SA-16
Available stocks
Related parts for N80960SA-16
N80960SA-16 Summary of contents
Page 1
... Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ trademark of Digital Equipment Corporation) Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. ...
Page 2
EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS CONTENTS ® 1.0 THE i960 PROCESSOR ...........................................................................................................................1 1.1 Key Performance Features .................................................................................................................2 1.1.1 Memory Space And Addressing Modes ...................................................................................4 1.1.2 Data Types ...............................................................................................................................4 1.1.3 Large Register Set ...................................................................................................................4 1.1.4 Multiple Register Sets ...
Page 3
LIST OF FIGURES Figure 1 The 80960SB Processor’s Highly Parallel Architecture ................................................................ 0 Figure 2 80960SB Programming Environment ........................................................................................... 1 Figure 3 Instruction Formats ...................................................................................................................... 4 Figure 4 Multiple Register Sets Are Stored On-Chip .................................................................................. 6 Figure 5 Connection Recommendation ...
Page 4
...
Page 5
THE i960 PROCESSOR The 80960SB is a member of the 32-bit architecture from Intel known as the i960 processor family. These microprocessors were especially designed to serve the needs of embedded applications. The embedded market includes applications as ...
Page 6
Key Performance Features The 80960SB architecture is based on the most recent advances in microprocessor technology and is grounded in Intel’s long experience in the design and manufacture of embedded microprocessors. Many features contribute to the 80960SB’s excep- ...
Page 7
Table 1. 80960SB Instruction Set Data Movement Arithmetic Load Add Store Subtract Move Multiply Load Address Divide Remainder Modulo Shift Extended Multiply Extended Divide Comparison Branch Compare Unconditional Branch Conditional Compare Conditional Branch Compare and Increment Compare and Branch Compare ...
Page 8
Control Opcode Compare and Opcode Branch Register to Opcode Register Memory Access--- Opcode Short Memory Access--- Opcode Long Figure 3. Instruction Formats 1.1.1 Memory Space And Addressing Modes The 80960SB offers a linear programming environment so that all programs ...
Page 9
These registers perform the same function as the general-purpose registers provided in other popular microprocessors. The term global refers to the fact that these registers retain their contents across procedure calls. The local registers, on ...
Page 10
REGISTER CACHE ONE OF FOUR LOCAL REGISTER SETS Figure 4. Multiple Register Sets Are Stored On-Chip 1.1.7 Floating-Point Arithmetic In the 80960SB, floating-point arithmetic has been made an integral part of the architecture. Having the floating-point unit integrated on ...
Page 11
Interrupt Handling The 80960SB can be interrupted in one of two ways: by the activation of one of four interrupt pins or by sending a message on the processor’s data bus. The 80960SB is unusual in that it automatically ...
Page 12
Table 4. 80960SB Pin Description: Bus Signals (Sheet NAME TYPE CLK2 I SYSTEM CLOCK provides the fundamental timing for 80960SB systems divided by two inside the 80960SB to generate the internal processor clock. A31:16 ...
Page 13
Table 4. 80960SB Pin Description: Bus Signals (Sheet NAME TYPE LOCK I/O BUS LOCK prevents bus masters from gaining control of the bus during O.D. Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert LOCK. ...
Page 14
Table 5. 80960SB Pin Description: Support Signals NAME TYPE RESET I RESET clears the processor’s internal logic and causes it to reinitialize. During RESET assertion, the input pins are ignored (except for INT0, INT1, INT3, LOCK), the three-state output ...
Page 15
ELECTRICAL SPECIFICATIONS 2.1 Power and Grounding The 80960SB is implemented in CHMOS IV technology and therefore has modest power require- ments. Its high clock frequency and numerous output buffers (address/data, control, error and arbitration signals) can cause power surges ...
Page 16
V = 5.0V CC 300 250 16 MHz 10 MHz 200 150 100 -60 -40 -20 Figure 6. Typical Supply Current vs. Case Temperature TEMP = +22°C 500 450 4.5V 400 5.0V 350 5.5V 300 250 200 150 ...
Page 17
TEMP = +85°C 300 4.5V 5.0V 250 5.5V 200 150 100 OPERATING FREQUENCY (MHz) Figure 8. Typical Current vs. Frequency (Hot Temp) 2.5 Test Load Circuit Figure 10 illustrates the load circuit used to ...
Page 18
ABSOLUTE MAXIMUM RATINGS* Parameter Maximum Rating Operating Temperature (PLCC) ............ 0°C to +85°C Cas e Operating Temperature (QFP) ............ 0°C to +100°C Cas e Storage Temperature .............................. –65°C to +150° C Voltage on Any Pin (PLCC)................. –0.5V to ...
Page 19
AC Specifications This section describes the AC specifications for the 80960SB pins. All input and output timings are specified relative to the 1.5V level of the rising edge of CLK2 and refer to the time at which the signal ...
Page 20
Table 7. 80960SB AC Characteristics (10 MHz) Symbol Parameter Input Clock T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time 3 (CLK2) T Processor Clock Fall Time (CLK2 ...
Page 21
Table 8. 80960SB AC Characteristics (16 MHz) Symbol Parameter Input Clock T Processor Clock Period (CLK2 Processor Clock Low Time (CLK2 Processor Clock High Time 3 (CLK2) T Processor Clock Fall Time (CLK2 Processor ...
Page 22
HIGH LEVEL (MIN) 0.7V CC LOW LEVEL (MAX) 0. Figure 12. Processor Clock Pulse (CLK2) CLK2 CLK OUTPUTS RESET INT0, INT1, INT3, LOCK NOTE: Initialization parameters must be set up at least four CLK2 periods before the ...
Page 23
T h CLK2 CLK T 12 HOLD T 6 HLDA Figure 14. HOLD Timing 80960SB 19 ...
Page 24
MECHANICAL DATA 3.1 Packaging The 80960SB is available in two package types: • 80-lead quad flat pack (EIAJ QFP). Shown in Figure 15. • 84-lead plastic leaded chip carrier (PLCC). Shown in Figure 16. Dimensions for both package ...
Page 25
A20 12 13 A19 14 A18 15 A17 A16 AD15 AD14 AD13 24 25 AD12 AD11 ...
Page 26
Pinout Table 9. 80960SB QFP Pinout — In Pin Order Pin Signal Pin 1 A22 A21 A20 A19 A18 25 AD6 6 A17 26 AD5 7 ...
Page 27
Table 10. 80960SB QFP Pinout — In Signal Order Signal Pin Signal A1 38 A18 A2 35 A19 A3 34 A20 AD1 30 A21 AD2 29 A22 AD3 28 A23 AD4 27 A24 AD5 26 A25 AD6 25 A26 AD7 ...
Page 28
Table 11. 80960SB PLCC Pinout — In Pin Order Pin Signal Pin A27 24 AD13 4 A26 25 AD12 5 A25 26 AD11 AD10 CC 7 ...
Page 29
Table 12. 80960SB PLCC Pinout — In Signal Order Signal Pin Signal A1 49 A18 A2 46 A19 A3 45 A20 D0 41 A21 AD1 40 A22 AD2 39 A23 AD3 38 A24 AD4 37 A25 AD5 36 A26 AD6 ...
Page 30
Package Thermal Specifications The 80960SB is specified for operation when case temperature is within the range 0°C to +85°C (PLCC) or 0°C to 100°C (QFP). Measure case temperature at the top center of the package. Ambient temper- ature ...
Page 31
WAVEFORMS Figures 17, 18, 19, 20 and 21 show waveforms for various transactions on the 80960SB’s bus. Figure 22 shows a cold reset functional waveform CLK2 CLK ALE AS A31:16 A15:4, ADDR D15:0 A3:1 BE1:0 BLAST W/R ...
Page 32
CLK2 CLK ALE AS A31:16 A15:4, ADDR D D15:0 A3:1 000 BE1:0 BLAST W/R DT/R DEN READY Figure 18. Quad Word Burst Read Transaction With ...
Page 33
CLK2 CLK ALE AS A31:16 A15:4, ADDR DATA D15:0 A3:1 VALID BE1:0 0x BLAST W/R DT/R DEN READY Figure 19. Burst Write Transaction With Wait States (6-8 Bytes Transferred) T ...
Page 34
Figure 20. Accesses Generated by Quad Word Read Bus Request, Misaligned One Byte from Quad Word Boundary Wait States 30 ...
Page 35
CLK2 CLK ALE AS A31:16 A15:4, ADD D15:0 A3:1 BE1 INTA BLAST W/R DT/R DEN LOCK READY Figure 21. Interrupt Acknowledge Cycle ...
Page 36
Figure 22. Cold Reset Waveform 32 ...
Page 37
REVISION HISTORY This data sheet supersedes data sheet 272207-001. The sections significantly changed since the previous revision are: Section 2.3 Connection Recommendations (pg. 11) 2.5 Test Load Circuit (pg. 13) 2.7 DC Characteristics (pg. 14) Data sheet 270917-004 applied ...
Page 38
The sections significantly changed between revisions -003 and -004 of the 80960SA/SB Data Sheet were: Section DC Characteristics Table 7. QFP Package, Thermal Resis- tance — C/Watt Table 8. PLCC Package, Thermal Resis- tance — C/Watt Table 9. 80960SA ...