PDIUSBD12 NXP Semiconductors, PDIUSBD12 Datasheet
PDIUSBD12
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PDIUSBD12 Summary of contents
Page 1
... Mbit/s also designed to be compliant with most device class specifications: imaging class, mass storage devices, communication devices, printing devices and human interface devices. The PDIUSBD12 is ideally suited for many peripherals, such as printer, scanner, external mass storage (Zip drive) and digital still camera ...
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... Multiple interrupt modes to facilitate both bulk and isochronous transfers 3. Ordering information Table 1. Ordering information Outside North North America America PDIUSBD12D PDIUSBD12D PDIUSBD12PW PDIUSBD12PW DH TSSOP28 plastic thin shrink small outline PDIUSBD12_9 Product data sheet 0 extended 5 V supply range of Package Name Description SO28 plastic small outline package; 28 leads; ...
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... INTEGRATED RAM BIT CLOCK RECOVERY MEMORY PHILIPS MANAGEMENT SIE UNIT PARALLEL AND DMA INTERFACE VOUT3 XTAL2 22 XTAL1 PDIUSBD12 21 GL_N 20 RESET_N 19 EOT_N 18 DMACK_N 17 DMREQ 16 WR_N 15 RD_N 004aaa532 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 004aaa796 ...
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... P voltage supply (4 5 operate the IC at 3.3 V, supply 3 both the V pins USB D data line Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus BUS CC CC © Koninklijke Philips Electronics N.V. 2006. All rights reserved. sensing. and VOUT3 ...
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... — selects the data phase This bit is a don’t care in a multiplexed address and data bus configuration and should be tied to HIGH. Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
Page 6
... SoftConnect The connection to the USB is accomplished by connecting D+ (for full-speed USB device) to HIGH through a 1.5 k pull-up resistor. In the PDIUSBD12, the 1.5 k pull-up resistor is integrated on-chip and is not connected to V established through a command sent by the external or system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection to the USB ...
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... I/O ports. This port controls the command or data phase to the PDIUSBD12. The multiplexed address and data bus of the 80C51 can now be directly connected to the data bus of the PDIUSBD12. The address phase will be ignored by the PDIUSBD12. The clock input signal of the 80C51 (pin XTAL1) can be provided by output CLKOUT of the PDIUSBD12 ...
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... In this mode, transfers occur only when the PDIUSBD12 requests them and are terminated when the Byte Count register reaches zero. After the DMA controller is programmed, the DMA ENABLE bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. ...
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... Philips Semiconductors The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In single address mode, the DMA transfer is done using the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In dual address mode, pins DMREQ, DMACK_N and EOT_N are not used; instead CS_N, WR_N and RD_N control signals are used ...
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... Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus [1] Max. Packet size (bytes) OUT [2] OUT [2][3] [4] OUT 64 [ OUT [2] ...
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... OUT endpoint 2 IN control OUT control IN endpoint 1 OUT endpoint 1 IN endpoint 2 OUT endpoint 2 IN selected endpoint selected endpoint Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus Code (Hex) Transaction D0 write write write write or read 1 B ...
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... ADDRESS: The value written becomes the address. ENABLE: Logic 1 enables this function. Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus Code (Hex) Transaction 40 write write write 1 B ...
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... For bit allocation, see Table 5. Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus Power-on value GENERIC/ISOCHRONOUS ENDPOINTS reserved; write 0 004aaa798 0 0 Power-on value reserved NO LAZYCLOCK CLOCK RUNNING INTERRUPT MODE SoftConnect reserved ...
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... For bit allocation, see Table 6. Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus Section 8. Power-on value CLOCK DIVISION FACTOR reserved SET_TO_ONE SOF-ONLY INTERRUPT MODE 004aaa800 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...
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... CPU. This allows the DMA data to be continuous and not interleaved by chunks of these headers. For DMA read operations, the header will be skipped by the PDIUSBD12. See header will be automatically added by the PDIUSBD12. This provides a clean and simple DMA data transfer. Fig 8. Set DMA command: bit allocation ...
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... DMA DIRECTION This bit determines the direction of data flow during a DMA transfer. Logic 1 means from the external shared memory to the PDIUSBD12 (DMA write); logic 0 means from the PDIUSBD12 to the external shared memory (DMA read). DMA ENABLE Writing logic 1 to this bit will start the DMA operation through the assertion of pin DMREQ ...
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... DMA EOT: This bit signifies that the DMA operation is completed. Read Interrupt register, byte 1: bit allocation Description When the PDIUSBD12 does not receive three SOFs, it will go into the suspend state and the SUSPEND CHANGE bit will be HIGH. Any change to the suspend or awake state will set this bit to HIGH and generate an interrupt ...
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... FULL/EMPTY: Logic 1 indicates that the buffer is full, logic 0 indicates an empty buffer. STALL: Logic 1 indicates that the selected endpoint is in the stall state Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus Power-on value ...
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... DATA PID; the received DATA PID was not what was expected Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus Power-on value DATA RECEIVE/TRANSMIT SUCCESS ...
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... The first two bytes will be skipped in the DMA read operation. Therefore, the first read will get data byte 1, the second read will get data byte 2, and so on. The PDIUSBD12 can determine the last byte of this packet through the EOP termination of the USB packet. ...
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... SETUP packet. PDIUSBD12_9 Product data sheet STALLED: Logic 1 indicates the endpoint is stalled. Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus 1 0 Power-on value X 0 STALLED reserved 004aaa806 © ...
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... Interrupt modes [1] INTERRUPT PIN MODE Table 7). Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus 1 0 least significant byte most significant byte X X 004aaa807 [2] Interrupt types Normal ...
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... CC1 CC only [2] apply V to both the 3.0 CC2 V and VOUT3.3 pins [3] see Section 15 and 40 Section 16 per device Conditions Schmitt trigger pins I = rated drive Rev. 09 — 11 May 2006 PDIUSBD12 Min Max 0.5 +6 100 [1] 2000 +2000 60 +150 - 95 Typ Max - 5.5 - 3.6 - 5.5 - 5.5 - 3.6 - ...
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... GND steady state drive SoftConnect = and D . [1] ; unless otherwise specified. CC Conditions see Figure 16 see Figure 16 Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus Min Typ Max 2 0 ...
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... EOP; see Figure 16 must accept as EOP; see Figure 16 CROSSOVER POINT CROSSOVER POINT SEO/EOP SKEW PERIOD DEOP Conditions Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus Min Typ EXTENDED SOURCE EOP WIDTH: t RECEIVER EOP WIDTH: t ...
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... DATA[7:0] Fig 17. ALE timing PDIUSBD12_9 Product data sheet USB peripheral controller with parallel bus …continued Conditions th byte and the second last (EOT 1) byte AVLL LLAX ADDRESS Rev. 09 — 11 May 2006 PDIUSBD12 Min Typ Max Unit 600 - - ns [ [2] 130 - - ...
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... RD WDSU WDH VALID DATA RLDD RHDZ VALID DATA Conditions simultaneous DMACK_N, RD_N/WR_N and EOT_N LOW time Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus RHNDV VALID DATA t RLDD Min Typ - - 130 - 120 ...
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... RD_N/WR_N Fig 21. DMA terminated by EOT PDIUSBD12_9 Product data sheet t RHSH RHSH DMREQ DMACK_N EOT_N Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus t AHRH t SHAH t SLRL t SHAH t ELRL © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 004aaa810 004aaa811 ...
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... Fig 22. Load for D+ and D PDIUSBD12_9 Product data sheet USB peripheral controller with parallel bus Figure 22. 1 internal test point 22 DUT 15 k Rev. 09 — 11 May 2006 PDIUSBD12 Table 16 004aaa813 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... 0.49 0.32 18.1 7.6 10.65 1.27 0.36 0.23 17.7 7.4 10.00 0.019 0.013 0.71 0.30 0.419 0.05 0.014 0.009 0.69 0.29 0.394 REFERENCES JEDEC JEITA MS-013 Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus detail 1.1 1.1 1.4 0.25 0.25 0.4 1.0 0.043 0.043 0.055 ...
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... Product data sheet 2.5 scale (1) ( 0.30 0.2 9.8 4.5 0.65 0.19 0.1 9.6 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION © ...
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... PDIUSBD12_9 Product data sheet USB peripheral controller with parallel bus 2 called small/thin packages. Rev. 09 — 11 May 2006 PDIUSBD12 3 350 mm so called © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus Soldering method Wave not suitable [4] not suitable suitable [5][6] not recommended [7] not recommended not suitable © ...
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... Power-On Reset Philips Serial Interface Engine Random Access Memory Small Computer System Interface Serial Interface Engine Start-Of-Frame Universal Serial Bus Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Figure 3 “Example of a parallel interface to an 80C51 Buffer”: updated the second paragraph. values”: removed table note 2. Product data Product data Product data Rev. 09 — 11 May 2006 PDIUSBD12 Change notice Supersedes - PDIUSBD12-08 microcontroller”. - PDIUSBD12-07 - PDIUSBD12- © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GoodLink — trademark of Koninklijke Philips Electronics N.V. SoftConnect — trademark of Koninklijke Philips Electronics N.V. Rev. 09 — 11 May 2006 PDIUSBD12 USB peripheral controller with parallel bus © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Table 19. Suitability of surface mount IC packages for wave and reflow soldering methods . . . . . . . . . . . . .33 Table 20. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .34 Table 21. Revision history . . . . . . . . . . . . . . . . . . . . . . . .35 PDIUSBD12_9 Product data sheet USB peripheral controller with parallel bus Rev. 09 — 11 May 2006 PDIUSBD12 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Fig 21. DMA terminated by EOT . . . . . . . . . . . . . . . . . . .28 Fig 22. Load for D+ and .29 Fig 23. Package outline SOT136-1 (SO28 .30 Fig 24. Package outline SOT361-1 (TSSOP28 .31 PDIUSBD12_9 Product data sheet USB peripheral controller with parallel bus Rev. 09 — 11 May 2006 PDIUSBD12 continued >> © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. All rights reserved. Date of release: 11 May 2006 Document identifier: PDIUSBD12_9 ...