PM5363-BI PMC-Sierra Inc, PM5363-BI Datasheet
PM5363-BI
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PM5363-BI Summary of contents
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... PMC-1981421 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 DATASHEET RELEASED ISSUE 4: JULY 2000 PM5363 TUPP+622 ...
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... V changed from 2.5V DD2.5 ± 10% to 2.5V ± 0.2V. TUGEN Bit and TUGBYP Bit description changed. Device ID Revision Number, SOS Bit description and Boundary Scan ID changed. Update Data-sheet portion to preliminary. Update pin and register description. Document created. PM5363 TUPP+622 ...
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... FUNCTIONAL DESCRIPTION.............................................................88 10.1 INPUT BUS DEMULTIPLEXER ................................................89 10.2 OUTPUT BUS MULTIPLEXER..................................................90 10.3 TRIBUTARY PAYLOAD PROCESSOR (VTPP).........................91 10.3.1 CLOCK GENERATOR....................................................91 10.3.2 INCOMING TIMING GENERATOR.................................91 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 i ...
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... JTAG TEST ACCESS PORT ...................................................106 10.7 MICROPROCESSOR INTERFACE ........................................107 11 NORMAL MODE REGISTER DESCRIPTION ................................... 117 11.1 TOP LEVEL CONFIGURATION REGISTERS......................... 118 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 ii ...
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... FUNCTIONAL TIMING.......................................................................389 15 ABSOLUTE MAXIMUM RATINGS .....................................................408 16 D.C. CHARACTERISTICS .................................................................409 17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS .........................................................................412 18 TUPP+622 TIMING CHARACTERISTICS .........................................420 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 iii ...
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... TUPP+622 DATASHEET PMC-1981421 19 ORDERING AND THERMAL INFORMATION....................................431 20 MECHANICAL INFORMATION ..........................................................434 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 iv ...
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... REGISTER 10H: STP TRIBUTARY ALARM AIS CONTROL ........................150 REGISTER 11H: STP TRIBUTARY REMOTE DEFECT INDICATION CONTROL ....................................................................152 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 v ...
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... TO TUG2 #7, CONFIGURATION AND STATUS ...........................182 REGISTER 3FH, 5FH, 7FH: VTPP TUG2 #1 TO TUG2 #7, LOP INTERRUPT ........................................................................184 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 vi ...
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... ACCEPTED PATH SIGNAL LABEL ...................................................212 REGISTER 104H, 204H, 304H: RTOP, TU3 TUG2 #1, BIP-2/BIP-8 ERROR COUNT LSB.....................................................213 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 vii ...
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... REGISTER 10EH, 116H, 11EH, 126H, 12EH, 136H: REGISTER 20EH, 216H, 21EH, 226H, 22EH, 236H: REGISTER 30EH, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 viii ...
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... REGISTER 141H, 149H, 151H, 159H, 161H, 169H, 171H: REGISTER 241H, 249H, 251H, 259H, 261H, 269H, 271H: REGISTER 341H, 349H, 351H, 359H, 361H, 369H, 371H: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 ix ...
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... RTOP TUG2 #1 TO TUG2 #7, REI ERROR COUNT MSB......................................................................................251 REGISTER 178H, 278H, 378H: RTOP TUG2 #1 TO TUG2 #7, COPSL INTERRUPT .........................................................253 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 x ...
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... REGISTER 383H, 38BH, 393H, 39BH, 3A3H, 3ABH, 3B3H: RTOP TUG2 #1 TO TUG2 #7, ACCEPTED PATH SIGNAL LABEL..................................................................................267 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xi ...
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... TUG2 #7, RFI INTERRUPT ...............................................................276 REGISTER 1BDH, 2BDH, 3BDH: RTOP TUG2 #1 TO TUG2 #7, IN BAND ERROR REPORTING CONFIGURATION .............................................................................277 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xii ...
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... REGISTER 2C6H, 2CEH, 2D6H, 2DEH, 2E6H, 2EEH, 2F6H: REGISTER 3C6H, 3CEH, 3D6H, 3DEH, 3E6H, 3EEH, 3F6H: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xiii ...
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... TUG2 #2 TO TUG2 #7, CONFIGURATION AND STATUS.................300 REGISTER 408H-40EH, 448H-44EH, 488H-48EH: RTTB TUG2 #1 TO TUG2 #7, CONFIGURATION AND STATUS.................302 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xiv ...
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... REGISTER 42AH, 46AH, 4AAH: RTTB, INDIRECT ADDRESS SELECT .............................................................................................322 REGISTER 42BH, 46BH, 4ABH: RTTB, INDIRECT DATA SELECT ............324 REGISTER 2000H: MASTER TEST .............................................................329 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xv ...
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... TEST REGISTER 3804H: (WRITE IN I/O TEST MODE) ..............................350 TEST REGISTER 3805H: (WRITE IN I/O TEST MODE) ..............................351 TEST REGISTER 3806H: (WRITE IN I/O TEST MODE) ..............................352 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xvi ...
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... TEST REGISTER 3802H: (READ IN I/O TEST MODE) ...............................362 TEST REGISTER 3803H: (READ IN I/O TEST MODE) ...............................363 TEST REGISTER 3804H: (READ IN I/O TEST MODE) ...............................364 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xvii ...
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... FIGURE 15- SDH STM-1 CARRYING MIX OF TU11, TU12, TU3 WITHIN TUG3/AU4.......................................................................................381 FIGURE 16- BOUNDARY SCAN ARCHITECTURE.....................................383 FIGURE 17- TAP CONTROLLER FINITE STATE MACHINE .......................385 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xviii ...
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... FIGURE 31- MICROPROCESSOR INTERFACE READ ACCESS TIMING (MOTOROLA MODE)......................................................................414 FIGURE 32- MICROPROCESSOR INTERFACE WRITE ACCESS TIMING (INTEL MODE) ................................................................................417 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xix ...
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... FIGURE 38- THETA JA VS. AIRFLOW PLOT ..............................................432 FIGURE 39- MECHANICAL DRAWING 304 PIN SUPER BALL GRID ARRAY (SBGA)...................................................................................434 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xx ...
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... TABLE 17 - THERMAL INFORMATION – THETA JC..................................431 TABLE 18 - MAXIMUM JUNCTION TEMPERATURE.................................431 TABLE 19 - THERMAL INFORMATION – THETA JA VS. AIRFLOW 432 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 xxi ...
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... Each TUG3 can also be configured to carry a single TU3. • Independently configurable for AU3 or AU4 frame format on incoming and outgoing interfaces. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 1 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 2 ...
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... Supports in-band error reporting by updating the REI, RDI and auxiliary RDI bits in the V5 byte (G1 in TU3) with the status of the incoming stream. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 3 ...
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... Low power, +2.5 Volt, CMOS technology, +3.3 Volt TTL compatible inputs and outputs (5V tolerant). • 304 pin Super BGA package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 4 ...
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... TUPP+622 DATASHEET PMC-1981421 2 APPLICATIONS • SONET/SDH Digital Cross-Connect • SONET/SDH Add-Drop Multiplexer PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 5 ...
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... Bell Communications Research - SONET Dual-Fed Unidirectional Path Switched Ring (UPSR) Equipment Generic Criteria, GR-1400-CORE, Issue 2, January 1999. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 6 ...
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... January 1996. 14. PMC-981215 “PM669 (0.25um RAM test chip) and P25 (Galax! I/O test chip) Rev. A Characterization Report”. Issue 1. February 9, 1999. 15. PMC-1991211 “PM5363-BI Rev. A (TUPP+622) Characterization Report”. Issue 1. March 27, 2000. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ...
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... VTPP Tributary Payload Processor RTOP Tributary Overhead Processor RTTB Tributary Trace Buffer STP STM-1 (STS-3) Tributary Processor PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 8 ...
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... STS-12 (STM-4) AGGREGATE INTERFACE Figure 1 shows how the TUPP+622 is used to implement a single 77.76 MHz STS-12 (STM-4) aggregate interface. In this application, the PM5313 SPECTRA- 622 performs SONET/SDH section, line and path termination and the PM5363 TUPP+622 performs tributary pointer processing and performance monitoring. Figure 1 ...
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... STS-3 (STM-1) aggregate interface using four 19.44 MHz Telecom buses on the system side interface. In this application, the PM5342 SPECTRA-155's perform SONET/SDH section, line and path termination and the PM5363 TUPP+622 performs tributary pointer processing and performance monitoring. Figure 2 - Quad STS-3 (STM-1) Aggregate Interface with Tributary ...
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... DATASHEET PMC-1981421 5.3 STS-48 (STM-16) AGGREGATE INTERFACE Four PM5363 TUPP+622 devices can be connected to four PM5313 SPECTRA- 622 devices and an OC-48 front end transceiver device to implement an STS-48 (STM-16) aggregate interface. Figure 3 shows a block diagram for the STS-48 (STM-16) application. In this application, the OC-48 transceiver performs ...
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... DATASHEET PMC-1981421 5.4 TUPP-PLUS Compatibility and TUPP+622 Feature Enhancements The TUPP+622 (PM5363) supports software configuration of the payload frame alignment in the outgoing data stream. The high order path active offset may be set to any alignment on a per-STM-1 (STS-3) basis. For example, by setting the outgoing stream active offset contained in the STP Outgoing Pointer MSB and ...
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... DATASHEET PMC-1981421 6 DESCRIPTION The PM5363 TUPP+622 SONET/SDH Tributary Unit Payload Processor For 622 Mbit/s Interfaces is a monolithic integrated circuit that implements a configurable, multi-channel, payload processor that aligns and monitors performance of SONET virtual tributaries (VTs) or SDH tributary units (TUs.). When configured for SONET compatible operation, the TUPP+622 transfers all ...
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... The TUPP+622 is implemented in low power, +2.5 Volt Core and +3.3 Volt I/O, CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 304 pin SBGA package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 14 ...
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... ID[18] IC1J1[3] COUT[4] AIS[4] OD[31] OD[27] OD[24] OTMF[4] OC1J1V1 IPL[3] VDDI8 IDLE[4] OTPL[4] OD[30] VDDI7 OD[25] [4] VSS TPOH[4] VSS ODP[4] OD[29] OD[26] VSS OPL[ PM5363 TUPP+622 A[11] A[8] VSS A[3] VSS ALE CSB TDO A[10] A[6] A[4] A[1] RDB VDDI16 TDI VSS A[9] A[5] A[2] WRB MBEB TCK TMS VDD OC1J1V1 ...
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... Processor Trib uta Tra ce Buffer (R TTB ) - PM5363 TUPP+622 [ [31 : ...
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... SCLK. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), ODP[4:1], OTPL[4:1], OTV5[4:1], OD[31:0], AIS[4:1], IDLE[4:1], TPOH[4:1], OC1J1V1[4:1] and OPL[4:1] are updated on the rising edge of SCLK. The test vector clock (VCLK) signal is used during TUPP+622 production testing to verify manufacture. PM5363 TUPP+622 17 ...
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... HSCLK, and ODP[1], OTPL[1], OTV5[1], OD[7:0], AIS[1], IDLE[1], TPOH[1], OC1J1V1[1] and OPL[1] are updated on the rising edge of HSCLK. When the incoming and the outgoing interfaces are in STM-1 mode (IHSMODEB and OHSMODEB both set high), HSCLK may be left unconnected. HSCLK has an integral pull-up resistor. PM5363 TUPP+622 18 ...
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... HSCLK. When OHSMODEB is set high, the 19.44 MHz STM-1 (STS-3) interface mode is selected. OTMF[4:1] are sampled on the rising edge of SCLK. ODP[4:1], OTPL[4:1], OTV5[4:1], OD[31:0], AIS[4:1], IDLE[4:1], OC1J1V1[4:1] and OPL[4:1] are updated on the rising edge of SCLK. OHSMODEB has an integral pull-up resistor. PM5363 TUPP+622 19 ...
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... HSCLK. GSCLK[0] must only be connected to SCLK externally when IHSMODEB or OHSMODEB is set low. GSCLK[ exact replica of GSCLK[0] and can be used to supply timing to external devices that are operating in the 19.44 MHz STM-1 (STS-3) interface timing domain. GSCLK[1:0] are updated on the rising edge of HSCLK. PM5363 TUPP+622 20 ...
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... C1 and all J1 bytes. The TUPP+622 will ignore a pulse on IC1J1[1] at the byte position of the V1 byte of the first tributary of each VC3 or the top byte of the first fixed stuff column of each TUG3. IC1J1[1] is sampled on the rising edge of HSCLK. PM5363 TUPP+622 21 ...
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... IC1J1[2] at the byte position of the V1 byte of the first tributary of each VC3 or the top byte of the first fixed stuff column of each TUG3. IC1J1[2] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IC1J1[2] is unused and must be strapped low. PM5363 TUPP+622 22 ...
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... IC1J1[3] at the byte position of the V1 byte of the first tributary of each VC3 or the top byte of the first fixed stuff column of each TUG3. IC1J1[3] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IC1J1[3] is unused and must be strapped low. PM5363 TUPP+622 23 ...
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... IC1J1[4] at the byte position of the V1 byte of the first tributary of each VC3 or the top byte of the first fixed stuff column of each TUG3. IC1J1[4] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IC1J1[4] is unused and must be strapped low. PM5363 TUPP+622 24 ...
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... STS-1 synchronous payload envelopes. In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IPL[2] must be brought high to mark each payload byte on ID[15:8]. IPL[2] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IPL[2] is unused and must be strapped low. PM5363 TUPP+622 25 ...
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... STS-1 synchronous payload envelopes. In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), IPL[4] must be brought high to mark each payload byte on ID[31:24]. IPL[4] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IPL[4] is unused and must be strapped low. PM5363 TUPP+622 26 ...
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... ITMF[1] must be low for the and 3 frame of the tributary multiframe. In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITMF[1] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITMF[1] is sampled on the rising edge of HSCLK. PM5363 TUPP+622 th frame of the tributary 27 ...
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... ITMF[2] must be low for the 1 rd and 3 frame of the tributary multiframe. In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITMF[2] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITMF[2] is unused and must be strapped low. PM5363 TUPP+622 ...
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... ITMF[3] must be low for the 1 rd and 3 frame of the tributary multiframe. In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITMF[3] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITMF[3] is unused and must be strapped low. PM5363 TUPP+622 ...
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... ITMF[4] must be low for the 1 rd and 3 frame of the tributary multiframe. In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITMF[4] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITMF[4] is unused and must be strapped low. PM5363 TUPP+622 ...
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... Also, ITPL[2] is ignored when IPL[2] is low. In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITPL[2] is set high to mark each tributary payload byte on the ID[15:8] bus. ITPL[2] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITPL[2] is unused and must be strapped low. PM5363 TUPP+622 31 ...
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... Also, ITPL[4] is ignored when IPL[4] is low. In incoming STM-1 (STS-3) interface mode (IHSMODEB set high), ITPL[4] is set high to mark each tributary payload byte on the ID[31:24] bus. ITPL[4] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITPL[4] is unused and must be strapped low. PM5363 TUPP+622 32 ...
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... SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITV5[1] is set high to mark each tributary V5 byte of the STM-4 stream on the ID[7:0] bus. When the incoming tributary is a TU3, ITV5[1] marks the J1 byte of the TU3. ITV5[1] is sampled on the rising edge of HSCLK. PM5363 TUPP+622 33 ...
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... ITV5[3] is set high to mark each tributary V5 byte on the ID[23:16] bus. When the incoming tributary is a TU3, ITV5[3] marks the J1 byte of the TU3. ITV5[3] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITV5[3] is unused and must be strapped low. PM5363 TUPP+622 34 ...
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... ITV5[4] is set high to mark each tributary V5 byte on the ID[31:24] bus. When the incoming tributary is a TU3, ITV5[4] marks the J1 byte of the TU3. ITV5[4] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), ITV5[4] is unused and must be strapped low. PM5363 TUPP+622 35 ...
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... IAIS[1] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IAIS[1] is set high when the associated tributary of the STM-4 stream on the ID[7: AIS state and is set low when the associated tributary is operating normally. IAIS[1] is sampled on the rising edge of HSCLK. PM5363 TUPP+622 36 ...
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... IAIS[3] is set high when the associated tributary on the ID[23:16 AIS state and is set low when the associated tributary is operating normally. IAIS[3] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IAIS[3] is unused and must be strapped low. PM5363 TUPP+622 37 ...
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... IAIS[4] is set high when the associated tributary on the ID[31:24 AIS state and is set low when the associated tributary is operating normally. IAIS[4] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IAIS[4] is unused and must be strapped low. PM5363 TUPP+622 38 ...
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... IPL[1] can be included in the parity calculation by setting the corresponding INCIC1J1 and INCIPL register bits high, respectively. Odd parity is selected by setting the corresponding IOP register bit high, and even parity is selected by setting the IOP bit low. IDP[1] is sampled on the rising edge of HSCLK. PM5363 TUPP+622 39 ...
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... INCIPL register bits high, respectively. Odd parity is selected by setting the corresponding IOP register bit high, and even parity is selected by setting the IOP bit low. IDP[3] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IDP[3] is unused and must be strapped low. PM5363 TUPP+622 40 ...
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... INCIPL register bits high, respectively. Odd parity is selected by setting the corresponding IOP register bit high, and even parity is selected by setting the IOP bit low. IDP[4] is sampled on the rising edge of SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), IDP[4] is unused and must be strapped low. PM5363 TUPP+622 41 ...
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... The C17 ID[15:8] bus is sampled on the rising edge of B18 SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), the ID[15:8] bus is unused and all bus signals must be strapped low. PM5363 TUPP+622 42 ...
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... The AC4 ID[31:24] bus is sampled on the rising edge of AB5 SCLK. In incoming STM-4 (STS-12) interface mode (IHSMODEB set low), the ID[31:24] bus is unused and all bus signals must be strapped low. PM5363 TUPP+622 43 ...
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... Pulses on OTMF[1] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[1] is ignored at other byte positions. OTMF[1] is sampled on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OTMF[1] identifies PM5363 TUPP+622 44 ...
Page 68
... Selection between marking the third byte after each bytes is controlled by the corresponding OTMFH4 register bit. Pulses on OTMF[1] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[1] is ignored at other byte positions. OTMF[1] is sampled on the rising edge of HSCLK. PM5363 TUPP+622 45 ...
Page 69
... Pulses on OTMF[2] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[2] is ignored at other byte positions. OTMF[2] is sampled on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OTMF[2] is unused and must be strapped low. PM5363 TUPP+622 46 ...
Page 70
... Pulses on OTMF[3] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[3] is ignored at other byte positions. OTMF[3] is sampled on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OTMF[3] is unused and must be strapped low. PM5363 TUPP+622 47 ...
Page 71
... Pulses on OTMF[4] are only effective during the H4 or third byte after each J1 byte positions, as appropriate. OTMF[4] is ignored at other byte positions. OTMF[4] is sampled on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OTMF[4] is unused and must be strapped low. PM5363 TUPP+622 48 ...
Page 72
... COUTx register bit associated with each tributary in the STM-1 #3 stream. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), COUT[3] is synchronized to the OD[23:16] bus. COUT[3] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), COUT[3] is invalid. PM5363 TUPP+622 49 ...
Page 73
... COUTx register bit associated with each tributary in the STM-1 #4 stream. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), COUT[4] is synchronized to the OD[31:24] bus. COUT[4] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), COUT[4] is invalid. PM5363 TUPP+622 50 ...
Page 74
... OD[7:0] is set to all-zeros at transport overhead bytes, except for the A1 and A2 framing bytes and the H1 and H2 pointer bytes. Pointer offset is determined by the STP Outgoing Pointer MSB and LSB registers. The OD[7:0] bus is updated on the rising edge of HSCLK. PM5363 TUPP+622 51 ...
Page 75
... H1 and H2 pointer bytes. Pointer offset is determined by the STP Outgoing Pointer MSB and LSB registers. The OD[15:8] bus is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OD[15:8] bus is unused and all bus signals are invalid. PM5363 TUPP+622 52 ...
Page 76
... H1 and H2 pointer bytes. Pointer offset is determined by the STP Outgoing Pointer MSB and LSB registers. The OD[23:16] bus is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OD[23:16] bus is unused and all bus signals are invalid. PM5363 TUPP+622 53 ...
Page 77
... H1 and H2 pointer bytes. Pointer offset is determined by the STP Outgoing Pointer MSB and LSB registers. The OD[31:24] bus is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), the OD[31:24] bus is unused and all bus signals are invalid. PM5363 TUPP+622 54 ...
Page 78
... Odd parity is selected by setting the corresponding OOP register bit high, and even parity is selected by setting the OOP bit low. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), ODP[2] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), ODP[2] is invalid. PM5363 TUPP+622 55 ...
Page 79
... Odd parity is selected by setting the corresponding OOP register bit high, and even parity is selected by setting the OOP bit low. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), ODP[4] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), ODP[4] is invalid. PM5363 TUPP+622 56 ...
Page 80
... STM-1 #2 stream. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTPL[2] is set high to mark each tributary payload byte on the OD[15:8] bus. OTPL[2] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTPL[2] is invalid. PM5363 TUPP+622 57 ...
Page 81
... STM-1 #4 stream. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OTPL[4] is set high to mark each tributary payload byte on the OD[31:24] bus. OTPL[4] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTPL[4] is invalid. PM5363 TUPP+622 58 ...
Page 82
... OTV5[2] is set high to mark each tributary V5 byte on the OD[15:8] bus. When the outgoing tributary is a TU3, OTV5[2] marks the J1 byte of the TU3. OTV5[2] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTV5[2] is invalid. PM5363 TUPP+622 59 ...
Page 83
... OTV5[4] is set high to mark each tributary V5 byte on the OD[31:24] bus. When the outgoing tributary is a TU3, OTV5[4] marks the J1 byte of the TU3. OTV5[4] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OTV5[4] is invalid. PM5363 TUPP+622 60 ...
Page 84
... In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), AIS[2] is set high when AIS is inserted in the associated tributary on the OD[15:8] and is set low when the AIS is not inserted. AIS[2] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), AIS[2] is invalid. PM5363 TUPP+622 61 ...
Page 85
... In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), AIS[4] is set high when AIS is inserted in the associated tributary on the OD[31:24] and is set low when the AIS is not inserted. AIS[4] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), AIS[4] is invalid. PM5363 TUPP+622 62 ...
Page 86
... IDLE[2] is set high when idle code is inserted in the associated tributary on the OD[15:8] and is set low when the idle code is not inserted. IDLE[2] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), IDLE[2] is invalid. PM5363 TUPP+622 63 ...
Page 87
... IDLE[4] is set high when idle code is inserted in the associated tributary on the OD[31:24] and is set low when the idle code is not inserted. IDLE[4] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), IDLE[4] is invalid. PM5363 TUPP+622 64 ...
Page 88
... bytes are marked. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), TPOH[2] is set high to mark each tributary path overhead byte on the OD[15:8] bus. TPOH[2] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), TPOH[2] is invalid. PM5363 TUPP+622 65 ...
Page 89
... bytes are marked. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), TPOH[4] is set high to mark each tributary path overhead byte on the OD[31:24] bus. TPOH[4] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), TPOH[4] is invalid. PM5363 TUPP+622 66 ...
Page 90
... TUGBYP set low), the AU3/AU4 pointer offset (J1 position relative to C1) of each STM-1 is determined by the corresponding STP Outgoing Pointer MSB and LSB registers. Optionally, OC1J1V1[1] also marks the third byte after J1 of the first tributary in each STS-1 (TUG3) stream when the corresponding OV1EN PM5363 TUPP+622 67 ...
Page 91
... OV1EN register bit is set high. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), the J1 and V1 byte position pulses are delayed versions from the IC1J1[2] input. OC1J1V1[2] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OC1J1V1[2] is invalid. PM5363 TUPP+622 68 ...
Page 92
... OV1EN register bit is set high. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), the J1 and V1 byte position pulses are delayed versions from the IC1J1[3] input. OC1J1V1[3] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OC1J1V1[3] is invalid. PM5363 TUPP+622 69 ...
Page 93
... OV1EN register bit is set high. When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), the J1 and V1 byte position pulses are delayed versions from the IC1J1[4] input. OC1J1V1[4] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OC1J1V1[4] is invalid. PM5363 TUPP+622 70 ...
Page 94
... When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), OPL[ delayed version of IPL[2]. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OPL[2] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OPL[2] is invalid. PM5363 TUPP+622 71 ...
Page 95
... When AU3/TUG3 bypass is enabled (TUGEN set low or TUGBYP set high), OPL[ delayed version of IPL[4]. In outgoing STM-1 (STS-3) interface mode (OHSMODEB set high), OPL[4] is updated on the rising edge of SCLK. In outgoing STM-4 (STS-12) interface mode (OHSMODEB set low), OPL[4] is invalid. PM5363 TUPP+622 72 ...
Page 96
... All four tributary overhead bytes of each tributary is shifted out once per payload frame. The corresponding POHEN signal is set high to identify overhead bytes that are presented for the first time. Each POH signal is updated on the falling edge of POHCK. PM5363 TUPP+622 73 ...
Page 97
... All four tributary overhead bytes of each tributary is shifted out once per payload frame. The corresponding POHEN signal is set high to identify overhead bytes that are presented for the first time. Each POH signal is updated on the falling edge of POHCK. PM5363 TUPP+622 74 ...
Page 98
... V5 byte of the first tributary. POHFP[1], POHFP[2] and POHFP[3] identify frame boundaries of the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POHFP[1], POHFP[2] and POHFP[3] identify frame boundaries of TUG3 #1, #2 and #3, respectively. Each POHFP signal is updated on the falling edge of POHCK. PM5363 TUPP+622 75 ...
Page 99
... V5 byte of the first tributary. POHFP[7], POHFP[8] and POHFP[9] identify frame boundaries of the tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POHFP[7], POHFP[8] and POHFP[9] identify frame boundaries of TUG3 #1, #2 and #3, respectively. Each POHFP signal is updated on the falling edge of POHCK. PM5363 TUPP+622 76 ...
Page 100
... POHEN[3] identify the status of tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POHEN[1], POHEN[2] and POHEN[3] identify the status of tributary path overhead bytes from TUG3 #1, #2 and #3, respectively. Each POHEN signal is updated on the falling edge of POHCK. PM5363 TUPP+622 77 ...
Page 101
... POHEN[9] identify the status of tributary path overhead bytes from STS-1 (AU3) #1, #2 and #3, respectively. In AU4 mode, POHEN[7], POHEN[8] and POHEN[9] identify the status of tributary path overhead bytes from TUG3 #1, #2 and #3, respectively. Each POHEN signal is updated on the falling edge of POHCK. PM5363 TUPP+622 78 ...
Page 102
... PDI status of each tributary in the STM- 1 #2. RAD[2] is updated on the falling edge of POHCK. T20 The receive alarm port #3 (RAD[3]) contains the tributary path BIP error count, the RDI status and the PDI status of each tributary in the STM- 1 #3. RAD[3] is updated on the falling edge of POHCK. PM5363 TUPP+622 79 ...
Page 103
... TUPP+622 register read accesses while in Intel bus mode. The TUPP+622 drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. The active high external access (E) signal is high during TUPP+622 register access while in Motorola bus mode. PM5363 TUPP+622 80 ...
Page 104
... RWB and E are high. The D[7:0] bus contents are clocked into the addressed register on the falling E edge while CSB and RWB are low. A11 The bidirectional data bus D[7:0] is used during TUPP+622 register read and write accesses. B12 C12 A13 B13 C13 D13 A14 PM5363 TUPP+622 81 ...
Page 105
... Schmitt triggered input with an integral pull up resistor. A5 The address latch enable (ALE) is active high and latches the address bus A[13:0] when low. When ALE is high, the internal address latches are transparent. It allows the TUPP+622 to interface to a multiplexed address/data bus. ALE has an integral pull up resistor. PM5363 TUPP+622 82 ...
Page 106
... TCK. TDO is a tristate output that is always tristated except when scanning of data is in progress. D5 The active low test reset (TRSTB) signal provides an asynchronous test access port reset. TRSTB is a Schmitt triggered input with an integral pull up resistor. TRSTB must be asserted during the power up sequence. PM5363 TUPP+622 83 ...
Page 107
... ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Pin Function No. G2 The core power (VDDI1 – VDDI16) pins should be connected to a well decoupled +2 supply AB7 AB10 AB13 AB17 U22 N22 J22 E22 B17 B14 B11 B5 PM5363 TUPP+622 84 ...
Page 108
... Function No. A1 The pad ring switching power (VDD[35:0]) pins A23 should be connected to a well decoupled +3.3 V AA3 DC supply. AA21 AB2 AB22 AC1 AC23 B2 B22 C3 C21 D12 D15 D18 D20 F4 F20 J4 J20 M4 M20 R4 R20 V4 V20 Y12 Y15 Y18 Y20 PM5363 TUPP+622 85 ...
Page 109
... VDD[35:0] and the VDDI1 – A16 VDDI16 power pins. A18 A22 AA2 AA22 AB1 AB3 AB21 AB23 AC2 AC6 AC8 AC12 AC16 AC18 AC22 B1 B3 B21 B23 C2 C22 F1 F23 H1 H23 M1 M23 T1 T23 V1 V23 Y7 Reserved. Must not be connected. PM5363 TUPP+622 86 ...
Page 110
... Hold the device in the reset condition until the device power supplies are within their nominal voltage range. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Pin Function No. Y16 Reserved. Must not be connected. PM5363 TUPP+622 87 ...
Page 111
... Input Bus Demultiplexer. Consolidation of outgoing STM-1 streams from the STP’s is performed by the Output Bus Multiplexer. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 88 ...
Page 112
... STP. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Order of T ransm ission Tw elveth Byte 4,3 3,3 2,3 1,3 4,2 Byte Interleaving to generate ST M-4 (STS-12) stream PM5363 TUPP+622 First Byte 3,2 2,2 1,2 4,1 3,1 2,1 1,1 STM-4 (ST S-12) 89 ...
Page 113
... OC1J1V1 and OPL outputs. This timing drives the outputs of the three VTPPs, RTOPs and RTTBs within the STP. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 90 ...
Page 114
... The identification of specific tributaries allows the pointer interpreter to be time-sliced across the mix of tributaries present in the incoming data PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 91 ...
Page 115
... TUG3 or STS-1 (AU3) stream. The algorithm can be modeled by a finite state machine. Within the pointer interpretation algorithm three states are defined (as shown in Figure 5): NORM_state (NORM) AIS_state (AIS) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 92 ...
Page 116
... Figure 5 - Pointer Interpretation State Diagram inc_ind / dec_ind LOP PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES 3 x eq_new_point NDF_enable NORM 3 x AIS_ind 8 x inv_point PM5363 TUPP+622 AIS 93 ...
Page 117
... Disabled NDF is defined as the following bit patterns: 0110, 1110, 0010, 0100, 0111. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 94 ...
Page 118
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES three consecutive equal new_point indications single NDF_enable indication three consecutive AIS indications eight consecutive inv_point indications PM5363 TUPP+622 95 ...
Page 119
... The identification of specific tributaries allows the pointer generator to be time-sliced across the mix of tributaries to be sourced PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 96 ...
Page 120
... The transitions from INC, DEC, and NDF states to the NORM state occur autonomously with the generation of special pointer patterns. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 97 ...
Page 121
... AIS_ind The following events, indicated in the state diagram (Figure 6), are defined: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PI_AIS NORM PI_NORM PI_AIS PM5363 TUPP+622 DEC NDF 98 ...
Page 122
... AIS_ind: active offset is undefined, transmit an all-1's pointer and payload. Notes: 1. Active offset is defined as the phase of the SPE (VC). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 99 ...
Page 123
... TUG3. The number of tributaries managed by each RTOP ranges from 1 (when configured to process a single TU3 (when configured to process all VT1.5s or all TU11s). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 100 ...
Page 124
... BIP-2 errors may be accumulated on a block or nibble basis as controlled by software configurable registers. Remote PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 101 ...
Page 125
... INTERFACES Accepted PSL 000 001 PDI Code XXX ≠ 000, 001, PDI Code 000 001 PDI Code XXX ≠ 000, 001, PDI Code 000 001 PM5363 TUPP+622 PSLM State UNEQ State Match Inactive Mismatch Inactive Mismatch Inactive Mismatch Inactive Mismatch Active ...
Page 126
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Accepted PSL PDI Code XXX ≠ 000, 001, PDI Code 000 001 XXX YYY PM5363 TUPP+622 PSLM State UNEQ State Match Inactive Mismatch Inactive Mismatch Active Match Inactive ...
Page 127
... The clock generator derives various clocks from the 19.44 MHz system clock and distributes them to other blocks within the tributary trace buffer. The overall PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 104 ...
Page 128
... If the accepted message differs from the expected message, the trail trace identifier mismatch (TIM) alarm is raised. TIM alarm is negated if the accepted PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 105 ...
Page 129
... The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 106 ...
Page 130
... STP Input Signal Activity Monitor #1, Accumulation Trigger 1803 STP Reset and Identity 1804 STP VTPP #1 Configuration #1 1805 STP VTPP #2 Configuration #1 1806 STP VTPP #3 Configuration #1 1807 STP Tributary Payload Processor and LOM Interrupt Enable 1808 STP Tributary Payload Processor Interrupt and LOM Status PM5363 TUPP+622 Description 107 ...
Page 131
... VTPP # TUG2 #3, Configuration and Status 1823 VTPP # TUG2 #4, Configuration and Status 1824 VTPP # TUG2 #5, Configuration and Status 1825 VTPP # TUG2 #6, Configuration and Status 1826 VTPP # TUG2 #7, Configuration and Status PM5363 TUPP+622 Description 108 ...
Page 132
... VTPP # TUG2 #5, Alarm Status 18A5 VTPP # TUG2 #6, Alarm Status 18A6 VTPP # TUG2 #7, Alarm Status 18A7 VTPP #1, TU3 TUG2 #1 to TUG2 #7, AIS Interrupt 18A8- VTPP # TUG2 #1 to TUG2 #7, Alarm 18AE Status PM5363 TUPP+622 Description 109 ...
Page 133
... RTOP #1, TU3 TUG2 #1, REI Count LSB 1907 RTOP #1, TU3 TUG2 #1, REI Count MSB 1908- RTOP # TUG2 #2, Configuration and 190F Status Registers 1910- RTOP # TUG2 #3, Configuration and 1917 Status Registers PM5363 TUPP+622 Description 110 ...
Page 134
... RTOP # TUG2 #1, Configuration and 1947 Status Registers 1948- RTOP # TUG2 #2, Configuration and 194F Status Registers 1950- RTOP # TUG2 #3, Configuration and 1957 Status Registers 1958- RTOP # TUG2 #4, Configuration and 195F Status Registers PM5363 TUPP+622 Description 111 ...
Page 135
... RTOP # TUG2 #2, Configuration and 198F Status Registers 1990- RTOP # TUG2 #3, Configuration and 1997 Status Registers 1998- RTOP # TUG2 #4, Configuration and 199F Status Registers 19A0- RTOP # TUG2 #5, Configuration and 19A7 Status Registers PM5363 TUPP+622 Description 112 ...
Page 136
... RTOP # TUG2 #3, Configuration and 19D7 Status Registers 19D8- RTOP # TUG2 #4, Configuration and 19DF Status Registers 19E0- RTOP # TUG2 #5, Configuration and 19E7 Status Registers 19E8- RTOP # TUG2 #6, Configuration and 19EF Status Registers PM5363 TUPP+622 Description 113 ...
Page 137
... RTTB # TUG2 #3 Configuration and Status 1C03 RTTB # TUG2 #4 Configuration and Status 1C04 RTTB # TUG2 #5 Configuration and Status 1C05 RTTB # TUG2 #6 Configuration and Status 1C06 RTTB # TUG2 #7 Configuration and Status PM5363 TUPP+622 Description 114 ...
Page 138
... RTTB # TUG2 #1 to TUG2 #7, TIU Interrupt 1C27 RTTB # TUG2 #1 to TUG2 #7, TIU Interrupt 1C28 RTTB #1, TIU Threshold 1C29 RTTB #1, Indirect Tributary Select 1C2A RTTB #1, Indirect Buffer Address 1C2B RTTB #1, Indirect Data 1C40- RTTB #2 Registers 1C7F PM5363 TUPP+622 Description 115 ...
Page 139
... All register numbers and addresses shown are in hexadecimal. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES STP #4 1C80- RTTB #3 Registers 1CBF Master Test Reserved for Test PM5363 TUPP+622 Description 116 ...
Page 140
... Writing to reserved registers should be avoided. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 117 ...
Page 141
... AU3/4 or STS-1 frame is the first frame of the tributary PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default IPE 0 LOPAIS 0 INCIPL 0 INCIC1J1 0 IOP 0 ITMFH4 0 ITMFEN 0 ICONCAT 0 PM5363 TUPP+622 118 ...
Page 142
... When IPE is set low, incoming parity errors will not cause an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 119 ...
Page 143
... ODP is even. When OOP is set high, the parity is odd. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default INCOPL 0 INCOC1J1 0 POHPT 0 OV1EN 0 OOP 0 OTMFH4 0 Reserved 0 OCONCAT 0 PM5363 TUPP+622 120 ...
Page 144
... OPL output. When INCOPL is set low, parity is calculated without regard to the state of OPL. Selection of odd or even parity is controlled by the OOP bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 121 ...
Page 145
... SCLKA is set high on a rising edge of SCLK, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default OTMFA X Unused X GSCLK_FPA X IDA X ITMFA X IPLA X IC1J1A X SCLKA X PM5363 TUPP+622 122 ...
Page 146
... OTMF input. OTMFA is set high on a rising edge of OTMF, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 123 ...
Page 147
... Otherwise the effect of a software reset is equivalent to that of a hardware reset for the STP. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default RESET 0 TYPE 1 ID[5] 0 ID[4] 0 ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 PM5363 TUPP+622 124 ...
Page 148
... TU3 bit. In TU3 mode, registers PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default TUGEN 0 SOS 0 MONIS 0 Reserved 0 NOFILT 0 TU3 0 ITUG3 0 OTUG3 0 PM5363 TUPP+622 125 ...
Page 149
... This bit does not apply to set new pointer events (i.e. NDF’s). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 126 ...
Page 150
... Telecom Bus signals, IC1J1 and IPL, to the output Telecom Bus is terminated gracefully. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 127 ...
Page 151
... TU3 bit. In TU3 mode, registers PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default TUGEN 0 SOS 0 MONIS 0 Reserved 0 NOFILT 0 TU3 0 ITUG3 0 OTUG3 0 PM5363 TUPP+622 128 ...
Page 152
... This bit does not apply to set new pointer events (i.e. NDF’s). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 129 ...
Page 153
... Telecom Bus signals, IC1J1 and IPL, to the output Telecom Bus is terminated gracefully. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 130 ...
Page 154
... TU3 bit. In TU3 mode, registers PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default TUGEN 0 SOS 0 MONIS 0 Reserved 0 NOFILT 0 TU3 0 ITUG3 0 OTUG3 0 PM5363 TUPP+622 131 ...
Page 155
... This bit does not apply to set new pointer events (i.e. NDF’s). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 132 ...
Page 156
... Telecom Bus signals, IC1J1 and IPL, to the output Telecom Bus is terminated gracefully. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 133 ...
Page 157
... VTPP3I bit, although the interrupt output will not be PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default Unused X Unused X LOM3E 0 LOM2E 0 LOM1E 0 VTPP3E 0 VTPP2E 0 VTPP1E 0 PM5363 TUPP+622 134 ...
Page 158
... When ICONCAT is set to logic 1 this interrupt enable bit should be set to logic 0. In the AU4 mode the multiframe alignment is determined by the H4 byte framer in tributary payload processor #1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 135 ...
Page 159
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default Unused X Unused X LOM3V 0 LOM2V 0 LOM1V 0 VTPP3I 0 VTPP2I 0 VTPP1I 0 PM5363 TUPP+622 136 ...
Page 160
... ICONCAT is set to logic 1 this status bit should be ignored since the multiframe alignment is determined by the H4 byte framer in tributary payload processor #1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 137 ...
Page 161
... LOM2I bit is set high on entry and exit to the loss of multiframe state and is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default IPI 0 Unused X LOM3I 0 LOM2I 0 LOM1I 0 Reserved3 1 Reserved2 1 Reserved1 1 PM5363 TUPP+622 138 ...
Page 162
... When this register is read, IPI (and the corresponding interrupt) is cleared. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 139 ...
Page 163
... RTOP3E will still be reported by the RTOP3I bit, although the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default Unused X Unused X RTTB3E 0 RTTB2E 0 RTTB1E 0 RTOP3E 0 RTOP2E 0 RTOP1E 0 PM5363 TUPP+622 140 ...
Page 164
... RTTB3I bit, although the interrupt output will not be activated. Interrupts disabled at tributary trace buffer #3 will not be reported by the RTTB3I bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 141 ...
Page 165
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default Unused X Unused X RTTB3I 0 RTTB2I 0 RTTB1I 0 RTOP3I 0 RTOP2I 0 RTOP1I 0 PM5363 TUPP+622 142 ...
Page 166
... Interrupts disabled at tributary trace buffer #3 will not be reported by the RTTB3I bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 143 ...
Page 167
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default ALGO2 0 PER5 0 Unused X Unused X RDI10 0 PDI[2] 0 PDI[1] 0 PDI[0] 1 PM5363 TUPP+622 144 ...
Page 168
... TIU is declared when the count exceeds the programmable TIU threshold. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 145 ...
Page 169
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default ALGO2 0 PER5 0 Unused X Unused X RDI10 0 PDI[2] 0 PDI[1] 0 PDI[0] 1 PM5363 TUPP+622 146 ...
Page 170
... TIU is declared when the count exceeds the programmable TIU threshold. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 147 ...
Page 171
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default ALGO2 0 PER5 0 Unused X Unused X RDI10 0 PDI[2] 0 PDI[1] 0 PDI[0] 1 PM5363 TUPP+622 148 ...
Page 172
... TIU is declared when the count exceeds the programmable TIU threshold. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 149 ...
Page 173
... When PSLUAIS is set PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default LOMAIS 0 LOPAIS 0 Unused X UNEQAIS 0 PSLMAIS 0 PSLUAIS 0 TIMAIS 0 TIUAIS 0 PM5363 TUPP+622 150 ...
Page 174
... When LOMAIS is set low, the generation of AIS on the outgoing data stream is inhibited. LOMAIS has no effect on TU3 streams. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 151 ...
Page 175
... RDI is reported on RAD and optionally in the V5 byte (G1 byte in PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default LOMRDI 0 LOPRDI 0 AISRDI 0 UNEQRDI 0 PSLMRDI 0 PSLURDI 0 TIMRDI 0 TIURDI 0 PM5363 TUPP+622 152 ...
Page 176
... When LOMRDI is set low, reporting of RDI due to LOM is inhibited. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 153 ...
Page 177
... PSLUARDI is set high, ARDI is reported on RAD and optionally in the V5 byte PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default NOLOMARDI 1 NOLOPARDI 1 NOAISARDI 1 UNEQARDI 0 PSLMARDI 0 PSLUARDI 0 TIMARDI 0 TIUARDI 0 PM5363 TUPP+622 154 ...
Page 178
... TIMARDI, PSLUARDI and PSLMARDI. When NOAISARDI is set low, reporting of RDI is according to TIUARDI, TIMARDI, PSLUARDI and PSLMARDI and the associated alarm states. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 155 ...
Page 179
... When NOLOMARDI is set low, reporting of RDI is according to TIUARDI, TIMARDI, PSLUARDI and PSLMARDI and the associated alarm states. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 156 ...
Page 180
... AIS state. When AISPDI is set low, reporting of path PDI due to AIS is inhibited. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default Unused X LOPPDI 0 AISPDI 0 UNEQPDI 0 PDIVPDI 0 Unused X Unused X Unused X PM5363 TUPP+622 157 ...
Page 181
... PDI-P is reported on RAD when the associated incoming tributary is in loss of pointer state. When LOPPDI is set low, reporting of path PDI due to LOP is inhibited. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 158 ...
Page 182
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default Unused X Unused X Unused X Reserved X IAISA X ITPLA X ITV5A X HSCLKA X PM5363 TUPP+622 159 ...
Page 183
... IAIS input. IAISA is set high on a rising edge of IAIS, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 160 ...
Page 184
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default OPTR[7] 0 OPTR[6] 0 OPTR[5] 0 OPTR[4] 0 OPTR[3] 1 OPTR[2] 0 OPTR[1] 1 OPTR[0] 0 Function Default Reserved 0 Unused X Unused X Unused X Unused X Unused X OPTR[9] 1 OPTR[8] 0 PM5363 TUPP+622 161 ...
Page 185
... A value of greater than 782 has no effect. Reserved: The Reserved bit must be written with a logic 0 for proper operation of the TUPP+622. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 162 ...
Page 186
... NOIC1J1PLBYP is ignored when TUGEN is set high or bridge monitoring is disabled in STS-1 #1 (TUG3 #1). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default TUGBYP 0 PIBYP 0 NOIC1J1PLBYP 0 H4SQL 0 Unused X Unused X Unused X Unused X PM5363 TUPP+622 163 ...
Page 187
... Telecom Bus signals, IC1J1 and IPL, to the output Telecom Bus is terminated gracefully. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 164 ...
Page 188
... NOIC1J1PLBYP is ignored when TUGEN is set high or bridge monitoring is disabled in STS-1 #2 (TUG3 #2). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default TUGBYP 0 PIBYP 0 NOIC1J1PLBYP 0 H4SQL 0 Unused X Unused X Unused X Unused X PM5363 TUPP+622 165 ...
Page 189
... Telecom Bus signals, IC1J1 and IPL, to the output Telecom Bus is terminated gracefully. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 166 ...
Page 190
... NOIC1J1PLBYP is ignored when TUGEN is set high or bridge monitoring is disabled in STS-1 #3 (TUG3 #3). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default TUGBYP 0 PIBYP 0 NOIC1J1PLBYP 0 H4SQL 0 Unused X Unused X Unused X Unused X PM5363 TUPP+622 167 ...
Page 191
... Telecom Bus signals, IC1J1 and IPL, to the output Telecom Bus is terminated gracefully. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 168 ...
Page 192
... The outgoing pointer is forced to zero. The IIDLE bit has precedence over the IPAIS bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default CONFIG[1] 1 CONFIG[ LOPV X ALARME 0 DLOP 0 IIDLE 0 IPAIS 0 PM5363 TUPP+622 169 ...
Page 193
... TUG2 #1. The CONFIG[1:0] bits have no effect in TU3 mode. The configuration specified by the CONFIG[1:0] bits are selected as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 170 ...
Page 194
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Configuration TU2 (VT6) VT3 TU12 (VT2) TU11 (VT1.5) PM5363 TUPP+622 Active TU (VT) #1 #1, #2 #1, #2, #3 #1, #2, #3, #4 171 ...
Page 195
... The DLOP bit has no effect when the IPAIS bit is set high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default CONFIG[1] 1 CONFIG[ LOPV X ALARME 0 DLOP 0 IIDLE 0 IPAIS 0 PM5363 TUPP+622 172 ...
Page 196
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Configuration TU2 (VT6) VT3 TU12 (VT2) TU11 (VT1.5) PM5363 TUPP+622 Active TU (VT) #1 #1, #2 #1, #2, #3 #1, #2, #3, #4 173 ...
Page 197
... An LOPxI bit is set high when a loss of PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default Reserved 0 LOP7I 0 LOP6I 0 LOP5I 0 LOP4I 0 LOP3I 0 LOP2I 0 LOP1I 0 PM5363 TUPP+622 174 ...
Page 198
... Reserved: The Reserved bit must be written with a logic 0 for proper operation of the TUPP+622. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES PM5363 TUPP+622 175 ...
Page 199
... the corresponding TUG2 is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Function Default CONFIG[1] 1 CONFIG[ LOPV X ALARME 0 DLOP 0 IIDLE 0 IPAIS 0 PM5363 TUPP+622 176 ...
Page 200
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 4 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S INTERFACES Configuration TU2 (VT6) VT3 TU12 (VT2) TU11 (VT1.5) PM5363 TUPP+622 Active TU (VT) #1 #1, #2 #1, #2, #3 #1, #2, #3, #4 177 ...