SAB80C517A-N18-T3 Infineon Technologies AG, SAB80C517A-N18-T3 Datasheet
SAB80C517A-N18-T3
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SAB80C517A-N18-T3 Summary of contents
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Microcomputer Components 8-Bit CMOS Single-Chip Microcontroller SAB 80C517A/83C517A-5 Data Sheet 05.94 ...
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High-Performance 8-Bit CMOS Single-Chip Microcontroller Preliminary SAB 83C517A-5 SAB 80C517A l SAB 80C517A/83C517A- MHz operation ROM (SAB 83C517A-5 only, ROM-Protection available) l 256 8 on-chip RAM on-chip RAM (XRAM) ...
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SAB 80C517A/83C517A-5 Revision History Previous Releases Page Subjects (changes since last revision 04.91) 6 – Pin configuration P-MQFP-100-2 added 4 – Pin differences updated 7-15 – Pin numbers for P-MQFP-100-2 package added several – Correction of P-MRFP-100 into P-MQFP-100-2 3 ...
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Ordering Information Type Ordering Code SAB 80C517A-N18 Q67120-C583 SAB 80C517A-M18 TBD SAB 83C517A-5N18 Q67120-C582 SAB 80C517A-N18-T3 Q67120-C769 SAB 83C517A-5N18- Q67120-C771 T3 SAB 83C517A-N18-T4 TBD SAB 83C517A-5N18- TBD T4 Semiconductor Group SAB 80C517A/83C517A-5 Package Description 8-bit CMOS Microcontroller P-LCC-84 for external ...
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Logic Symbol Semiconductor Group SAB 80C517A/83C517A-5 4 1994-05-01 ...
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The pin functions of the SAB 80C517A are identical with those of the SAB 80C517/80C537 with one exception: Typ P-LCC-84, Pin 60 P-MQFP-100-2, Pin 36 Pin Configuration (P-LCC-84) Semiconductor Group SAB 80C517A SAB 80C517/80C537 HWPD N.C. 5 SAB 80C517A/83C517A-5 1994-05-01 ...
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Pin Configuration (P-MQFP-100-2) Semiconductor Group SAB 80C517A/83C517A-5 6 1994-05-01 ...
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Pin Definitions and Functions Symbol Pin Number P-LCC-84 P4.0 – P4.7 1– – 9 PE/SWD Input O = Output Semiconductor Group *) I/O Function P-MQFP-100 66, I/O Port ...
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Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 RESET AREF 12 V AGND P7.7 -P7 Input O = Output Semiconductor Group Function *) I/O P-MQFP-100 RESET A low ...
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Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 P-MQFP-100-2 P3 Input O = Output Semiconductor Group SAB 80C517A/83C517A-5 Function *) I/O I/O Port bidirectional I/O ...
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Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 P-MQFP-100-2 P1 100 Input O = Output Semiconductor Group SAB 80C517A/83C517A-5 Function *) I/O I/O Port 1 ...
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Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 P-MQFP-100-2 XTAL2 39 12 XTAL1 40 13 P2 Input O = Output Semiconductor Group SAB 80C517A/83C517A-5 Function *) I/O – ...
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Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 P-MQFP-100-2 PSEN 49 22 ALE P0 Input O = Output Semiconductor Group ...
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Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 P-MQFP-100-2 HWPD 60 36 P5 OWE Input O = Output Semiconductor Group SAB 80C517A/83C517A-5 Function *) I/O I ...
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Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC-84 P-MQFP-100-2 P6 P8 Input O = Output Semiconductor Group ...
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Pin Definitions and Functions (cont’d) Symbol Pin Number P-LCC N.C. – Input O = Output Semiconductor Group Function *) I/O P-MQFP-100 Reset Output This ...
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Figure 1 Block Diagram Semiconductor Group SAB 80C517A/83C517A-5 16 1994-05-01 ...
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Functional Description The SAB 80C517A is based on 8051 architecture fully compatible member of the Siemens SAB 8051/80C51 microcontroller family being an significantly enhanced SAB 80C517. The SAB 80C517A is therefore compatible with code written for the ...
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Program Memory ('Code Space') The SAB 83C517A-5 has 32 Kbyte of on-chip ROM, while the SAB 80C517A has no internal ROM. The program memory can externally be expanded Kbyte. Pin EA controls whether program fetches below address ...
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Data Memory ('Code Space') The data memory space consists of an internal and an external memory space. The SAB 80C517A contains another 2 Kbyte on On-Chip RAM above the 256-bytes internal RAM of the base type SAB 80C517. This RAM ...
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Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM. Note reset occurs during a write operation to XRAM, the effect ...
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Special Function Register XPAGE Addr The reset value of XPAGE is 00 XPAGE can be set and read by software. The register XPAGE provides the upper address byte for accesses to XRAM with MOVX @Ri instructions. If the ...
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Control of XRAM in the SAB 80C517A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On-Chip RAM (XRAM). Special Function Register SYSCON Addr. 0B1 — — H ...
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XMAP0 is hardware protected by an unsymmetric latch. An unintentional disabling of XRAM could be dangerous since indeterminate values would be read from external bus. To avoid this the XMAP-bit is forced to '1' only by reset. Additionally, during reset ...
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Table 1: Behaviour of P0/P2 and / during MOVX accesses Ý DPTR < XRAM a) P0/P2 Bus address active range c) ext. memory is MOVX used @DPTR Ý DPTR XRAM a) P0/P2 BUS ...
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Multiple Datapointers As a functional enhancement to standard 8051 controllers, the SAB 80C517A contains eight 16-bit datapointers. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in special function ...
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Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 81 special function registers include arithmetic registers, pointers, and registers that provide an interface between the ...
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Table 2 Special Function Register (cont’d) Address Register SYSCON H reserved B2 H reserved B3 H reserved B4 H reserved B5 H reserved B6 H reserved IEN1 H B9 IP1 H ...
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Table 2 Special Function Register (cont’d) Address Register reserved H F2 CML6 H F3 CMH6 H F4 CML7 H F5 CMH7 H F6 CMEN H F7 CMSEL H 1) Bit-addressable special function registers 2) X ...
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Table 3 Special Function Registers - Functional Blocks Block Symbol Name CPU ACC Accumulator B B-Register DPH Data Pointer, High Byte DPL Data Pointer, Low Byte DPSEL Data Pointer Select Register PSW Program Status Word Register SP Stack Pointer A/D- ...
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Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Compare/ CCEN Comp./Capture Enable Reg. Capture- CC4EN Comp./Capture Enable 4 Reg. Unit CCH1 Comp./Capture Reg. 1, High Byte (CCU) CCH2 Comp./Capture Reg. 2, High Byte Timer 2 CCH3 ...
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Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Compare/ CLRMSK Mask Register, concerning Capture- COMCLR Unit CTCON Com. Timer Control Reg. (CCU), CTRELH Com. Timer Rel. Reg., High Byte (cont’d) CTRELL Com. Timer Rel. Reg., Low ...
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Table 3 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Timer 0/ TCON Timer Control Register Timer 1 TH0 Timer 0, High Byte TH1 Timer 1, High Byte TL0 Timer 0, Low Byte TL1 Timer 1, Low Byte ...
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A/D Converter In the SAB 80C517A a new high performance / high-speed 12-channel 10-bit A/D-Converter is implemented. Its successive approximation technique provides 7 s con-version time (f MHz). The conversion principle is upward compatible to the one used in the ...
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Figure 4 Block Diagram A/D Converter Semiconductor Group SAB 80C517A/83C517A-5 34 1994-05-01 ...
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Compare/Capture Unit (CCU) The compare/capture unit is a complex timer/register array for applications that require high speed I/O pulse width modulation and more timer/counter capabilities. The CCU contains – one 16-bit timer/counter (timer2) with 2-bit prescaler, reload capability and a ...
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Table 4 CCU Compare Configuration Assigned Timer Compare Register Timer 2 CRCH/CRCL CC1H/CC1L CC2H/CC2L CC3H/CC3L CC4H/CC4L CC4H/CC4L : CC4H/CC4L COMSETL/COMSETH COMCLRL/ COMCLRH CM0H/CM0L : CM7H/CM7L Compare CM0H/CM0L timer : CM7H/CM7L Semiconductor Group SAB 80C517A/83C517A-5 Compare Output Possible Modes P1.0/INT3/CC0 Comp. ...
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Figure 5 Block Diagram of the Compare/Capture Unit Semiconductor Group SAB 80C517A/83C517A-5 37 1994-05-01 ...
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Compare In compare mode, the 16-bit values stored in the dedicated compare registers are compared to the contents of the timer 2 register or the compare timer register. If the count value in the timer registers matches one of the ...
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Reload of Timer 2 A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the 8-bit registers CRCL and CRCH. There are two modes from which to select: Mode 0: Reload is caused by ...
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Figure 6 Block Diagram of Timer 2 Semiconductor Group SAB 80C517A/83C517A-5 40 1994-05-01 ...
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OSC Figure 7 Block Diagram of the Compare Timer Figure 8 Compare-Mode 0 with Registers CM0 to CM7 Semiconductor Group 3-Bit Prescaler Compare Timer / /16 /32 /64 /128 Control (CTCON) 16-Bit Compare Timer Overflow 16-Bit ...
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Figure 9 Compare-Mode 2 (Port 5 only) Semiconductor Group SAB 80C517A/83C517A-5 42 1994-05-01 ...
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Interrupt Structure The SAB 80C517A has 17 interrupt vectors with the following vector addresses and request flags. Table 5 Interrupt Sources and Vectors Interrupt Request Flags IE0 TF0 IE1 TF1 RI0 + TI0 TF2 + EXF2 IADC IEX2 IEX3 IEX4 ...
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Figure 10 Interrupt Structure of the SAB 80C517A Semiconductor Group SAB 80C517A/83C517A-5 44 1994-05-01 ...
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Figure 10 Interrupt Structure of the SAB 80C517A (cont'd) Semiconductor Group SAB 80C517A/83C517A-5 45 1994-05-01 ...
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Figure 10 Interrupt Structure of the SAB 80C517A (cont'd) Semiconductor Group SAB 80C517A/83C517A-5 46 1994-05-01 ...
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Multiplication/Division Unit This on-chip arithmetic unit provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. All operations are integer operation. Operation Result 32-bit/16-bit 32-bit 16-bit/16-bit 16-bit 16-bit 16-bit 32-bit * 32-bit normalize – 32-bit shift left/right ...
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I/O Ports The SAB 80C517A has seven 8-bit I/O ports and two input ports (8-bit and 4-bit wide). Port open-drain bidirectional I/O port, while ports are quasi-bidirectional I/O ports with internal pull-up resistors. That ...
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Power Saving Modes The SAB 80C517A provides – due to Siemens ACMOS technology – four modes in which pow- er consumption can be significantly reduced. – The Slow Down Mode The controller keeps up the full operating functionality, but is ...
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Requirements for Hardware Power Down Mode There is no dedicated pin to enable the Hardware Power Down Mode. Nevertheless for a correct function of the Hardware Power Down Mode the oscillator watchdog unit including its internal RC oscillator is needed. ...
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Power Down Mode Power Down Mode The power down mode is entered by two consecutive instructions directly following each other. The power down mode is entered by two consecutive instructions directly following each other. The first instruction has to set ...
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Table 8 Status of all pins during Idle Mode, Power Down Mode and Hardware Power Down Mode Pins Idle Mode Last instruction executed from internal external ROM ROM P0 Data float P1 Data alt Data alt outputs outputs P2 Data ...
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Table 8 Status of all pins during Idle Mode, Power Down Mode and Hardware Power Down Mode (cont’d) Pins Idle Mode Last instruction executed from internal external ROM ROM PSEN ALE VAREF VAGND OWE RESET RO Semiconductor Group SAB 80C517A/83C517A-5 ...
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Serial Interfaces The SAB 80C517A has two serial interfaces. Both interfaces are full duplex and receive buffered. They are functionally identical with the serial interface of the SAB 8051 when working as asynchronous channels. Serial interface 0 additionally has a ...
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Serial Interface 0 Serial Interface 0 can operate in 4 modes: Mode 0: Shift register mode: Serial data enters and exits through R clock 8 data bits are transmitted/received (LSB first). The baud rate is fixed at 1/12 of the ...
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Serial Interface 1 Serial interface 1 can operate in two asynchronous modes: Mode A: 9-bit UART, variable baud rate. 11 bits are transmitted (through T a start bit (0), 8 data bits (LSB first), a programmable 9th, and a stop ...
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Watchdog Units The SAB 80C517A offers two enhanced fail safe mechanisms, which allow an automatic recovery from hardware failure or software upset: – programmable watchdog timer (WDT), variable from 512 appr. 1.1 s time-out period @12 MHz. ...
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Oscillator Watchdog The unit serves three functions: – Monitoring of the on-chip oscillator’s function. The watchdog supervises the on-chip oscillator’s frequency lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock ...
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Figure 12 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group SAB 80C517A/83C517A-5 59 1994-05-01 ...
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Fast internal reset after power-on The SAB 80C517A can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally members of the 8051 family (like the SAB 80C517) enter their default reset state not before the ...
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Absolute Maximum Ratings Ambient temperature under bias................................................................. – 110˚ C Storage temperature ................................................................................... – 150 Voltage on V pins with respect to ground (V CC Voltage on any pin with respect to ground (V Input current ...
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DC Characteristics (cont’d) Parameter Output low voltage (ports Output low voltage (ports ALE, PSEN, RO) Output high voltage (ports Output high voltage (port 0 in external bus mode, ...
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Notes for page 62: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V of ALE and ports and 6. The noise is due to external bus ...
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A/D Converter Characteristics – 5 AREF CC AGND = – ...
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AC Characteristics – for port 0, ALE and PSEN outputs = 100 pF Parameter Symbol Program Memory Characteristics ALE pulse width t Address setup to ALE ...
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AC Characteristics (cont’d) Parameter Symbol External Data Memory Characteristics RD pulse width t WR pulse width t Address hold after ALE valid data in t Data hold after RD t Data float after RD t ALE to ...
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ALE PSEN Port 0 Port 2 Program Memory Read Cycle Data Memory Read Cycle Semiconductor Group SAB 80C517A/83C517A-5 t LHLL t t AVLL PLPH t LLPL t LLIV t PLIV t t AZPL PXAV t t LLAX PXIZ t PXIX ...
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ALE PSEN WR t AVLL from Port DPL t AVWL Port 2 Data Memory Write Cycle Semiconductor Group t t LLWL WLWH t QVWX LLAX2 t QVWH Data OUT P2.0 - P2.7 or ...
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AC Characteristics (cont'd) Parameter Symbol External Clock Drive Oscillator period t High time t Low time t Rise time t Fall time t Oscillator frequency 1/t External Clock Cycle Semiconductor Group Variable clock Frequ. = 3.5 MHz to 18 MHz ...
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AC Characteristics (cont'd) Parameter System Clock Timing ALE to CLKOUT CLKOUT high time CLKOUT low time CLKOUT low to ALE high System Clock Timing Semiconductor Group Symbol 18 MHz clock min. max. 349 – t LLSH t 71 – SHSL ...
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ROM Verification Characteristics T = 25˚C 5˚ 10 Parameter Symbol ROM Verification Mode 1 (Standard Verify Mode for not Read Protected ROM) Address to valid data t ENABLE to valid data t Data ...
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ROM Verification Mode 2 (New Verify Mode for Protected and not Protected ROM) ROM Verification Mode 2 Semiconductor Group SAB 80C517A/83C517A-5 72 1994-05-01 ...
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Application Circuitry for Verifying the Internal ROM Semiconductor Group SAB 80C517A/83C517A-5 73 1994-05-01 ...
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AC Inputs during testing are driven at V ments are made at V for a logic ’1’ and V IHmin AC Testing: Input, Output Waveforms For timing purposes a port pin is no longer floating when a 100 mV change ...
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Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package) Figure 1 P-MQFP-100-2 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group SAB 80C517A/83C517A-5 ...
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Plastic Package, P-LCC-84-2 (SMD) (Plastic Leaded Chip Carrier) Figure 2 P-LCC-84-2 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group SAB 80C517A/83C517A-5 76 ...