AM79C32AVC Advanced Micro Devices, AM79C32AVC Datasheet
AM79C32AVC
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AM79C32AVC Summary of contents
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... MCLK This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Certified protocol software support available CMOS technology, TTL compatible D-channel processing capability — ...
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DISTINCTIVE CHARACTERISTICS (continued) Audio processing capability (DSC circuit only) — Registers for implementation of software-based speaker phone algorithms — Dual audio inputs — Earpiece and loudspeaker drivers — Codec/filter with A/ selection — Programmable gain and equalization filters GENERAL DESCRIPTION ...
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CONNECTION DIAGRAMS Top View CAP1 CAP2 RESET RSRVD RSRVD RESET Note: 1. Pin 1 is marked for orientation ...
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CONNECTION DIAGRAMS (continued) Top View CAP1 CAP2 RESET RSRVD RSRVD RESET Note: Pin 1 is marked for orientation ...
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ORDERING INFORMATION Standard Products ® AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM79C30A/32A J Valid Combinations AM79C30A JC, VC AM79C32A JC, VC ...
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PIN DESCRIPTION* Line Interface Unit (LIU) HSW Hook-Switch (Input) The HSW signal indicates if the hook-switch off hook. This signal may be generated with a mechanical switch wired to ground with a pull-up resistor to V Any ...
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RD Read (Input) The active Low read signal is conditioned by CS and in- dicates that internal information transferred onto the data bus. A number of internal registers are user accessible. The contents of the accessed register ...
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OPERATIONAL DESCRIPTION Overview of Power Modes The minimization of power consumption is a key factor in the design of Terminal Equipment for the ISDN, and the DSC/IDC circuit employs two basic approaches to power management: 1. The power consumption of ...
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The LIU receiver is enabled, detects an incoming signal on the S/T Interface, and achieves activation as indicated by a transition to state F7. Both the INT pin and the F7 transition interrupt must be enabled for Power-Down mode ...
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INIT2 Register (INIT2) default = 00H Address = Indirect 20 Hex, Read/Write A special write procedure must be followed in order to modify the contents of the INIT2 Register, since the INIT2 Register includes control bits which could result in ...
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Bc buffers must be accessed within 122.4 µs. This is to prevent erroneous data transfers. Only one interrupt is used to signal accessibility for both B channels of the S Interface. Since the data transfer must occur synchro- nously to ...
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Table 4. Format of the Interrupt Register (IR), Read Only Bit Interrupt Generated/Action Required 0 D-channel transmit threshold interrupt/load D-channel Transmit buffer 1 D-channel receive threshold interrupt/read D-channel Receive buffer 2 D-channel status interrupt/read DSR1 Source Cause DSR1 bit 0 ...
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FUNCTIONAL DESCRIPTION Microprocessor Interface (MPI) The Am79C30A/32A can be connected to any general purpose 8-bit microprocessor via the MPI. The MCLK from the Am79C30A/32A can be used as the clock for the microprocessor. The MPI is an interrupt-driven in- terface ...
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Operation Block Register INIT Initialization Register INIT Initialization Register 2 LIU LIU Status Register LIU LIU Priority Register LIU LIU Mode Register 1 LIU LIU Mode Register 2 LIU — LIU Multiframe Register LIU Multiframe S-bit/Status Register LIU Multiframe Q-bit ...
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Table 7. Indirect Register Access Guide (Continued) Operation Block Register DLC D-channel Mode Register 1 DLC D-channel Mode Register 2 DLC — DLC D-channel Receive Byte Count Register DLC Random Number Generator Register DLC Random Number Generator Register DLC First ...
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TEs connected to one NT. Line Code Pseudo-ternary coding is used for both transmitting and receiving over the S Interface. In this type of cod- ing, a binary 1 is represented by a space (zero ...
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Frame Number NT-to-TE Q Control Bit ...
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LIU Registers The LIU contains the registers shown in Table 9. Table 9. LIU Registers Registers No./Registers Mnemonic LIU Status Register 1 LIU Priority Register 1 LIU Mode Registers 2 Multiframe Register 1 Multiframe S-bit/Status 1 Register Multiframe Q-bit buffer ...
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LIU Mode Register (LMR1), Read/Write Address = Indirect A3H LMR1 is defined in Table 12. Bit Logical 1 0 Enable B1 transmit 1 Enable B2 transmit 2 Disable F transmit 3 Disable F transmit A 4 Activation request 5 Go ...
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The three D-channel loopback controls defined in LMR2 bits 0, 1, and 2 are explained below: Bit 0, D-channel loopback at Am79C30A/32A enable: Am79C30A This remote loopback is provided for maintenance pur- poses from ...
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Multiframe S-bit/Status Buffer (MFSB), Read Only Address = Indirect A7H Table 15. Multiframe S-Bit/Status Buffer Bit Description Generates Interrupt S-data available If MF bit ...
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Bb MPI Bc Therefore, in this example, MCR1 provides a data link from the S Interface and MCR2 sets up a voice connec- tion across the S Interface. To loopback a channel, the same channel code is used for port ...
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MUX Control Register 4 (MCR4), Read/Write Address = Indirect 44H The MUX Control Register 4 (MCR4) can prevent interrupt generation by masking the output of IR bit 4. MCR4 has the format shown in Table 19. Bit Logical 1 0–2 ...
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Main Audio Processor (MAP) (Am79C30A only) Overview The MAP, as illustrated in Figure 3, implements au- dio-band analog-to-digital (ADC) and digital-to-analog (DAC) conversions together with a wide variety of audio support functions. Analog interfaces are provided for a handset earpiece, ...
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Programmable Analog Preamplifier A programmable analog preamplifier GA is included in front of the A/D converter and is adjustable in 6-dB in- crements from +24 dB. The existing GX gain stage in the transmit path may be ...
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The peak registers are double-buffered and can be read asynchronously to the operation of the DSP register. They are cleared on read. 7. The peak registers default to “don't care” values when the part is reset. An initial read ...
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The output frequency of the DTMF tone generator ap- proximately equals: 64000 DTMF Frequency --------------------------------------------------- - integer 8192 i where i is the decimal equivalent of value programmed into the FTGR register. This allows the DTMF genera- ...
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Programmable Gain Coefficients The GER, GR, GX, and Sidetone gain coefficients are each 16 bits in length. Two consecutive register locations correspond to one gain coefficient. The LSB is transferred first to (or from) the microprocessor. Sample coefficients for the ...
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Example coefficients for the GR, GX, and STG filters are listed in Tables 25, 26, and 27. The gain values are rounded off to the nearest 0.1 dB. Table 25. GX Gain Coefficients Hex Code Gain (dB) MSB 0.0 08 ...
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Table 27. STG Gain Coefficients Hex Code Gain (dB) MSB –18.0 8B –17.5 8B –17.0 8B –16.5 8B –16.0 8B –15.5 8B –15.0 91 –14.5 91 –14.0 91 –13.5 91 –13.0 91 –12.5 91 –12.0 91 –11.5 91 –11.0 91 ...
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... Ai = – The X and R filter coefficients are programmed using a 16-byte transfer with the format shown in Table 30. Note: AmMAP™ software, which calculates X and R filter coeffi- cients, is available from Advanced Micro Devices. Contact your local AMD Sales Office for more information. 3 – 4 ...
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MAP digital circuitry is functional. Note that the digital patterns received after loopback will not be identical to the transmitted patterns. The D-D gain is approximately 2.5 dB. MAP Digital Loopback 2 This loopback mode connects the ...
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MAP Mode Register 1 — (MMR1) — Read/Write Address = Indirect 69H Bit Logical 1 0 A-Law 1 GX coefficient loaded from register 2 GR coefficient loaded from register 3 GER coefficient loaded from register 4 X coefficient loaded from ...
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Map Mode Register 3 — (MMR3) — Read/Write Address Indirect 6CH Bit Function Bit 7 Reserved, must be written ...
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Secondary Tone Ringer Frequency Register (STRF), Read/Write; Address = Indirect 6EH STRF is a Read/Write register controlling the frequency of the secondary tone ringer. Hex codes 7F and 00 are re- served and should not be used. The coefficients are ...
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Table 37. Frequencies for Secondary Tone Ringer (Continued) Counter Frequency Counter Value (Hz) Value 24 827 813 800 786.9 0-8 B2 774 761 150 738.5 B0 Data Link ...
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When receiving, the DLC examines the frame con- tent between the ...
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DMR4 DMR1 Bits Bit 7 Bit ...
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Am79C30A/32A receives the first two bytes, issues an End of Address interrupt, and receives the packet. Both a Valid Address and an End of Ad- dress interrupt set Interrupt Register bit logical 1 and bit ...
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D-channel Re- ceive buffer. The incoming bit stream (including FCS) is run through the FCS generation and compare block. Upon receipt of ...
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D-Channel Receive and Transmit Errors Non-Integer Number of Bytes A non-integer number of bytes occurs when the num- ber of D-channel bits received between opening and closing flags is not divisible by eight received packet consists of a ...
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Transmit Address Register — (TAR) — Read/Write Address = Indirect 83H This register contains the address of the packet to be transmitted if the TAR bit is enabled (DMR1 bit 2). First Received Byte Address Register — (FRAR1–FRAR4) — Read/Write ...
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D-Channel Mode Register 2 — (DMR2) — Read/Write Address = Indirect 87H DMR2 is used to enable/disable the interrupts generated in the DER (see DER definition on page 41). DMR2 is con- trolled by the microprocessor and does not generate ...
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D-Channel Mode Register 4 — (DMR4) — Read/Write Address = Indirect 8FH Bit ...
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D-Channel Status Register 1 — (DSR1) — Read Only DSR1 has the format shown in Table 44. Bit Logical 1 0 Valid Address (VA) if the address decode logic is enabled or End-of-Address (EOA) if the address decode logic is ...
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D-Channel Status Register 2 — (DSR2) — Read Only DSR2 has the format illustrated in Table 46. Bit Logical 1 0 Last byte of received packet 1 Receive byte available 2 Receive packet lost 3 Last byte transmitted 4 Transmit ...
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D-Channel Error Register — (DER) — Read Only The DER has the format illustrated in Table 48. Bit Logical 1 0 Received Packet Abort 1 Non-integer number of bits have been received 2 Collision Detected 3 FCS Error 4 Overflow ...
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Peripheral Port (PP) Overview The purpose of the Peripheral Port is to allow external peripherals to be connected to the DSC/IDC circuit. There are two basic modes of operation, Serial Bus Port mode, and IOM-2 Terminal mode. Within IOM-2 Terminal ...
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SCLK 192 kHz MSB SBIN or SBOUT SFS 41.7 µs Note: SBIN is ...
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DSC/IDC Circuit IOM-2 Terminal Mode Implementation Data Channels The B1 and B2 channels are physically the first two 8-bit time slots after the frame sync pulse. When mak- ing a MUX connection to these channels, IOM-2 chan- nels B1 and ...
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MASTER Mode DSC is the timing master (FSC and SCLK are outputs) and control master (can communicate with down- stream devices). The configuration of timing master and control slave is covered within this mode. The pres- SBOUT DSC SBIN DD ...
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SLAVE Mode — Bus Reversal Enabled DSC is the timing slave (FSC and SCLK are inputs) and control master (can communicate with other down- SBOUT DSC SBIN DD Downstream # Downstream #2 DU Figure 9. IOM-2 Slave Mode ...
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SLAVE Mode — Bus Reversal Disabled DSC is the timing slave (FSC and SCLK are inputs) and control master (cannot communicate with other SBOUT DSC SBIN DD Downstream # Downstream #2 DU Figure 10. IOM-2 Slave Mode Operation ...
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Intelligent NT Either Slave mode can be used to implement the Intel- ligent NT configuration. The diagram below depicts this configuration using DSC Slave mode with bus reversal disabled. The U-transceiver operates as the IOM-2 master de- vice, programmed to ...
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Monitor Channel Procedures The Monitor channel operates on an event-driven ba- sis; although data transfers on the bus are synchro- nized to the frame sync, the flow of data is controlled by a handshake procedure using the outgoing MX and ...
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MX Transmitter MX First Byte MR Receiver MR MX Transmitter MX MR Receiver MR MX Transmitter MX First Byte MR Receiver MR 56 New Byte Last Byte ACK ACK n • 125 µs 125 µs a. General Case New Byte ...
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IOM-2 Activation/Deactivation The IOM-2 Interface includes an activation/deactivation capability (see Figure 13). Activation and deactivation can be initiated from either upstream or downstream components on the bus. When deactivated, the up- stream device holds all the clock outputs Low, and ...
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Register Number 1 (PPCR1). When this bit is cleared, the data output pin (SBOUT) is also forced to High-Z (seen as a High on the system bus due to the external pullup resistor), and the Am79C30A begins monitoring the data ...
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DSC has no D-channel communications also in progress. A priority scheme is included to prevent the DSC from dominating the bus. A new bus access will not be al- lowed until the device detects BAC bit set ...
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Peripheral Port Registers The PP contains the following registers: Registers Peripheral Port Control Register Peripheral Port Status Register Peripheral Port Interrupt Enable Register Monitor Transmit Data Register Monitor Receive Data Register C/I Transmit Data Register C/I Receive Data Register Peripheral ...
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Peripheral Port Control Register 1 (PPCR1) — (continued) Bit Function 1–0 Port Mode Select Field—These two bits select the configuration of the Peripheral Port as follows. Bit 1 0 Function 0 0 Port Disabled 0 1 SBP mode enabled 1 ...
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Peripheral Port Interrupt Enable Register (PPIER Default = Write = 00 Hex, Read = Bit Bits 6– Address = Indirect C2 Hex, Read/Write 7 6 ENABL ENABL PP/MF IOM-2 CHNG INT EN TIME ...
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C/I Transmit Data Register 0 (C/ITDR0) Default = 0F Hex Address = Indirect C4 Hex, Write 7 6 Bus Access RSRVD RSRVD Request The C/I Transmit Data Register 0 is the user-visible portion of the C/I channel 0 transmitter. Data ...
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Peripheral Port Control Register 2 (PPCR2) Default = Bits 7, 6, and Bit Bits 4–1 are Indeterminate* Address = Indirect C8 Hex, Read/Write 7 6 REV REV CODE CODE BIT 2 BIT 1 (MSB) ...
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APPLICATIONS ISDN Feature Phone This basic feature phone is the ISDN equivalent to the common analog phone. The keypad can be a simple four-by-four single-pole switch-matrix or a larger-matrix to provide full-key system features. The display option illustrated in Figure ...
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PSB2110 ISGN Terminal Adaptor Circuit V.110 Processor Terminal Interface Terminal Port UART HDLC FIFO FIFO Microprocessor Interface Interrupts 3 Microcontroller Figure 15. Terminal Adapter (V.110/V.120) With Voice Upgrade Capability 66 Speaker Tone Am79C32A DSC Circuit Serial B-Channel PP Port MUX ...
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Am85C30 or PSB82525 Data Link Data Link Controller Controller Microprocessor Interface DMA Controller 80188 DMA Timers Interrupts Am85C30/PSB82525 CPU Chip DSC Circuit Selects Memory Clock Figure 16. PC Add-On Board ( Data Channels) Analog Telephone Interface Am79C30A DSC ...
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ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Storage temperature –65°C to +150°C Ambient temperature with power applied . . . . . . . . . . . . . –55°C to +125°C Supply voltage to ground, potential continuous . . . ...
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Table 51. Revision E Power Specifications for CCITT-Restricted Mode Phone Operation Parameter Parameter Test Conditions Symbol Descriptions Supply Current Clocks & Oscillator Stopped; LIU Receiver Enabled; S Interface CC (Power-Down mode) Silent (INFO 0) ...
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MAP Transmission Characteristics (Am79C30A only) The codec is designed to meet CCIIT Recommenda- tion G.714 requirements for signal to distortion, gain tracking, frequency response, and idle channel noise specification as defined in Table 53. Verification of con- formance to G.714 ...
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Table 54. Codec Performance Specifications (Am79C30A only) Parameter Parameter Descriptions Symbol TXG Transmit absolute gain RXGE Receive absolute gain at EAR1/EAR2 (nominal) RXGL Receive absolute gain TXSTD Transmit signal/total distortion; CCITT method 2, 1020 Hz (Tx gain = 0) RXSTD ...
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Figure 17. Attenuation/Frequency Distortion (Transmit) 750 380 130 500 Figure 18. Group Delay Variation with Frequency (Transmit) 72 Frequency (Hz) 600 1000 Frequency (Hz) Am79C30A/32A Data Sheet 9 dB 09893H-13 2600 2800 09893H-14 ...
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Input Level (dBm0) –1.6 Figure 19. Gain Tracking Error (Transmit) (CCITT Method 2 at 1020 Hz) Am79C30A/32A Data Sheet –10 +3 09893H-15 73 ...
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Figure 20. Signal-to-Total Distortion Ratio (Transmit) (CCITT Method 2 at 1020 Hz) 0.9 0.25 0 –0.25 300 1020 Frequency (Hz) Figure 21. Attenuation/Frequency Distortion (Receive) 74 –45 –40 –30 Input Level (dBm0) Am79C30A/32A Data Sheet –10 ...
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Frequency (Hz) Figure 22. Group Delay Variation with Frequency (Receive) 1.6 0.6 0.3 –55 –50 –40 –0.3 –0.6 Input Level (dBm0) –1.6 Figure 23. Gain Tracking Error (Receive) (CCITT Method 2 at 1020 Hz) ...
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Input Level (dBm0) Figure 24. Signal-to-Total-Distortion Ratio (Receive) (CCITT Method 2 at 1020 Hz) 76 –45 –40 –30 Am79C30A/32A Data Sheet –10 0 09893H-18 ...
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LIU Characteristics All of the parameters below are measured at the chip terminals and are consistent with 2:1 transformers. Parameter Symbol Parameter Descriptions V Output mark amplitude measured between LOUT2 and LOUT1 (Note 1) LOUT Receivable input level measured between ...
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R + LOUT2 V LOUT LOUT1 – LIN1 LIN2 R Notes Transmitter output at the S-interface reference point. (s-interface the termination impedence at the S interface the effective ...
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I LOUT LOUT2 + V LOUT LOUT1 – Notes the DC impedance of the transformer secondary (IC side of transformer). SEC the DC impedance of the transformer primary (line side of transformer). PRIM 3. ...
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Microprocessor Read/Write Timing Microprocessor Read Timing Parameter Symbol Parameter Description t RD Pulse Width RLRH t Read Recovery Time (Notes 1, 2) RHRL t Address Valid to RD Low AVRL t Address Hold After RD High AHRH t RD High ...
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ADDR t t AVRL AHRH t RDCS CS t RHCH t t RLRH FHFL RD/WR Read t t RACC RHDZ DATA Figure 29. Microprocessor Read/Write Timing Interrupt Timing Parameter Symbol Parameter Description t INT Cycle Time INTC t INT Recovery ...
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Reset and Hookswitch Timing Reset Timing Parameter Symbol Parameter Description t Reset Pulse Width RES t Power Stable to Reset Low PHRL t Reset Transition Fall Time F t Reset Transition Rise Time R Hookswitch Timing Parameter Symbol Parameter Description ...
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OSC (XTAL2) Timing Parameter Symbol Parameter Description t Oscillator Period CLCL t High Time CH t Low Time CL t Rise Time CLCH t Fall Time CHCL Note: Frequency = 12.288 MHz ±80 ppm. MCLK Timing Parameter Symbol Parameter Description ...
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OSC Divide by 1 12.288 MHz Divide by 2 6.144 MHz Divide by 3 4.096 MHz t FALL 1,2 Divide by 4 3.072 MHz SBP Mode Timing Parameter Symbol Parameter Description Tp* ...
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Ta SCLK SBIN or SBOUT Bd SFS T1 BCL/CH2STRB Notes: 1. For PPCR2( SBIN data is sampled on the rising edge of SCLK; SBOUT data is changed on the falling edge of SCLK. For PPCR2( SBIN ...
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IOM-2 Master Mode Timing Parameter Signal Data Clock Rise/Fall SCLK Clock Period SCLK Pulse Width SCLK Frame Sync SFS Frame Sync Setup/Clock SFS Frame Sync Delay/Clock SFS Frame Sync Hold/Clock SFS Frame Delay SFS Data Delay/Clock SBOUT Data Hold/Clock SBOUT ...
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BCL SFS SBOUT Bit 95 SBIN Note: ** SFS width is 16 SCLK cycles + setup and hold time. BCL t R SCLK t FD SFS SBOUT SBIN Note Master Mode, SFS is 16 SCLK cycle ...
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Switching Test Conditions 2.4 V 0.45 V Note: AC testing inputs are driven at 2.4 V for a logical 1, and 0.45 V for a logical 0. Timing measurements are made at 2.0 V and 0.8 V for a logical ...
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APPENDIX A Table 1. Coefficients for GX, GR, and STG Attenuators Hex Gain (dB) MSB LSB –84 –78 –72 –66 –60 –54 –50 –49 ...
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Table 1. Coefficients for GX, GR, and STG Attenuators (Continued) Hex Gain (dB) MSB LSB –29 –29 –29 –29 –29 –29 –29 –29 –29.1 ...
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Table 1. Coefficients for GX, GR, and STG Attenuators (Continued) Hex Gain (dB) MSB LSB –12 –12 –11 –11 –11 –11 –11 –11 –11.3 ...
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Table 1. Coefficients for GX, GR, and STG Attenuators (Continued) Hex Gain (dB) MSB LSB 1.8 ...
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Table 2. Coefficients for GER Attenuators (Continued) Hex Gain (dB) MSB LSB –18 –18 –18 –18 –18 –17 –17 –17 –17 –16.1 ...
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Table 2. Coefficients for GER Attenuators (Continued) Hex Gain (dB) MSB LSB –2 –2 –2 –1 –1 –1 –1 –1 –1 –1.3 ...
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Table 2. Coefficients for GER Attenuators (Continued) Hex Gain (dB) MSB LSB 11.2 ...
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APPENDIX B KEY DESIGN HINTS FOR THE DSC/IDC CIRCUIT Due to the high level of integration of the Am79C30A/ 32A DSC/IDC circuit easy to overlook important design information when reading the data sheet. The following list of key ...
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The sidetone path defaults to –18-dB attenuation. If disabling the sidetone path is desired, the sidetone block must be enabled and programmed for infinite attentuation. • Consider the LIU transformers, series resistors, and IC LIU output drivers as a ...
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APPENDIX C PHYSICAL DIMENSIONS PL 044 .685 .695 .650 .656 .685 .695 Pin 1 I.D. .650 .656 .026 .032 TOP VIEW Note: Dimensions are measured in inches. 98 .042 .056 .009 .015 .050 REF Am79C30A/32A Data Sheet .062 .083 .500 ...
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PHYSICAL DIMENSIONS 1 -A- 0.95 1.05 1.00 REF. Note: Dimensions are measured in inches. PQT 44 44 -D- 9.80 10.20 11.80 12.20 TOP VIEW 11° – 13° 0.80 BSC 11° – 13° 0.30 0.45 SIDE VIEW Am79C30A/32A Data Sheet 11.80 ...
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... AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. AmMAP, Digital Subscriber Controller, DSC, and IDC are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...
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AMENDMENT Am79C30A/32A Digital Subscriber Controller™ (DSC™) Circuit Table 23: Amplitude Gain Coefficients on page 27 of the Am79C30A/32A final data sheet has the following changes: The tone gain block was intended to provide amplitude steps with a ...