DS1387 Dallas Semiconductor, DS1387 Datasheet
DS1387
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DS1387 Summary of contents
Page 1
... AD4 8 AD5 9 16 GND AD5 9 AD6 AD6 10 AD7 11 14 ALE AD7 11 GND GND 12 DS1385 24–PIN DIP DS1387 24–PIN (600 MIL) ENCAPSULATED PACKAGE (740 MIL FLUSH) OER SQW AS0 AD0 5 24 AS1 AD1 6 23 ...
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... Address/data multiplexing does not slow the ac- cess time of the DS1385/DS1387 since the bus change from address to data occurs during the internal RAM ac- cess time. Addresses must be valid prior to the latter portion of ALE, AS0, or AS1, at which time the DS1385/DS1387 latches the address from AD0 to AD7 ...
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... DS1385/DS1387 BLOCK DIAGRAM Figure OSC CS POWER V CC SWITCH AND WRITE POK PROTECT V BAT + +3V – BUFFER ENABLE ALE CLOCK/ BUS CALENDAR INTERFACE UPDATE AD0-AD7 AS1 BCD/BINARY INCREMENT AS0 WER OER ADDRESS HIGH BYTE LATCH ADDRESS LOW NONVOLATILE RAM ...
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... Underwriters Laboratories for UL listing (E99151). ADDRESS MAP The address map of the DS1385/DS1387 is shown in Figure 2. The address map consists of the RTC and the SRAM section. The RTC section contains 50–bytes of user RAM, 10–bytes of RAM that contain the RTC time, calendar, and alarm data, and 4– ...
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... ADDRESS MAP DS1385/DS1387 Figure 14–BYTES 50–BYTES USER RAM 000 SRAM 4096 FFF TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by read- ing the appropriate register bytes shown in Table 1. The time, calendar and alarm are set or initialized by writing the appropriate register bytes ...
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... Year USER NONVOLATILE RAM – RTC The 50 user nonvolatile RAM bytes are not dedicated to any special function within the DS1385/DS1387. They can be used by the application program as nonvolatile memory and are fully available during the update cycle. This memory is directly accessible in the RTC section. ...
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... Register C clears all active flag bits and the IRQF bit. OSCILLATOR CONTROL BITS When the DS1385/DS1387 is shipped from the factory, the internal oscillator is turned off. This feature prevents the lithium battery from being used until it is installed in a system. A pattern of 010 in bits 6 through 4 of Register A ...
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... UPDATE CYCLE The DS1385/DS1387 executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar and alarm by- tes is frozen and will not update as the time increments ...
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... When the AIE bit is set to zero, the AF bit does not initiate the IRQ signal. The in- ternal functions of the DS1385/DS1387 do not affect the AIE bit. UIE – The Update Ended Interrupt Enable (UIE) bit is a read/write bit that enables the Update End Flag (UF) bit in Register C to assert IRQ ...
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... BIT RAM The DS1385/DS1387 provides on–chip SRAM which is controlled as nonvolatile storage sustained from a lithium battery. On power–up, the RAM is taken out of write–protect status by the internal power OK sig- nal (POK) generated from the write protect circuitry. ...
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... Standby Current CS, OER and I CC2 WER = V –0.3 volt CC Input Leakage I IL I/O Leakage I LO Output @ 2.4 volts I OH Output @ 0.4 volts I OL –0.3V to +7. DS1387: – +70 C DS1385: – +125 C 260 C for 10 seconds ( MIN TYP MAX UNITS 4.5 5.0 5.5 V 2 –0.3 +0 ...
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... DS1385/DS1387 RTC AC TIMING CHARACTERISTICS PARAMETER SYMBOL Cycle Time t CYC Pulse Width, RD/WR Low PW EH Pulse Width, RD/WR High PW EL Input Rise and Fall Time Chip Select Setup Time Before Chip Select Hold Time t CH Read Data Hold Time t DHR ...
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... DS1385/DS1387 BUS TIMING FOR WRITE CYCLE TO RTC PW ASH ALE t ASD ASD ASL AD0–AD7 DS1385/DS1387 BUS TIMING FOR READ CYCLE TO RTC PW ASH ALE t ASD ASD ASL AD0–AD7 IRQ t CYC t ASED ...
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... DS1385/DS1387 TIMING CHARACTERISTICS PARAMETER SYMBOL Address Setup Time t AS Address Hold Time t AH Data Setup Time t DS Data Hold Time t DH Output Enable Access Time t OEA Write Pulse Width t WP OER Pulse Width t RP OER to Output in High Z t OEZ ...
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... BUS TIMING FOR WRITE CYCLE SRAM t OER = V ASP IH AS0 AS1 WER AD0–AD7 LOW ADDRESS VALID UPPER ADDRESS VALID POWER–UP CONDITION CE 4.5V 4.25V 4. POWER FAIL t ASP t ASW DATA IN VALID REC t R DS1385/DS1387 012496 15/20 ...
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... DS1385/DS1387 POWER–DOWN CONDITION POWER FAIL POWER–UP POWER–DOWN TIMING PARAMETER SYMBOL CE High to Power Fail t PF Recovery at Power Up t REC V Slew Rate Power Down 4.0 < Slew Rate Power Down 3.0 <V < 4. Slew Rate Power 4.5V>V CC Expected Data Retention ...
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... Measured with a load as shown in Figure 4. 8. The real–time clock will keep time to an accuracy of 1 minute per month during data retention time for the period Applies to DS1385 and DS1385S only. OUTPUT LOAD Figure 4 D.U.T. 680 +5 VOLTS 1. DS1385/DS1387 012496 17/20 ...
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... DS1385/DS1387 DS1385 24–PIN DIP 012496 18/20 PKG 24–PIN DIM MIN MAX IN. 1.245 1.270 MM 31.62 32.26 B IN. 0.530 0.550 MM 13.46 13.97 C IN. 0.140 0.160 MM 3.56 4.06 D IN. 0.600 0.625 MM 15.24 15.88 E IN. 0.015 0.050 MM 0.38 1.27 F IN. 0.120 0.145 MM 3.05 3.68 G IN. 0.090 0.110 MM 2.29 2. IN. 0.625 0.675 MM 15.88 17. IN. ...
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... PKG 28–PIN DIM MIN A IN. 0.706 MM 17.93 B IN. 0.338 MM 8.58 C IN. 0.086 MM 2.18 D IN. 0.020 MM 0.58 E IN. 0.002 MM 0.05 F IN. 0.090 MM 2.29 C 0.050 BSC G IN. 1. IN. 0.460 MM 11.68 J IN. 0.006 MM 0.15 K IN. 0.014 MM 0.36 F DS1385/DS1387 MAX 0.728 18.49 0.350 8.89 0.110 2.79 0.050 1.27 0.014 0.36 0.124 3.15 0.480 12.19 0.013 0.33 0.020 0.51 012496 19/20 ...
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... DS1385/DS1387 DS1387 24–PIN 740 MIL FLUSH ENCAPSULATED EQUAL SPACES AT .100 .010 TNA 012496 20/20 13 PKG 24–PIN DIM MIN A IN. 1.320 MM 33. IN. 0.720 MM 18.29 C IN. 0.345 MM 8.76 D IN. 0.100 MM 2.54 E IN. 0.015 MM 0. IN. 0.110 MM 2. IN. 0.090 MM 2.29 H IN. 0.590 MM 14.99 J IN. ...