ML2653CQ Micro Linear, ML2653CQ Datasheet

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ML2653CQ

Manufacturer Part Number
ML2653CQ
Description
10 base-T physical interface chip
Manufacturer
Micro Linear
Datasheet

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GENERAL DESCRIPTION
The ML2652, 10BASE-T Physical Interface Chip, is a
complete physical interface for twisted pair and AUI
Ethernet applications. It combines a 10BASE-T MAU,
Manchester Encoder/Decoder, and Twisted Pair Interface
filters in one monolithic IC. A complete DTE interface for
twisted pair Ethernet can be implemented by combining
the ML2652, an Ethernet controller, and transformers.
The ML2652 can automatically select between an AUI and
twisted pair interface based on Link Pulses. Six LED
outputs provide complete status at the physical link. Link
pulse testing can be enabled or disabled through the
LTP LED Pin.
The unique transmitter design uses a waveform generator
and low pass filter to meet the 10BASE-T transmitter
requirements without the need for an external filter. The
differential current driven output reduces common mode
which in turn results in very low EMI and RFI noise.
The ML2652 and ML2653 (28 pin version) are implemented
in a low power double polysilicon CMOS technology. The
ML2653 does not include the AUI interface.
ML2652 BLOCK DIAGRAM
TxC
TxE
TxD
LPBK
CLK
COL
RxC
RxE
RxD
CS0 CS1 CS2 FD V
OSC
CONTROLLER
RPOL
INTERFACE
AUISEL
CC
DATA
ENABLE
COLLISION
DATA
ENABLE
V
XMT
CC
MANCHESTER
MANCHESTER
10Base-T Physical Interface Chip
ENCODER
DECODER
GND
CLS
LEDS
GND
RCV
FEATURES
DETECT
JABBER
COLLISION
LTP
Complete physical interface solution
Conforms to IEEE 802.3i–1990 (10Base-T)
On-chip transmit and receive filters
Automatic AUI/Twisted Pair selection (ML2652 only)
Power down mode
Pin selectable controller interface-(CS0 – CS2)
Automatic polarity correction
Pin selectable receive squelch levels
Status pins for: link detect, receive &
transmit activity, collision, jabber, AUI selection
Single supply 5V ±5%
DETECT
JABDIS
Intel 82586, 82596
NSC DP8390
Seeq 8003, 8005
AMD 7990
JAB
WAVEFORM
GEN & LPF
RECEIVER
PULSE
LINK
XMT
ML2652/ML2653
DRIVEN XMT
CURRENT
OUTPUT
RECEIVE
DRIVER
AUI
LPF
AUI/TP
DO+
DO–
RTX
Rx+
DI+
Tx+
Rx–
RSL
CI+
DI–
Tx–
CI–
July 2000
1

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ML2653CQ Summary of contents

Page 1

GENERAL DESCRIPTION The ML2652, 10BASE-T Physical Interface Chip complete physical interface for twisted pair and AUI Ethernet applications. It combines a 10BASE-T MAU, Manchester Encoder/Decoder, and Twisted Pair Interface filters in one monolithic IC. A complete DTE interface ...

Page 2

ML2652/ML2653 PIN CONNECTIONS ML2653 28-Pin PLCC (Q28 Tx– CLK 7 LPBK 8 Rx+ 9 Rx– CLK LPBK NC ...

Page 3

ML2653 BLOCK DIAGRAM CS0 CS1 CS2 FD TxC TxE TxD CONTROLLER COL INTERFACE LPBK RxC RxE RxD CLK OSC RPOL PIN DESCRIPTION NAME FUNCTION V Positive supply. +5V CC GND Ground. 0 volts. All inputs and outputs referenced to this ...

Page 4

ML2652/ML2653 PIN DESCRIPTION (Continued) NAME FUNCTION RxD Receive data output. Digital output which contains receive data sent to the controller. RxE Receive data valid. Digital output to the controller that indicates when the receive data (RxD) is valid. LPBK Local ...

Page 5

ELECTRICAL CHARACTERISTICS Unless otherwise specified T = 0°C to 70° SYMBOL PARAMETER VIL Digital input low voltage VIH Digital input high voltage IIL Digital input low current IIH Digital input high current CIN Digital input capacitance VOL Digital ...

Page 6

ML2652/ML2653 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER RRI Receive input resistance RCI Receive input capacitance RSON Receive squelch on level (Differential zero to peak voltage) RSOF Receive squelch off level (Differental zero to peak voltage) DOV DO± differential output voltage DOVI DO± ...

Page 7

ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER t9 Start of Idle Pulse Width t10 SOI pulse width to within 40mV of final value t11 Transmit output jitter t12 Transmit output rise and fall time TxE to XMT assert t13 XMT blinker pulse period ...

Page 8

ML2652/ML2653 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER t34 Minimum SOI pulse width required for receive detection t40 Jabber activation delay- TxE assert to Tx± disable Tx± disable to JAB assert t41 t42 Jabber reset time – TxE deassert to JAB deassert t43 ...

Page 9

ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER t75 Transmission start during reception to COL assert t76 Transmission start during reception to CLS assert t77 CI± period t78 CI± duty cycle t79 First valid negative CI± data transition to COL assert t80 First valid ...

Page 10

ML2652/ML2653 TIMING DIAGRAMS (Continued) TxC TxE TxD (NRZ) COL 1 MANCH. DATA XMT TWISTED LINK PAIR PULSE RCV TWISTED PAIR 1 0 RxC RxE RxD (NRZ ...

Page 11

TIMING DIAGRAMS (Continued) TxC TxE TxD B0 Tx XMT 1 Rx RxE (1) RxC RxC ( RxD RCV NOTE: 1. RxC IS NOT CONTINUOUS DURING IDLE 2. RxC IS CONTINUOUS DURING IDLE ...

Page 12

ML2652/ML2653 TIMING DIAGRAMS (Continued RxE Rx Rx RxC ( (2) RxC t 30 RxD NOTE: 1. RxC IS NOT CONTINUOUS DURING IDLE — 8 EXTRA CLOCKS ADDED FOR CS2 – 000 2. RxC ...

Page 13

TIMING DIAGRAMS (Continued) TRANSMIT Tx RECEIVE Rx LTP INTERFACE SELECT AUI/TP AUISEL TxC TxE TxD COL Figure 7. Link Pulse Timing Figure 8. SQE Test Timing ...

Page 14

ML2652/ML2653 TIMING DIAGRAMS (Continued) TxD Tx RxD COL t 71 CLS Figure 9. Collision Timing Reception During Transmission Rx TxE TxD Tx COL CLS Figure 10. Collision Timing Transmission During Reception 14 DATA MAY BE INVALID t ...

Page 15

TIMING DIAGRAMS (Continued) CI COL CLS APPLICATION CIRCUIT — ML2652 ETHERNET CONTROLLER (SEE TABLE 1) SEEQ 8003 SEEQ 8005 NSC DP8390 +5V AMD AM7990 5.1K INTEL 82586 5.1K +5V INTEL 82596 510 510 ...

Page 16

ML2652/ML2653 FUNCTIONAL DESCRIPTION GENERAL The ML2652 and ML2653 are composed of a transmitter section, receive section and some miscellaneous functions. The transmit section consists of the manchester encoder, AUI, jabber detect, link pulse generator, start of idle (SOI) pulse generator, ...

Page 17

FUNCTIONAL DESCRIPTION Then the NRZ data is encoded by the manchester encoder as shown in transmit timing diagram in Figure 1. The manchester encoded data then goes to either the AUI or twisted pair interface. The selection of the appropriate ...

Page 18

ML2652/ML2653 FUNCTIONAL DESCRIPTION The receive squelch circuit determines when data on incoming Rx+, Rx– is valid. The receive squelch is considered “on” when the data is deemed to be invalid, and the receive squelch is considered “off” when data is ...

Page 19

FUNCTIONAL DESCRIPTION 2–7ms apart in the link fail state, the device ignores the link pulses and resets the number of consecutive link pulses to zero. After the link pulse fail state is exited, transmission and reception can be resumed. Link ...

Page 20

ML2652/ML2653 FUNCTIONAL DESCRIPTION outputs can be coupled to an external MAU with either capacitors or a transformer. The ML2652 meets all AUI transmitter specifications outlined in IEEE 802.3–1988 Section 7. DI+ and DI– are inputs from the external MAU which ...

Page 21

FUNCTIONAL DESCRIPTION The controller interface consists of seven pins. TxC, TxD, and TxE are the transmit clock output, transmit data input, and transmit data enable input, respectively. RxC, RxD, and RxE are the receive clock output, receive data output, and ...

Page 22

ML2652/ML2653 PHYSICAL DIMENSIONS 0.685 - 0.695 (17.40 - 17.65) 0.650 - 0.656 (16.51 - 16.66) 1 PIN 1 ID 0.042 - 0.048 (1.07 - 1.22 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 ...

Page 23

... BSC) ORDERING INFORMATION PART NUMBER ML2652CQ ML2653CQ ML2653CH © Micro Linear 1998 registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; ...

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