74HC164

Manufacturer Part Number74HC164
ManufacturerNXP Semiconductors
74HC164 datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Page 1/24

Download datasheet (132Kb)Embed
Next
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Rev. 03 — 4 April 2005
1. General description
The 74HC164; 74HCT164 are high-speed Si-gate CMOS devices and are pin compatible
with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC164; 74HCT164 are 8-bit edge-triggered shift registers with serial data entry
and an output from each of the eight stages. Data is entered serially through one of two
inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry
through the other input. Both inputs must be connected together or an unused input must
be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input
and enters into Q0, which is the logical AND of the two data inputs (DSA and DSB) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all other inputs and clears the
register asynchronously, forcing all outputs LOW.
2. Features
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
3. Quick reference data
Table 1:
GND = 0 V; T
Symbol
Type 74HC164
t
, t
PHL
PLH
Quick reference data
= 25 C; t
= t
= 6 ns.
amb
r
f
Parameter
propagation delay
CP to Qn
MR to Qn
Product data sheet
Conditions
Min
Typ
C
= 15 pF;
-
12
L
V
= 5 V
CC
C
= 15 pF;
-
11
L
V
= 5 V
CC
Max
Unit
-
ns
-
ns

74HC164 Summary of contents