CY7C63001A Cypress Semiconductor Corporation., CY7C63001A Datasheet
CY7C63001A
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CY7C63001A Summary of contents
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... SOIC, and 24-pin QSOP packages • Industry-standard programmer support R/C EXT RAM 8-bit NOW™ 128-Byte Timer USB PORT 0 Engine D+,D– P0.0–P0 • 3901 North First Street • CY7C63001A CY7C63101A PORT 1 P1.0–P1.7 , San Jose CA 95134 • 408-943-2600 Revised October 5, 2004 [+] Feedback ...
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... Port 1 bit Port 1 bit Port 1 bit Port 1 bit Port 1 bit Ceramic resonator Ceramic resonator out CY7C63001A CY7C63101A CY7C63101A DIE (-SC) packages. The 26-GPIO Description ...
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... Ground Description 6.1.1 Program Memory Organization The CY7C63001A and CY7C63101A each offer 4 Kbytes of EPROM. The program memory space is divided into two functional groups: interrupt vectors and program code. The interrupt vectors occupy the first 16 bytes of the program space. Each vector is 2 bytes long. After a reset, the Program Counter points to location zero of the program space ...
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... On-chip program Memory 0x07FF 2K ROM (CY7C63000A, CY7C63100A) 0x0FFF 4K ROM (CY7C63001A, CY7C63101A) Figure 6-1. Program Memory Space The DSP pre-decrements by one whenever a PUSH instruction is executed and it increments by one after a POP instruction is used. The default value of the DSP after reset is 0x00, which would cause the first PUSH to write into USB FIFO space for Endpoint 1 ...
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... Free-running timer W Input sink current control for Port 0 pins. There is one Isink register for each pin. Address of the Isink register for pin 0 is located at 0x30 and the register address for pin 7 is located at 0x37. CY7C63001A CY7C63101A Page Figure 6-8 Figure 6-9 Figure 6-17 Figure 6-18 ...
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... POR to conserve power (the clock oscillator, the timers, and the interrupt logic are turned off in suspend mode). After POR, only a non-idle USB Bus state terminates the suspend mode. The microcontroller then begins execution from ROM address 0x00. CY7C63001A CY7C63101A Page Figure 6-13 Figure 6-3 ...
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... R- C timing circuit. The format of the Cext register is shown in Figure 6-5. Reading the register returns the value of the Cext pin. During a reset, the Cext pin is HIGH Reserved Reserved Reserved CY7C63001A CY7C63101A b1 b0 Reserved CEXT R Page [+] Feedback ...
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... Figures 6-8 and 6-9 for the formats of the data registers. In addition to supporting general input/output functions, each I/O line can trigger an interrupt to the microcontroller. Please refer to the interrupt section for more details P0.4 P0.3 R/W R P1.4 P1.3 R/W R CY7C63001A CY7C63101A T.2 T.1 T 1.024-ms interrupt 128- s interrupt m 0 Resonator Clock/6 ...
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... GPIO interrupt “0” selects a HIGH to LOW transition while a “1” selects a LOW to HIGH transition PULL0.4 PULL0 CY7C63001A CY7C63101A currents GPIO Pin Interrupt Polarity High to Low Low to High ...
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... Figure 6-15 illustrates the format of the Global Interrupt Enable Register EP1IE EP0IE R/W R generates an interrupt request enabled in the Global Interrupt Enable Register. The highest priority interrupt request is serviced following the execution of the current instruction. CY7C63001A CY7C63101A PULL1.2 PULL1.1 PULL1 ...
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... IRQ Enable [1] 1-ms CLR CLK 1-ms IRQ End P0 CLR End P0 IRQ End P1 CLR End P1 IRQ GPIO CLR CLR GPIO IRQ D Q Enable [6] CLK Wake-up CLR CLR Wake-up IRQ D Q Enable [7] CLK CY7C63001A CY7C63101A Function IRQ Interrupt Vector Interrupt Priority Encoder Page [+] Feedback ...
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... USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. When a GPIO interrupt is serviced, the ISR must poll the ports to determine which pin caused the interrupt. CY7C63001A CY7C63101A IE0 ...
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... The host generates control reads to the USB Controller to request the Configuration and Report descriptors. 10.The USB Controller retrieves the descriptors from its program space and returns the data to the host over the USB. 11.Enumeration is complete after the host has received all the descriptors. CY7C63001A CY7C63101A b1 b0 ADR1 ADR0 R/W ...
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... No No OUT Error No No OUT Valid No No OUT Error No No OUT Status No Yes OUT N/Status No Yes OUT Error No Yes CY7C63001A CY7C63101A OUT SETUP R/W R/W R Section 6.9.2.2. The ‘StatusOuts’ USB Engine Response Count Update Interrupt Reply Yes Yes ACK Yes ...
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... Endpoint 0. A valid Status stage OUT contains a DATA1 packet with 0 bytes of data. If the Statu- sOuts bit is set, the USB engine responds to a valid Status stage OUT with an ACK, and any other OUT with a STALL. CY7C63001A CY7C63101A b1 b0 ...
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... In addition to the differ- ential receiver, there is a single-ended receiver for each of the two data lines. The single-ended receivers have a switching threshold between 0.8V and 2.0V (TTL inputs). CY7C63001A CY7C63101A Page [+] Feedback ...
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... Port1 VSS D+ VPP D– CEXT VCC XTALIN XTALOUT ± 7.5kW 1% 0.1 F 6-MHz Resonator +3.3V Port0 Port0 Switches, Devices, Etc. ± Port1 Port1 1 D– PP CEXT V CC XTALIN XTALOUT +4.35V (min.) 0.1 F 6-MHz Resonator CY7C63001A CY7C63101A 2.6 2.8 3.0 3.2 +4.35V (min) 4.7 F 3.3V Reg 0 4.7 F Page [+] Feedback ...
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... AND [expr],A 5 AND [X+expr],A 7 XOR [expr],A 8 XOR [X+expr],A 4 IOWX [X+expr] 5 CPL 6 ASL 4 ASR 5 RLC 13 RRC 4 RET JNC 5 JACC 5 INDEX CY7C63001A CY7C63101A operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index ...
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... Vout = 2.0V DC, Port 0 only Vout = 2.0V DC, Port 0 only Vout = 2.0V DC, Port 1 only Vout = 2.0V DC, Port 1 only Vout = 0.4V DC, Port 1 only Vout = 2.0V DC, Port [11] Port 0 or Port 1 [12] Vout = 2.0V Full scale transition Summed over all Port 1 bits CY7C63001A CY7C63101A +0.5V CC ................................................ > 200 mA = 4.0 to 5.25V CC Min. Max. Unit 25 mA ...
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... See Notes 5, 6, and 9 See Notes 5, 6, and See Note 5 Ave. Bit Rate (1.5 Mb/s ± 1.5%) [10] To Next Transition, Figure 9-3 For Paired Transitions, Figure 9-3 [10] [10] Accepts as EOP To next transition, Figure 9-5 To paired transition, Figure 9-5 CY7C63001A CY7C63101A = 4.0 to 5.25V (continued) CC Min. Max. Unit 25 mW 45% 65 12% V ...
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... JR1 Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD JR2 Figure 9-3. Receiver Jitter Tolerance Crossover Point Extended SE0 Skew + T PERIOD DEOP CY7C63001A CY7C63101A f 10% T JR2 Source EOP Width: T EOPT Receiver EOP Width EOPR1 EOPR2 Page [+] Feedback ...
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... Ordering Information EPROM Number of Ordering Code Size CY7C63001A-PC 4KB CY7C63001A-PXC 4KB CY7C63001A-SC 4KB CY7C63001A-SXC 4KB CY7C63101A-QC 4KB CY7C63101A-QXC 4KB CY7C63001A-XC 4KB CY7C63001A-XWC 4KB 11.0 Package Diagrams Document #: 38-08026 Rev. *A Crossover Points Consecutive Transitions PERIOD xJR1 Paired Transitions PERIOD xJR2 Figure 9-5. Differential Data Jitter ...
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... Package Diagrams (continued) Document #: 38-08026 Rev. *A 24-Lead Quarter Size Outline Q13 20-Lead (300-Mil) Molded SOIC S5 CY7C63001A CY7C63101A 51-85055-*B 51-85024-*B Page [+] Feedback ...
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... Table 11-1 below shows the die pad coordinates for the CY7C63001A-XC and CY7C63001A-XWC. The center location of each bond pad is relative to the bottom left corner of the die which has coordinate (0,0). Table 11-1. CY7C63001A-XC Probe Pad Coordinates in Microns ((0,0) to Bond Pad Centers) Pin X Pad # Name ...
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... Document History Page Document Title: CY7C63001A, CY7C63101A Universal Serial Bus Microcontroller Document Number: 38-08026 Orig. of REV. ECN NO. Issue Date Change ** 116223 06/12/02 *A 276070 See ECN Document #: 38-08026 Rev. *A Description of Change DSG Change from Spec number: 38-00662 to 38-08026 BON Added die form and bond pad information. Added lead-free packages. ...