MC14077B ON Semiconductor, MC14077B Datasheet

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MC14077B

Manufacturer Part Number
MC14077B
Description
Manufacturer
ON Semiconductor
Datasheet

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MC14070B, MC14077B
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
exclusive NOR gate are constructed with MOS P−channel and
N−channel enhancement mode devices in a single monolithic
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.
Features
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
Symbol
V
I
The MC14070B quad exclusive OR gate and the MC14077B quad
in
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Schottky TTL Load Over the Rated Temperature Range
in
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Double Diode Protection on All Inputs
MC14070B − Replacement for CD4030B and CD4070B Types
MC14077B − Replacement for CD4077B Type
Pb−Free Packages are Available
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
A
D
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
SS
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
xx
A
WL, L
YY, Y
WW, W
G
ORDERING INFORMATION
http://onsemi.com
CASE 751A
SOEIAJ−14
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
CASE 646
CASE 965
P SUFFIX
D SUFFIX
F SUFFIX
PDIP−14
SOIC−14
Publication Order Number:
14
1
14
14
1
1
MC140xxBCP
DIAGRAMS
AWLYYWWG
MARKING
MC140xxB
AWLYWW
MC14070B/D
ALYWG
140xxBG

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MC14077B Summary of contents

Page 1

... MC14070B, MC14077B CMOS SSI Quad Exclusive “OR” and “NOR” Gates The MC14070B quad exclusive OR gate and the MC14077B quad exclusive NOR gate are constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired ...

Page 2

... V SS (BOTH DEVICES *Inverted output on MC14077B only. Figure 1. Power Dissipation Test Circuit and Waveform V DD PULSE * GENERATOR # *Inverted output on MC14077B only. #Connect unused input to V for MC14070B Figure 2. Switching Time Test Circuit and Waveforms http://onsemi ...

Page 3

... MC14070BDR2 MC14070BDR2G MC14070BFEL MC14070BFELG MC14077BCP MC14077BCPG MC14077BD MC14077BDG MC14077BDR2 MC14077BDR2G MC14077BFEL MC14077BFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Package PDIP−14 PDIP−14 (Pb−Free) SOIC−14 SOIC− ...

Page 4

ELECTRICAL CHARACTERISTICS Î Î Î Î Î ...

Page 5

−T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

Page 6

... K D SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...

Page 7

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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