STA529Q STMicroelectronics, STA529Q Datasheet
STA529Q
Specifications of STA529Q
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STA529Q Summary of contents
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... CC – with 32-Ω headphones – with 16-Ω headphones – 720 mW with 8-Ω speakers – 1.1 W with 4-Ω speakers Table 1. Device summary Order code Operating temp. range STA529Q - °C STA529 - °C April 2010 Applications Portable devices – Laptops – Digital cameras – Microless applications ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA529 8 Driver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STA529 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction 1 Introduction The STA529 is a digital stereo class-D audio amplifier. It includes an audio DSP proprietary high-efficiency class-D driver and CMOS power output stage intended for high-efficiency digital-to-power-audio conversion for portable applications. The STA529 ...
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STA529 2 Connection diagrams and pin descriptions This section includes connection diagrams and pin descriptions for the following packages: TFBGA48 VFQFPN52. 2.1 TFBGA48 package Figure 2. Connection diagram for TFBGA48 (bottom view) Table 2. Pin description for TFBGA48 Pin Name ...
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Connection diagrams and pin descriptions Table 2. Pin description for TFBGA48 (continued) Pin Name B5 OUT1B B6 OUT1A B7 MUTE B8 GND C1 VDDIO C2 VCC33 CLKOUT / C7 PWM2B C8 VDD D1 XTI D2 XTO D7 RST_N D8 VCM ...
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STA529 Table 2. Pin description for TFBGA48 (continued) Pin Name GNDPLL H4 VDDPLL H5 LRCLKI H6 BICLKI H7 INL H8 INR 2.2 VFQFPN52 package Figure 3. Connection diagram for VFQFPN52 (bottom view) Table 3. Pin description for ...
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Connection diagrams and pin descriptions Table 3. Pin description for VFQFPN52 (continued) Pin Name 8 AGND 9 VCM 10 RST_N CLKOUT / 11 PWM2B 12 GND1 13 VDD1 14 MUTE 15 VCC1A 16 OUT1A 17 GND1A 18 GND1B 19 OUT1B ...
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STA529 Table 3. Pin description for VFQFPN52 (continued) Pin Name 39 XTO 40 FILT 41 GNDPLL 42 VDDPLL 43 GND2 44 VDD2 45 SDATAI SDATAO / 46 PWM2A 47 LRCLKI LRCLKO / 48 PWM1B 49 GNDIO2 50 VDDIO2 51 BICLKI ...
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Electrical and thermal specifications 3 Electrical and thermal specifications 3.1 Thermal data Table 4. Thermal data Device TFBGA48 Thermal resistance junction to ambient VFQFPN52 Thermal resistance junction to ambient 3.2 Absolute maximum ratings Table 5. Absolute maximum ratings Pin/symbol VDD ...
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STA529 3.3 Recommended operating conditions Table 6. Recommended operating conditions Symbol VDD VDD1 Digital supply voltage VDD2 AVDD ADC supply voltage VDDPLL PLL analog supply voltage VCC1A VCC1B Power stage supply voltage VCC2A VCC2B Pre-driver supply VCC33 (must be at ...
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Electrical and thermal specifications 3.4 Electrical characteristics The electrical specifications in recommended conditions listed in (fs kHz, input frequency = 1 kHz, and R Table 7. Electrical characteristics Symbol Eff Output power efficiency Output stage N/PMOS on- R ...
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STA529 The following tables give the output power for 1% and 10% THD levels for headphones and speakers. Table 8. Load power at 1% distortion in headphone mode Load (Ω Table 9. Load power at 10% distortion in ...
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Input clock 4 Input clock 4.1 SELCLK33 In STA529 the oversampling clock comes from MCLK33 or from pin XTI. The selection is done by applying the appropriate voltage to pin SELCLK33. If SELCLK33 is logical 1 then MCLK33 is selected, ...
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STA529 5 Digital processing The STA529 processor block is a digital block providing two channels of audio processing and channel-mapping capability. 5.1 Signal processing flow stereo ADC data can be selected. The I ADC sampling frequency ...
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Digital processing 5.3 Volume control and gain The volume control structure of the STA529 consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes ...
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STA529 6 PLL Figure 5 shows the main components of the PLL. Figure 5. PLL block diagram CLKIN IDF INFOUT REFOUT STRB STRB_BYPASS FRAC_CTRL DITHER_DISABLE 6.1 Functional description Phase/frequency detector The phase/frequency detector (PFD) compares the phase difference between the ...
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PLL Input frequency divider This frequency divider divides the PLL input clock CLKIN by a factor called the input division factor (IDF) to generate the PFD input frequency INFIN. Loop frequency divider This frequency divider is present within the PLL ...
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STA529 6.2 Configuration examples The STA529 PLL can be configured in two ways: default startup configuration direct PLL programming The default startup configuration reads the device defaults. With this configuration not necessary to program the PLL dividers directly ...
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PLL When automatic settings are not used, the PLL must be configured to generate an internal frequency fs, where fs is the frequency of pin LRCLKI. Values for N are given in PHI Table 15. ...
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STA529 7 ADC 7.1 ADC performance values Table 16. Programmable gain performance Dynamic range 1 kHz, A-weighted (3.3 V supply) Dynamic range 1 kHz, A-weighted (1.8 V supply) SNDR 1 kHz, A-weighted (3.3 V supply) SNDR 1 kHz, A-weighted (1.8 ...
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ADC 7.2.1 Digital filter characteristics Table 17. Digital filter characteristics Parameter Pass band Pass-band ripple: Fs mode Fs_by_2 mode Fs_by_4 mode Stop-band attenuation: Fs mode Fs_by_2 mode Fs_by_4 mode Group delay: Fs mode Fs_by_2 mode Fs_by_4 mode 7.2.2 High-pass filter ...
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STA529 7.3 Applications scheme Figure 7. Diagram of input coupling and supply decoupling AC coupled DC coupled AC coupled DC coupled supply VSSA R1 VSSA 7.4 Configuration examples The ADC sampling frequency can be selected from ...
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Driver configuration 8 Driver configuration A driver configuration is available that allows PWM commands to be used on an external power device. For this purpose, the output serial audio interface is disabled and the respective pins have an alternative name ...
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STA529 9 Serial audio interface The serial-to-parallel interface and the parallel-to-serial interface can have different sampling rates. The following terms are used in this section: BICLK active edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO always change synchronously with BITCLK active edges. ...
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Serial audio interface 9.2 Slave mode In this mode, pins BICLKI/O and pins LRCLKI/O are configured as inputs. Figure 9. Slave mode BICLKI/ BICLKO LRCLKI/ LRCLKO SDATAI SDATAO Table 21. Slave mode Symbol t BICLK cycle time BCY t BICLK ...
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STA529 9.3 Serial formats Different audio formats are supported in both master and slave modes. Clock and data configurations can be customized to match most of the serial audio protocols available on the market. Data length can be customized to ...
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Serial audio interface 9.3.1 DSP Figure 12. DSP LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 2 9.3 Figure 13 LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 30/55 Left ...
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STA529 9.3.3 PCM/IF (non-delayed mode) MSB first 16-bit data Figure 14. PCM/IF (non delayed mode) LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI SDATAO 9.3.4 PCM/IF (delayed mode) MSB first 16-bit data Figure 15. PCM/IF (delayed mode) LRCLKI/ LRCLKO BICLKI/ ...
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I C interface interface 10.1 Data transition and change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify ...
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STA529 10.6 Write operation Following the start condition the master sends a device select code with the R/W bit set to 0. The STA529 acknowledges this and then writes to the byte of the internal address. After receiving the internal ...
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I C interface 10.7.4 Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA529. The master acknowledges each data byte read and then generates ...
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STA529 11 Registers This section describes the set-up register used in the device. 11.1 Summary Table 22. Register summary Address Name Bit 7 0x00 FFXCFG0 MUTE 0x01 FFXCFG1 L1_R2 0x02 MVOL 0x03 LVOL 0x04 RVOL 0x05 TTF0 0x06 TTF1 0x07 ...
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Registers Table 22. Register summary (continued) Address Name Bit 7 0x23 FFXST 0x28 BISTRUN 0x29 BISTST0 0x2A BISTST1 0x2B BISTST2 0x2D PWMINT1 0x2E PWMINT2 POWER 0x32 POWST DOWN All other registers not mentioned here are reserved and must not be ...
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STA529 FFXCFG1 Bit 7 Bit 6 MUTE_ON_ L1_R2 INVALID Address: 0x01 Type: R/W Buffer: No Reset: 0xF8 Description: 7 L1_R2: channel mapping: 0: right channel is mapped to output channel 1 and left channel is mapped to output channel 2 ...
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Registers LVOL Bit 7 Bit 6 Address: 0x03 Type: R/W Buffer: No Reset: 0x48 Description: 7:0 SET_VOL_LEFT[7:0]: left channel volume control: Left channel volume control (from + -91 0.5-dB steps) Default value (0x48) corresponds to 0 ...
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STA529 TTF1 Bit 7 Bit 6 Address: 0x06 Type: R/W Buffer: No Reset: 0x02 Description: 7:0 LSBs of TIM_TS_FAULT[15:0]: time in which power is held in tristate mode after a fault signal: Time is TIM_TS_FAULT * 83.33 µs. Default value ...
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Registers S2PCFG0 Bit 7 Bit 6 BICLK_STRB LRCLK_LEFT SHARE_BILR Address: 0x0A Type: R/W Buffer: No Reset: 0xD2 Description: 7 BICLK_STRB: 0: bit clock strobe edge is falling edge, bit clock active edge is rising edge 1: bit clock strobe edge ...
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STA529 S2PCFG1 Bit 7 Bit 6 PDATA_LENGTH[1:0] Address: 0x0B Type: R/W Buffer: No Reset: 0x91 Description: 7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: Length is (N+ bit Default (10 bit 5:4 BICLK_OS[1:0]: bit clock oversampling: Value is ...
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Registers P2SCFG0 Bit 7 Bit 6 BICLK_ STRB LRCLK_LEFT SDATAO_ACT Address: 0x0C Type: R/W Buffer: No Reset: 0xD3 Description: 7 BICLK_STRB: defines the bit clock edges: 0: strobe is falling edge, active edge is rising 1: strobe is rising edge, ...
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STA529 P2SCFG1 Bit 7 Bit 6 PDATA_LENGTH[1:0] Address: 0x0D Type: R/W Buffer: No Reset: 0x91 Description: 7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: Length is (PDATA_LENGTH+ bit Default (10 bits 5:4 BICLK_OS[1:0]: bit clock oversampling: Value is ...
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Registers 6 FRAC_CTRL: 0: default 1: PLL fractional-frequency synthesis is enabled 5:4 DITHER_DISABLE[1:0]: 00: default 1x: disables rectangular phase frequency divider dither input to fractional control x1: disables triangular Phase Frequency Divider dither input to Fractional Control The mentioned blocks ...
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STA529 PLLCFG3 Bit 7 Bit 6 STRB STRB_BYPASS Address: 0x17 Type: R/W Buffer: No Reset: 0x00 Description: 7 STRB: asynchronous strobe input to the fractional controller: 0: default 6 STRB_BYPASS: standby bypass: 0: STRB signal is not bypassed (default) 1: ...
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Registers 4 PFE1A: 0: default 1: POP-free resistances are connected to output 1A 3 PFE1B: 0: default 1: POP-free resistances are connected to output 1B 2 PFE2A: 0: default 1: POP-free resistances are connected to output 2A 1 PFE2B: 0: ...
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STA529 ADCCFG Bit 7 Bit 6 PGA[2:0] Address: 0x1E Type: RO Buffer: No Reset: Undefined Description: 7:5 PGA[2:0]: gain selection bits for the ADC programmable gain amplifier: 000: default Values are from steps ...
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Registers MISC Bit 7 Bit 6 OSC_DIS P2P_FS_RANGE[2:0] Address: 0x20 Type: R/W Buffer: No Reset: 0x20 Description: 7 OSC_DIS: enable/disable crystal oscillator: 0: default 1: disabled 6:4 P2P_FS_RANGE[2:0]: FFX audio frequency range: 000: very low ( ...
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STA529 Description: 7:3 Reserved 2 INVALID_INP_FBK: invalid input status: 1: invalid input sent to FFX 1 MUTE_INT_FBK: FFX mute status 1: FFX is in mute state 0 Reserved PWMINT1 Bit 7 Bit 6 Address: 0x2D Type: R/W Buffer: No Reset: ...
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Registers POWST Bit 7 Bit 6 POW_ POW_ POW_FAULT1A POWERDOWN TRISTATE Address: 0x32 Type: RO Buffer: No Reset: Undefined Description: 7 POW_POWERDOWN: power-down bridge: 0: not in power-down state 1: power-down state 6 POW_TRISTATE: 1: power bridge is in tristate ...
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STA529 12 Package mechanical data This section contains packaging information for the following packages: TFBGA48 VFQFPN52 In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ...
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Package mechanical data Table 23. Package dimensions (TFBGA48) Reference ddd eee fff 52/55 Dimensions in mm Min - - 0. 0.785 - 0. 0.25 ...
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STA529 12.2 Package VFQFPN52 Figure 19. Package outline (VFQFPN52 Table 24. Package dimensions (VFQFPN52) Reference ddd ) Dimensions in mm Min 0.800 0.900 - 0.020 - 0.650 - 0.250 ...
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Revision history 13 Revision history Table 25. Document revision history Date 25-Jan-2007 09-Apr-2010 54/55 Revision 1 Initial release. 2 Complete update and change in presentation Doc ID 13095 Rev 2 STA529 Changes ...
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... STA529 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...