AD73360L Analog Devices, AD73360L Datasheet
AD73360L
Specifications of AD73360L
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AD73360L Summary of contents
Page 1
... The AD73360L is particularly suitable for industrial power metering as each channel samples synchronously, ensuring that there is no (phase) delay between the conversions. The AD73360L also features low group delay conversions on all channels. An on-chip reference voltage is included with a nominal value of 1 ...
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... LOGIC INPUTS V , Input High Voltage INH V , Input Low Voltage INL I , Input Current Input Capacitance IN 1 (AVDD = 2 3.6 V; DVDD = 2 3.6 V; DGND = AGND = 8.192 MHz kHz; T SCLK S AD73360LA Min Typ Max Unit 1.08 1.2 1. ppm/°C Ω 130 1.08 1.2 1. kΩ 100 pF 1 ...
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... Unit ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns max ns max ns max AD73360L Test Conditions/Comments |IOUT| ≤ 100 µA |IOUT| ≤ 100 µA See Table unless other- A MlN MAX Description See Figure 1. MCLK Period MCLK Width High MCLK Width Low See Figures 3 and 4 ...
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... AD73360L 100 OUTPUT PIN C L 15pF 100 MCLK SCLK SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). SE (I) THREE- STATE SCLK (O) SDIFS (I) SDI ( THREE- STATE SDOFS (O) THREE- STATE SDO (O) 80 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73360L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. SOIC, θ ...
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... SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low. 17 SDI Serial Data Input of the AD73360L. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low SPORT Enable ...
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... BW Bandwidth. CRx A Control Register where placeholder for an alphabetic character (A–E). There are eight read/write control registers on the AD73360L— designated CRA through CRE. CRx:n A bit position, where placeholder for a numeric character (0–7), within a control regis- ter; where placeholder for an alphabetic character (A– ...
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... Sigma-delta converters employ a technique known as over- sampling, where the sampling rate is many times the highest frequency of interest. In the case of the AD73360L, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The main effect of oversampling is that the quantization noise is spread over a very wide bandwidth (Figure 6a) ...
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... Figure 7 shows the various stages of filtering that are employed in a typical AD73360L application. In Figure 7a we see the trans- fer function of the external analog antialias filter. Even though single RC pole, its cutoff frequency is sufficiently far away from the initial sampling frequency (DMCLK/8) that it takes care of any signals that could be aliased by the sampling frequency ...
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... In this mode, control information can be written to or read from the AD73360L. In Data Mode (CRA:0 = 1), any infor- mation that is sent to the device is ignored, while the encoder section (ADC) data is read from the device. In this mode, only ADC data is read from the device ...
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... Bits 10–8 Register Address This 3-bit field is used to select one of the eight control registers on the AD73360L. Bits 7–0 Register Data This 8-bit field holds the data that written to the selected register provided the device address field is zero ...
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... AD73360L CONTROL REGISTER Bit Name 0 DR0 1 DR1 2 SCD0 3 SCD1 4 MCD0 5 MCD1 6 MCD2 7 CEE CONTROL REGISTER C 7 RES Bit Name 0 GPU 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 PUREF Reserved CONTROL REGISTER D 7 PUI2 Bit Name 0 I1GS0 1 I1GS1 2 I1GS2 3 PUI1 4 I2GS0 5 I2GS1 ...
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... CH5 Description CH1 Channel 1 Select CH2 Channel 2 Select CH3 Channel 3 Select CH4 Channel 4 Select CH5 Channel 5 Select CH6 Channel 6 Select RMOD Reset Analog Modulator SEEN Enable Single-Ended Input Mode AD73360L I3GS2 I3GS1 I3GS0 I5GS2 I5GS1 I5GS0 ...
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... REGISTER BIT DESCRIPTIONS Control Register A CRA:0 Data/Program Mode. This bit controls the operating mode of the AD73360L. If CRA this bit places the part in Program Mode. If CRA this bit places the part in Data Mode. CRA:1 Mixed Mode. If this bit the operating mode is determined by CRA:0. If this bit the part operates in Mixed Mode ...
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... Setting this bit to 0 will select Noninverted (Normal) Mode for all channels. SPORT Register Maps There are eight control registers for the AD73360L, each eight bits wide. Table III shows the control register map for the AD73360L. The first two control registers, CRA and CRB, are reserved for controlling the SPORT ...
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... The AD73360L inputs and outputs data in a Time Division Multiplexing (TDM) format. When data is being read from the AD73360L each channel has a fixed time slot in which its data is transmitted channel is not powered up, no data is trans- mitted during the allocated time slot and the SDO line will be three-stated ...
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... The serial clock (SCLK output from the AD73360L and is used to define the serial transfer rate to the DSP’s Tx and Rx ports. Two primary configurations can be used: the first is shown in Figure 11 where the DSP’ ...
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... DSP in this configuration it is advisable to preload the Tx register with the first control word to be sent before the AD73360L is taken out of reset. This ensures that this word will be transmitted to coincide with the first out- put word from the device(s). ...
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... CHANNEL 1 ADC SAMPLE WORD SDIFS SDI CONTROL WORD SE SCLK SDOFS SDO CHANNEL 1 ADC SAMPLE WORD SDIFS SDI DON'T CARE UNDEFINED DATA CONTROL WORD READ RESULT 0x7FFF OR CONTROL WORD CHANNEL 6 ADC SAMPLE WORD CONTROL WORD CHANNEL 6 ADC SAMPLE WORD DON'T CARE AD73360L ...
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... AD73360L Cascade Operation The AD73360L has been designed to support two devices in a cascade connected to a single serial port (see Figure 17). The SPORT interface protocol has been designed so that device addressing is built into the packet of information sent to the device. This allows the cascade to be formed with no extra hard- ware overhead for control signals or addressing ...
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... MCLK CLK RESET PERFORMANCE As the AD73360L is designed to provide high-performance, low-cost conversion important to understand the means by which this high performance can be achieved in a typical appli- cation. This section will, by means of spectral graphs, outline the typical performance of the device and highlight some of the ...
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... AD73360L to be used with either a single-ended or differential signal. The applied signal can also be inverted internally by the AD73360L if required. The analog input signal to the AD73360L can be dc-coupled, provided that the dc bias level of the input signal is the same as the internal reference level (REFOUT). Figure 24 shows the recommended differential input circuit for the AD73360L ...
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... Digital Interface As there are a number of variations of sample rate and clock speeds that can be used with the AD73360L in a particular appli- cation important to select the best combination to achieve the desired performance. High-speed serial clocks will read the data from the AD73360L in a shorter time, giving more time for processing at the expense of injecting some digital noise into the circuit ...
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... The AD73360L, with its six-channel simulta- neous sampling capability, is ideally suited for use in vector motor control applications. A block diagram of a vector motor control application using the AD73360L is shown in Figure 30. The position of the field is derived by determining the current in each phase of the motor ...
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... DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS. APPENDIX A 8 kHz (with a master clock of 16.384 MHz). In Step 2, the con- trol word in the DSP’s Tx register will cause all the AD73360Ls channels to power up. This data is received by the AD73360L with the next frame sync pulse. An invalid ADC word is also received at the DSP’ ...
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... In Step 2, the DSP instructs the AD73360L to power up channels 1 and 2 and sets the gain of each. No data is read from the AD73360L at this point. Steps 3 and 4 set the reference and places the part into Mixed Mode. In Steps 5 and 6 valid ADC results are read from the AD73360L and in Step 7 the DSP sends an instruc- tion to the AD73360L to change the gain of Channel 1 ...
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... Configuring a Cascade of Two AD73360Ls to Operate in Data Mode This section describes a typical sequence of control words that would be sent to a cascade of two AD73360Ls to set them up for operation not intended definitive initialization sequence, but will show users the typical input/output events that occur in the programming and operation phases . This description panel refers to Figure 34 ...
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... AD73360L DSP Tx REG CONTROL WORD 1 1000 1001 0000 0011 STEP 1 DSP Tx REG CONTROL WORD 1 1000 0001 0000 0011 STEP 2 DSP Tx REG CONTROL WORD 2 1000 1010 1110 0001 STEP 3 DSP Tx REG CONTROL WORD 1000 0010 1110 0001 STEP 4 DSP Tx REG CONTROL WORD ...
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... DSP and Device 1 sends an ADC result to Device 2. The remain- ing time before the next sample interval can be used to program more registers in the AD73360Ls. Care must be taken that the subsequent writes do not overlap the next sample interval to avoid corrupting the data. The control words are written as Device 2, Device 1, Device 2, etc ...
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... AD73360L DSP Tx REG CONTROL WORD 1 1000 1001 0000 0011 STEP 1 DSP Tx REG CONTROL WORD 2 1000 0001 0001 0011 STEP 2 DSP Tx REG CONTROL WORD 2 1000 0001 0001 0011 STEP 3 DSP Tx REG CONTROL WORD 1000 0010 1110 0001 STEP 4 DSP Tx REG CONTROL WORD ...
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... THD – 8kHz 1kHz IN SCLK = 8MHz 76 76.5 77 77.5 78 78.5 SNR – 64kHz 1kHz IN SCLK = 8MHz 4kHz 58 58.5 59 59.5 60 SNR – dB AD73360L f = 8kHz 1kHz IN SCLK = 16MHz –84 –83 –82 –81 –80 –79 THD – 8kHz 1kHz IN SCLK = 16MHz 74.5 75 75.5 76 76.5 77 77.5 SNR – ...
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... SPORT Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 15 Decimation Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE OF CONTENTS Page Topic OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Resetting the AD73360L . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Program (Control) Mode . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Mixed Program/Data Mode . . . . . . . . . . . . . . . . . . . . . . 17 Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Digital Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PERFORMANCE ...