TP82C54-2 Intel Corporation, TP82C54-2 Datasheet

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TP82C54-2

Manufacturer Part Number
TP82C54-2
Description
10MHz CHMOS programmable interval timer
Manufacturer
Intel Corporation
Datasheet

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The Intel 82C54 is a high-performance CHMOS version of the industry standard 8254 counter timer which is
designed to solve the timing control problems common in microcomputer system design It provides three
independent 16-bit counters each capable of handling clock inputs up to 10 MHz All modes are software
programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253
Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator
programmable one-shot and in many other applications
The 82C54 is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24-pin DIP
and 28-pin plastic leaded chip carrier (PLCC) packages
Compatible with all Intel and most
other microprocessors
High Speed ‘‘Zero Wait State’’
Operation with 8 MHz 8086 88 and
80186 188
Handles Inputs from DC
Available in EXPRESS
October 1994
10 MHz for 82C54-2
Standard Temperature Range
Extended Temperature Range
Figure 1 82C54 Block Diagram
CHMOS PROGRAMMABLE INTERVAL TIMER
231244 –1
82C54
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Three independent 16-bit counters
Low Power CHMOS
Completely TTL Compatible
Six Programmable Counter Modes
Binary or BCD counting
Status Read Back Command
Available in 24-Pin DIP and 28-Pin PLCC
I
frequency
CC
e
PLASTIC LEADED CHIP CARRIER
Diagrams are for pin reference only
Figure 2 82C54 Pinout
Package sizes are not to scale
10 mA
8 MHz Count
Order Number 231244-006
231244 –3
231244 –2

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TP82C54-2 Summary of contents

Page 1

CHMOS PROGRAMMABLE INTERVAL TIMER Compatible with all Intel and most Y other microprocessors High Speed ‘‘Zero Wait State’’ Y Operation with 8 MHz 8086 88 and 80186 188 Handles Inputs from MHz for 82C54-2 Available in EXPRESS ...

Page 2

Pin Number Symbol DIP PLCC D -D 1-8 2 CLK OUT GATE GND 12 14 OUT GATE CLK GATE ...

Page 3

Block Diagram DATA BUS BUFFER This 3-state bi-directional 8-bit buffer is used to in- terface the 82C54 to the system bus (see Figure 3) Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC ...

Page 4

Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag (See detailed explanation of ...

Page 5

OPERATIONAL DESCRIPTION General After power-up the state of the 82C54 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it ...

Page 6

Write Operations The programming procedure for the 82C54 is very flexible Only two conventions need to be remem- bered 1) For each Counter the Control Word must be written before the initial count is written 2) The initial count ...

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COUNTER LATCH COMMAND The second method uses the ‘‘Counter Latch Com- mand’’ Like a Control Word this command is written to the Control Word Register which is selected when Also like a Control Word the e 1 ...

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The read-back command may also be used to latch status information of ...

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Write into Counter Write into Counter Write into Counter Write ...

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If an initial count is written while GATE still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this ...

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MODE 2 RATE GENERATOR This Mode functions like a divide-by-N counter It is typicially used to generate a Real Time Clock inter- rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for ...

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OUT will be high for ( counts and low for counts b NOTE A GATE transition should not occur one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED ...

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After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe ...

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Operation Common to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE ...

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ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias Storage Temperature b Supply Voltage Operating Voltage Voltage on any Input GND Voltage on any Output GND Power Dissipation D C CHARACTERISTICS ( ...

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A C CHARACTERISTICS (Continued) WRITE CYCLE Symbol Parameter t Address Stable Before Stable Before Address Hold Time After Pulse Width WW t Data Setup Time Before WR DW ...

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WAVEFORMS WRITE READ RECOVERY 82C54 231244 –14 231244 –15 231244–16 17 ...

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CLOCK AND GATE A C TESTING INPUT OUTPUT WAVEFORM INPUT OUTPUT A C Testing Inputs are driven for a logic ‘‘1’’ and 0 45V for a logic ‘‘0 ’’ Timing measurements are made ...

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