AT45DB041A ATMEL Corporation, AT45DB041A Datasheet
AT45DB041A
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AT45DB041A Summary of contents
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... The AT45DB041A is a 2.5-volt only, serial interface Flash memory suitable for in-system reprogramming. Its 4,325,376 bits of memory are organized as 2048 pages of 264 bytes each. In addition to the main memory, the AT45DB041A also contains two SRAM data buffers of 264 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed ...
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... Architecture Diagram illustrates the breakdown of each AT45DB041A 2 To allow for simple in-system reprogrammability, the AT45DB041A does not require high input voltages for pro- gramming. The device operates from a single power supply, 2.5V to 3.0V or 2.7V to 3.6V, for both the program and read operations. The AT45DB041A is enabled through ...
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Memory Architecture Diagram SECTOR ARCHITECTURE SECTOR Pages 2112 bytes (2K + 64) SECTOR 1 = 248 Pages 65,472 bytes (62K + 1984) SECTOR 2 = 256 Pages 67,584 bytes (64K + 2K) SECTOR 3 = 512 Pages ...
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... BRBD A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. The maximum SCK frequency allowable for the Burst Array Read is defined by AT45DB041A 4 the f specification. The Burst Array Read bypasses both BAR data buffers and leaves the contents of the buffers unchanged ...
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... The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB041A, the three bits are 0, 1, and 1. The decimal value of these three binary bits does not equate to the device density; the three bits represent a ...
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... SCK pin to load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the AT45DB041A 6 PA6 PA5 ...
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The operation is internally self-timed and should take place in a maximum time of t time, the status register will indicate that the part is busy sector is programmed or reprogrammed sequentially page-by-page, then the ...
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... Auto Page Rewrite through Buffer 2 Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3). AT45DB041A 8 SCK Mode Inactive Clock Polarity Low or High ...
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Table 4. Detailed Bit-level Addressing Sequence Opcode Opcode 50H 52H 53H ...
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... After power is applied and V tional mode is started. AT45DB041A 10 *NOTICE: + 0.6V CC AT45DB041A (2.5V Version) 0°C to 70°C – 2. the minimum specified datasheet value, the system should wait 20 ms before an opera- CC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device ...
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... CMOS levels CMOS levels I 1 -100 µ Min Typ Max 0.6 2.0 0.4 - 0.2V CC AT45DB041A (2.5V Version) AT45DB041A Min Max Min Max 250 250 250 250 250 250 200 200 ...
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... SI Waveform 2 – Inactive Clock Polarity High and SPI Mode 3 CS tCSS SCK HIGH AT45DB041A 12 Output Test Load AC MEASUREMENT LEVEL times for the SI signal are referenced to the low-to-high transition on the SCK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3 ...
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Reset Timing (Inactive Clock Polarity Low Shown) CS SCK RESET HIGH IMPEDANCE SO SI Note: The CS signal should be in the high state before the RESET signal is deasserted. Command Sequence for Read/Write Operations (except Status Register Read) MSB ...
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... Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB041A 14 FLASH MEMORY ARRAY MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1 I/O INTERFACE ...
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Read Operations The following block diagram and waveforms illustrate the various read sequences available. PAGE (264 BYTES) MAIN MEMORY PAGE TO BUFFER 1 BUFFER 1 (264 BYTES) BUFFER 1 READ Main Memory Page Read CS SI CMD ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity Low Continuous Array Read (Opcode: 68H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO Burst Array Read (Opcode: 68H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB041A DATA OUT ...
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Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued) Main Memory Page Read (Opcode: 52H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: 54H or 56H) CS SCK 1 2 tSU COMMAND OPCODE ...
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... Detailed Bit-level Read Timing – Inactive Clock Polarity High Continuous Array Read (Opcode: 68H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO Burst Array Read (Opcode: 68H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB041A DATA OUT ...
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Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued) Main Memory Page Read (Opcode: 52H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: 54H or 56H) CS SCK 1 2 tSU COMMAND OPCODE ...
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... Detailed Bit-level Read Timing – SPI Mode 0 Continuous Array Read (Opcode: E8H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO Burst Array Read (Opcode: E8H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB041A DATA OUT ...
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Detailed Bit-level Read Timing – SPI Mode 0 (Continued) Main Memory Page Read (Opcode: D2H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: D4H or D6H) CS SCK 1 2 tSU COMMAND OPCODE SI ...
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... Detailed Bit-level Read Timing – SPI Mode 3 Continuous Array Read (Opcode: E8H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO Burst Array Read (Opcode: E8H) CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB041A DATA OUT ...
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Detailed Bit-level Read Timing – SPI Mode 3 (Continued) Main Memory Page Read (Opcode: D2H) CS SCK 1 2 tSU COMMAND OPCODE Buffer Read (Opcode: D4H or D6H) CS SCK 1 2 tSU COMMAND OPCODE SI ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB041A 24 START provide address ...
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Figure 2. Algorithm for Randomly Modifying Data MAIN MEMORY PAGE PROGRAM THROUGH BUFFER Notes preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations ...
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... Plastic Thin Small Outline Package (TSOP) 14C1 14-ball Array Plastic Chip-scale Ball Grid Array (CBGA) AT45DB041A 26 Ordering Code AT45DB041A-JC AT45DB041A-RC AT45DB041A-TC AT45DB041A-CC AT45DB041A-JI AT45DB041A-RI AT45DB041A-TI AT45DB041A-CI AT45DB041A-RC-2.5 AT45DB041A-TC-2.5 Package Type Package Operation Range 32J Commercial 28R (0°C to 70°C) 2.7V to 3.6V ...
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Packaging Information 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE .045(1.14) X 45˚ PIN NO. 1 IDENTIFY .553(14.0) .547(13.9) .032(.813) .595(15.1) .026(.660) .585(14.9) .050(1.27) TYP .300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS ...
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... Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war- ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...