FDC37N958FR Standard Microsystems, FDC37N958FR Datasheet
FDC37N958FR
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FDC37N958FR Summary of contents
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... Four 64K pages - Host System BIOS ! 8051 Keyboard and System Controller - Provides System Power Management - System Watch Dog Timer (WDT) - 8042 Style Host Interface SMSC DS – FDC37N958FR FDC37N958FR FEATURES - Asynchronous Access to Two Data Registers and One Status Register - Supports Interrupt and Polling Access - ...
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... IBM, PC/XT and PC/AT are registered trademarks and PS trademark of International Business Machines Corporation. SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation Order Number: FDC37N958FRTQFP 208 Pin QFP/TQFP Package Options SMSC DS – FDC37N958FR ! Enhanced Digital Data Separator - Low Cost Implementation ...
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... REGISTER DESCRIPTION ................................................................................................................... 80 PROGRAMMABLE BAUD RATE GENERATOR .................................................................................. 89 FIFO INTERRUPT MODE OPERATION................................................................................................ 91 FIFO POLLED MODE OPERATION...................................................................................................... 91 NOTES ON SERIAL PORT FIFO MODE OPERATION ........................................................................ 96 INFRARED COMMUNICATIONS CONTROLLER (IRCC) .................................................................... 98 IRRX/IRTX PIN ENABLE....................................................................................................................... 99 IR REGISTERS - LOGICAL DEVICE 5 ............................................................................................... 100 IR DMA CHANNELS............................................................................................................................ 101 SMSC DS – FDC37N958FR TABLE OF CONTENTS Rev. 09/01/99 ...
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... PARALLEL PORT ............................................................................................................................... 102 PARALLEL PORT INTERFACE MULTIPLEXOR ............................................................................... 124 HOST (LEGACY) PARALLEL PORT INTERFACE (FDC37N958FR STANDARD)............................ 125 PARALLEL PORT FDC INTERFACE ................................................................................................. 125 PARALLEL PORT - 8051 CONTROL (FDC37N958FR STANDARD) ................................................ 126 8051 EMBEDDED CONTROLLER...................................................................................................... 127 FEATURES.......................................................................................................................................... 127 8051 FUNCTIONAL OVERVIEW......................................................................................................... 127 8051 MEMORY MAP ........................................................................................................................... 131 8051 CONTROL REGISTERS ...
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... POWER MANAGEMENT..................................................................................................................... 221 ACCESS.BUS...................................................................................................................................... 222 BACKGROUND ................................................................................................................................... 222 REGISTER DESCRIPTION ................................................................................................................. 223 PS/2 DEVICE INTERFACE.................................................................................................................. 229 PS/2 LOGIC OVERVIEW..................................................................................................................... 229 SERIAL INTERRUPTS ........................................................................................................................ 233 FDC37N958FR CONFIGURATION ..................................................................................................... 238 CONFIGURATION ELEMENTS........................................................................................................... 238 TYPICAL SEQUENCE OF CONFIGURATION OPERATION.............................................................. 239 CONFIGURATION REGISTERS ......................................................................................................... 241 OPEN MODE REGISTERS.................................................................................................................. 266 SMSC DS – FDC37N958FR Rev. 09/01/99 ...
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... ELECTRICAL SPECIFICATIONS........................................................................................................ 269 LOAD CAPACITANCE ........................................................................................................................ 274 TIMING DIAGRAMS ............................................................................................................................ 275 FUNCTIONAL REVISION ADDENDUM .............................................................................................. 308 FDC37N958FR ERRATA SHEET........................................................................................................ 309 SMSC DS – FDC37N958FR Rev. 09/01/99 ...
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... There are 480 I/O address location options, 13 IRQ options, and 4 DMA channel options for each logical device. The FDC37N958FR does not require any external filter components and is, therefore, easy to use and offers lower system cost and reduced board area. The FDC37N958FR is software and register compatible with SMSC's proprietary 82077AA core ...
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... OUT11 200 OUT10 201 OUT9 202 OUT8 203 IRRX 204 IRTX 205 VCC2 206 GPIO17 207 GPIO18 208 GPIO19 FIGURE 1 - FDC37N958FR PIN CONFIGURATION SMSC DS – FDC37N958FR Page 2 104 VCC2 103 CLOCKI 102 OUT7 101 SIRQ 100 PSBDAT 99 PSBCLK 98 nMEMWR 97 nMEMRD 96 ...
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... FLASH ROM/ MEMORY MAP INTERFACE 161:166, FAD[7:0] 168:169 170:175, FA[8:17] 177:180 182 nFRD SMSC DS – FDC37N958FR DESCRIPTION HOST (ISA) INTERFACE System Data Bus System Address Bus ROM Chip Select Address Enable (DMA master has bus control) I/O Channel Ready DMA Requests DMA Requests/GP Outputs ...
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... The FDC output pins must tristate when the FDC is in powerdown mode (The board designer must provide external pull-up resistors on these output pins). 17 nRDATA 12 nWGATE 11 nWDATA SMSC DS – FDC37N958FR DESCRIPTION Flash Memory Write Flash Address latch Enable KEYBOARD Keyboard Scan Outputs(14*8 = 112) Configuring GPIO4 and GPIO5 as KSO14 and KSO15 yields a scan matrix 128 ...
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... MID[1]/ GPIO16 21 FPD 130 RXD1 131 TXD1 134 nRTS1 135 nCTS1 136 nDTR1 SMSC DS – FDC37N958FR DESCRIPTION Head Select (1 = side 0 ) Step Direction (1 = out ) Step Pulse Disk Change Drive Select 0 Motor On 0 Drive Select 1/ Output 5 Motor On 1/ Output 6 Write Protected Track 0 Index Pulse Input Drive Density Select [0:1] Media ID 0 input ...
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... BUSY 115 nACK 113 PE 112 SLCT 127 nERROR SMSC DS – FDC37N958FR DESCRIPTION Data Set Ready 1 Data Carrier Detect 1 Ring Indicator 1 SERIAL PORT 2 INTERFACE Receive Serial Data 2/ General Purpose I/O 8 Transmit Serial Data 2/ General Purpose I/O 9 Request to Send 2/ General Purpose I/O 10 Clear to Send 2/ ...
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... IRRX 204 IRTX 200 PWM0/ OUT10 199 PWM1/ OUT11 SMSC DS – FDC37N958FR DESCRIPTION 32 KHz Crystal Input 32 KHz Crystal Output MISCELLANEOUS System Management Interrupt/ Output 7 32 KHz Out -- The 32 KHz output is enabled / disabled by setting / clearing bit-0 of the Output Enable 8051 memory mapped register. ...
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... WK_HL4/ GPIO1 186 WK_HL5/ GPIO2 187 TRIGGER/ GPIO3 SMSC DS – FDC37N958FR DESCRIPTION VCC1 Power Good Input pin. The trailing edge of VCC1 POR is released 20ms from the assertion of this pin. If this pin is pulled low while VCC1 is valid, then VCC1 POR will be asserted and held until 20ms from re-assertion of this pin ...
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... Note ACCESS.bus SMSC DS – FDC37N958FR Table 1 - Power Pin List Bias Pins VCC0 RTC Supply Voltage VCC1 8051 + AB +4.7V Supply Voltage (Note) VCC2 Core +5V Supply Voltage AGND Analog Ground for VCC0. GND ...
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... GPIO9 COM-TX 145 GPIO10 nRTS2 | IR_MODE | FRX 146 GPIO11 nCTS2 147 GPIO12 nDTR2 144 GPIO13 nDSR2 140 GPIO14 nDCD2 SMSC DS – FDC37N958FR I/O Type Mux Default Alternate Control O24 O24 MISC0 O24 O24 O24 O24 O24 O24 O24 O24 O24 O24/OD24 ...
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... The Mux Control Column in Table 2 lists the Misc Bits which the 8051 has access to through the three Multiplexing registers. See the 8051 section of this data sheet for a description of the Multiplexing registers. SMSC DS – FDC37N958FR I/O Type Mux Default ...
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... Output, 8mA sink, 4mA source with Slew Rate Limiting O16 Output, 16mA sink, 8mA source. OD16 Open Drain Output, 16mA sink. O24 Output, 24mA sink, 12mA source. OD24 Open Drain Output, 24mA sink. OD48 Open Drain Output, 48mA sink SMSC DS – FDC37N958FR Page 12 Rev. 09/01/99 ...
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... XOSEL RTC XTAL2 two 128B banks of CMOS RAM XTAL1 BANK BANK VCC0 2 1 AGND FIGURE 2 - FUNCTIONAL BLOCK DIAGRAM SMSC DS – FDC37N958FR DIGITAL DATA nWDATA SEPARATOR WITH WRITE PRECOMPENSATION nRDATA, nDSKCHG, nWPROT, nTRK0, nINDEX, MID0, MID1(*1) SMSC PROPRIETARY nWGATE, nHDSEL, nDIR, 82077 COMPATIBLE ...
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... FDC37N958FR Ultra I/O controller. addresses of the FDC, Parallel, Serial 1 and Serial 2 ports can be moved via the configuration registers. Table 3 - FDC37N958FR Operating Register Addresses LOGICAL DEVICE LOGICAL NUMBER DEVICE 0x00 ...
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... Serial Port [0x100:0x0FF8 BYTE BOUNDARIES 0x62, [0x100:0x0FF8] 0x63 ON 8 BYTE BOUNDARIES 0x06 RTC Not Relocatable Fixed Base SMSC DS – FDC37N958FR BASE I/O RANGE FIXED (NOTE3) BASE OFFSETS +0 : RB/TB $ LSB div +1 : IER % MSB div +2 : IIR/FCR +3 : LCR +4 : MCR +5 : LSR +6 : MSR +7 : SCR +0 : RB/TB $ LSB div ...
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... Not Relocatable Note 1: Refer to the configuration register descriptions for setting the base address Note 2: Serial Port 2 supports Infrared. Note 3: This chip uses all ISA address bits to decode the base address of each of its logical devices. SMSC DS – FDC37N958FR BASE I/O RANGE FIXED (NOTE3) ...
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... Wake Up From Auto Powerdown If the FDC37N958FR enters the powerdown state through the auto powerdown mode, then the FDC37N958FR can be awakened by reset or by appropriate access to certain registers hardware or software reset is used then the FDC37N958FR will go through the normal reset sequence ...
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... The pins which interface to the floppy disk drive A are disabled so that no power will be drawn through the FDC37N958FR as a result of any voltage applied to the pin within the VCC2 power supply range. Most of the pins which interface to the system are left active to monitor system ...
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... Access to these registers wakes up the FDC37N958FR 04H 05H Note 1: Writing to the DOR or DSR does not wake up the FDC37N958FR, however, writing any of the motor enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the FDC37N958FR. SMSC DS – FDC37N958FR the powerdown are labeled " ...
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... The FPD pin can be used to automatically shut off power to the floppy disk drive when it is not required. The FPD pin is an active high output signal which is driven based on the states of the SMSC DS – FDC37N958FR STATE IN AUTO POWERDOWN Input Pins Unchanged Unchanged ...
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... AUTO POWER DOWN Note: The FPD pin will go active when the FDC auto powers down. Refer to the FDC auto power management section for more details. SMSC DS – FDC37N958FR STATE IN FDC AUTO POWERDOWN Input Pins Input Input Input Input Input ...
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... The transmitter exits powerdown on a write to the transmit buffer. The receiver powerdown when RXD changes state. SMSC DS – FDC37N958FR Parallel Port Power Management Direct power management is controlled by CR22. Refer to CR22 in the Configuration Section for more information. Auto power management is enabled by CR23 bit 3 ...
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... SMSC DS – FDC37N958FR The FDC is compatible to the 82077AA using SMSC's proprietary FDC core. FDC INTERNAL REGISTERS The FDC contains eight internal registers which facilitate the interfacing microprocessor and the disk drive. shows the addresses required to access these registers. ...
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... Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. SMSC DS – FDC37N958FR pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins are held in a high impedance state for a read of SRA ...
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... BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. SMSC DS – FDC37N958FR STEP TRK0 nHDSEL INDX ...
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... This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. SMSC DS – FDC37N958FR DRIVE WDATA RDATA ...
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... Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA input signal. This bit is latched by the inactive going SMSC DS – FDC37N958FR nDS0 WDATA ...
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... FDC’s DRQ and Interrupt outputs in a high impedance state. This bit is a logic "0" after a reset. SMSC DS – FDC37N958FR contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time ...
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... Bit 5 Bit 4 Bit1 SMSC DS – FDC37N958FR DRIVE DOR VALUE 0 1CH 1 2DH DRIVE SELECT OUTPUTS (ACTIVE LOW) Bit 0 nDS1 nDS0 DRIVE SELECT OUTPUTS (ACTIVE LOW) ...
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... ID0 For this mode, MID[1:0] pins are gated into bits 6 and 7 of the TDR register. These two bits are not affected by a hard or soft reset. SMSC DS – FDC37N958FR the device. The TDR is unaffected by a software reset. Normal Floppy Mode Normal mode. The TDR Register contains only bits 0 and 1 ...
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... Bit 1 Bit Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. SMSC DS – FDC37N958FR Which two bits these are depends on the last drive selected in the Digital Output Register. (See Table 14) Table 12 - Media ID 1 MEDIA ID1 BIT 7 L0-CRF1-B5 L0-CRF1- ...
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... Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command. SMSC DS – FDC37N958FR and PS/2 Model applications. Other applications can set the data rate in the DSR. ...
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... Drive Rate Table (Recommended) Note 1: The DRATE and DENSEL values are mapped onto the DRIVEDEN pins. SMSC DS – FDC37N958FR PRECOMPENSATION DELAY (nsec) <2Mbps 2Mbps 0.00 41.67 83.34 125.00 166.67 208.33 104.2 250.00 Default Default Default: See Table 17 ...
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... DRATE0 1 1 DRATE1 Table 18 - Default Precompensation Delays DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps The 2 Mbps data rate is only available if V SMSC DS – FDC37N958FR Table 17 - DRVDEN Mapping DRVDEN0 (1) DENSEL 4/2/1 MB 3.5" 2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE) DRATE1 nDENSEL PS/2 DRATE0 PRECOMPENSATION DELAYS 20 ...
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... BIT 7 RQM Indicates that the host can transfer data if set to a “1”. No access is permitted if set to a “0”. SMSC DS – FDC37N958FR The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode ...
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... FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes The 2 Mbps data rate is only available if V SMSC DS – FDC37N958FR Table 19 - FIFO Service Delay MAXIMUM DELAY TO SERVICING AT 2 Mbps* DATA RATE 58.5 ms ...
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... Kbps and 300 Kbps are selected. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 16 for the settings corresponding to the individual data rates. The data rate select bits are unaffected SMSC DS – FDC37N958FR N/A N/A N/A N/A ...
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... The data rate select bits are unaffected by a software reset and are set to 250 Kbps after a hardware reset. BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register. SMSC DS – FDC37N958FR ...
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... These bits determine the data rate of the floppy controller. See Table 16 for the appropriate values. BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. SMSC DS – FDC37N958FR N/A N/A N/A N/A These bits determine the data rate of the floppy controller ...
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... H Head Address 1,0 DS1,0 Drive Select SMSC DS – FDC37N958FR During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 20 - Status Register 0 DESCRIPTION 00 - Normal termination of command. command was properly executed and completed without error ...
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... NW Not Writable 0 MA Missing Address Mark SMSC DS – FDC37N958FR Table 21 - Status Register 1 DESCRIPTION The FDC tried to access a sector beyond the final sector of the track (255D). Will be set not issued after Read or Write Data command. Unused. This bit is always "0". ...
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... Register (which controls RESET_OUT/nRESET_OUT pins FDC37N958FR); a reset generated via a bit in the DOR; and a reset generated via a bit in the DSR. At VCC2 power on, a VCC2 Power On Reset initializes the FDC. All resets take the FDC out of the power down state. All operations are terminated upon a RESET, and the Floppy Disk Controller enters an idle state ...
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... TC is active high and DENSEL is active low. DMA TRANSFERS DMA transfers are enabled with the Specify command and are initiated by the FDC by activating its DRQ pin during a data transfer SMSC DS – FDC37N958FR command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid. ...
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... FIFO. The FDC will deactivate the FDC’s IRQ pin and RQM bit when the FIFO becomes empty. SMSC DS – FDC37N958FR Non-DMA Mode - Transfers from the Host to the FIFO The FDC’s IRQ pin and RQM bit in the Main Status Register are activated upon entering the execution phase of data transfer commands ...
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... FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay. SMSC DS – FDC37N958FR Result Phase The generation of the FDC’s IRQ determines the beginning of the result phase. For each of the ...
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... Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with SMSC DS – FDC37N958FR the command invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error ...
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... HLT Head Load Time HUT Head Unload Time LOCK SMSC DS – FDC37N958FR DESCRIPTION The currently selected address 255. The pattern to be written in each sector data field during formatting. Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive ...
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... RCN Relative Cylinder Number SC Number of Sectors Per Track SMSC DS – FDC37N958FR DESCRIPTION writing to the appropriate bits of either tha DSR or DOR) A one selects the double density (MFM) mode. A zero selects single density (FM) mode. When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and single track ...
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... ST2 Status 2 ST3 Status 3 WGATE Write Gate SMSC DS – FDC37N958FR DESCRIPTION a Verify command when EC is set. When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to " ...
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... PHASE R Command W MT MFM Execution Result SMSC DS – FDC37N958FR Table 25 - FDC Instruction Set READ DATA DATA BUS HDS DS1 DS0 -------- C -------- -------- H -------- -------- R -------- -------- N -------- ------- EOT ------- ------- GPL ------- ------- DTL ------- ...
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... PHASE R Command W MT MFM Execution Result SMSC DS – FDC37N958FR READ DELETED DATA DATA BUS HDS DS1 DS0 -------- C -------- -------- H -------- -------- R -------- -------- N -------- ------- EOT ------- ------- GPL ------- ------- DTL ------- ------- ST0 ------- ------- ST1 ------- ------- ST2 ------- ...
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... PHASE R Command W MT MFM Execution Result SMSC DS – FDC37N958FR WRITE DATA DATA BUS HDS DS1 DS0 -------- C -------- -------- H -------- -------- R -------- -------- N -------- ------- EOT ------- ------- GPL ------- ------- DTL ------- ------- ST0 ------- ------- ST1 ------- ------- ST2 ------- -------- C -------- -------- H -------- ...
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... PHASE R Command W MT MFM Execution Result SMSC DS – FDC37N958FR WRITE DELETED DATA DATA BUS HDS DS1 -------- C -------- -------- H -------- -------- R -------- -------- N -------- ------- EOT ------- ------- GPL ------- ------- DTL ------- ------- ST0 ------- ------- ST1 ------- ------- ST2 ------- -------- C -------- -------- H -------- ...
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... PHASE R Command W 0 MFM Execution Result SMSC DS – FDC37N958FR READ A TRACK DATA BUS HDS DS1 -------- C -------- -------- H -------- -------- R -------- -------- N -------- ------- EOT ------- ------- GPL ------- ------- DTL ------- ------- ST0 ------- ------- ST1 ------- ------- ST2 ------- -------- C -------- -------- H -------- -------- R -------- -------- N -------- ...
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... MT MFM Execution Result PHASE R Command W 0 Result R 1 SMSC DS – FDC37N958FR VERIFY DATA BUS HDS DS1 -------- C -------- -------- H -------- -------- R -------- -------- N -------- ------- EOT ------- ------- GPL ------- ------ DTL/SC ------ ------- ST0 ------- ------- ST1 ------- ------- ST2 ------- -------- C -------- -------- H -------- ...
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... W W Execution for W Each Sector Repeat Result PHASE R Command Execution SMSC DS – FDC37N958FR FORMAT A TRACK DATA BUS HDS DS1 -------- N -------- -------- SC -------- ------- GPL ------- -------- D -------- -------- C -------- -------- H -------- -------- R -------- -------- N -------- ------- ST0 ------- ------- ST1 ------- ...
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... Command Result R R PHASE R Command --- SRT --- W PHASE R Command Result R SMSC DS – FDC37N958FR SENSE INTERRUPT STATUS DATA BUS ------- ST0 ------- ------- PCN ------- SPECIFY DATA BUS ...
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... W Execution PHASE R Command EIS EFIFO Execution W PHASE R Command W 1 DIR SMSC DS – FDC37N958FR SEEK DATA BUS HDS DS1 DS0 ------- NCN ------- CONFIGURE DATA BUS ...
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... PHASE R/W D7 Command W 0 Execution Result LOCK SMSC DS – FDC37N958FR DUMPREG DATA BUS ------ PCN-Drive 0 ------- ------ PCN-Drive 1 ------- ------ PCN-Drive 2 ------- ------ PCN-Drive 3 ------- ---- SRT ---- --- HUT --- ------- HLT ------- ------- SC/EOT ------- EIS EFIFO POLL -- FIFOTHR -- -------- PRETRK -------- Page REMARKS 1 0 *Note: ...
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... PHASE R Command W 0 MFM W 0 Execution Result PHASE R/W D7 Command SMSC DS – FDC37N958FR READ ID DATA BUS HDS DS1 -------- ST0 -------- -------- ST1 -------- -------- ST2 -------- -------- C -------- -------- H -------- -------- R -------- -------- N -------- PERPENDICULAR MODE DATA BUS ...
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... Read or Write. Note: These bits are used internally only. They are not reflected in the Drive Select pins the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR). SMSC DS – FDC37N958FR INVALID CODES DATA BUS ...
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... ID fields. When the sector address read off The amount of data which can be handled with a single command to the FDC depends upon MT SMSC DS – FDC37N958FR the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO ...
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... SMSC DS – FDC37N958FR If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to " ...
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... Deleted Data Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 29 describes the effect of the SMSC DS – FDC37N958FR RESULTS SECTOR CM BIT OF DESCRIPTION OF READ? ST2 SET? ...
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... The FDC compares the ID information read from each sector with the specified value in the command and sets the ND flag of Status SMSC DS – FDC37N958FR RESULTS SECTOR CM BIT OF DESCRIPTION OF READ? ST2 SET? ...
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... FIFO and writes it to the sector's data field. After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of SMSC DS – FDC37N958FR Table 30 - Result Phase Table ID INFORMATION AT RESULT PHASE ...
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... Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like SMSC DS – FDC37N958FR a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value ...
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... D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for and N (cylinder, head, number and sector size respectively). SMSC DS – FDC37N958FR SC/EOT VALUE TERMINATION RESULT Success Termination Result Phase Valid ...
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... IAM GAP1 SYNC 40x 6x 26x GAP4a SYNC IAM GAP1 SYNC 80x 12x 50x 12x SMSC DS – FDC37N958FR Table 32 - Diskette Format Fields IDAM GAP2 SYNC 22x 12x IDAM C H ...
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... GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives. Note: All values except sector size are in hex. SMSC DS – FDC37N958FR N SC 128 00 12 ...
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... Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command SMSC DS – FDC37N958FR phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase NON-BUSY state. At this time, another ...
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... Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification SMSC DS – FDC37N958FR Sense Interrupt Status An interrupt signal on the FDC’s IRQ pin is generated by the FDC for one of the following reasons: 1. Upon entering the Result Phase of: A. ...
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... ND bit. When this bit is "1", the non- DMA mode is selected, and when ND is "0", the DMA mode is selected. In DMA mode, data SMSC DS – FDC37N958FR execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval ...
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... Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. SMSC DS – FDC37N958FR Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value returned as the result byte ...
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... Table 36 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a SMSC DS – FDC37N958FR reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0). Selection of the 500 Kbps and 1 Mbps ...
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... D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. SMSC DS – FDC37N958FR In this mode the following set of conditions also apply: 1. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate ...
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... FORMAT FIELD WRITE DATA OPERATION 22 Bytes 22 Bytes 22 Bytes 41 Bytes COMPATIBILITY The FDC37N958FR was designed with software compatibility in mind. compatible solution with the older generation 765A/B disk implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, FDC subsystems. After a hardware reset of the FDC, ...
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... Specification. DSR, bit-6 (pwr down) =0: Normal Run =1: Manual Pwr down Refer to the description of the DSR in the FDC section of any SMSC Super or Ultra I/O data sheet. SMSC DS – FDC37N958FR 2) the Activate bit; and 3) the FDC powerdown pins for state. FDC IN POWER DOWN FDC PINS ...
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... Note1: DSR pwr down overrides auto pwr down. Note 2: Outputs tri-state only if all of the required auto power down conditions are met, otherwise outputs are active. See Auto Power Management Section of the FDC37C93x Data Sheet. SMSC DS – FDC37N958FR FDC OUTPUT PINS STATE X ...
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... The FDC37N958FR incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start ...
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... Line Status and MODEM Status Registers. contents of the Interrupt Enable Register are described below. SMSC DS – FDC37N958FR BIT 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1". ...
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... This bit is self- clearing. BIT 7 BIT SMSC DS – FDC37N958FR BIT 3 Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip. BITS 4 and 5 Reserved BITS 6 and 7 These bits are used to set the trigger level for the RCVR FIFO interrupt ...
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... SMSC DS – FDC37N958FR BIT 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit logic " ...
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... REGISTER SMSC DS – FDC37N958FR INTERRUPT SET AND RESET FUNCTIONS Second Received Data Receiver Data Available Available Second Character No Characters Timeout Have Been Indication Removed From or Input to the RCVR FIFO during the last 4 Char times and ...
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... Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. SMSC DS – FDC37N958FR BITS 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. encoding of bits 0 and follows: BIT 0 ...
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... This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR SMSC DS – FDC37N958FR output is forced to a logic "0". When bit logic "0", the nDTR output is forced to a logic "1". ...
Page 93
... FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read. SMSC DS – FDC37N958FR BIT 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic " ...
Page 94
... In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. SMSC DS – FDC37N958FR These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read ...
Page 95
... Rate Generator that is capable of taking any clock input ( MHz) and dividing it by any divisor from 1 to 65535. This output frequency of the SMSC DS – FDC37N958FR Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format ...
Page 96
... The percentage error for all baud rates, except where indicated otherwise, is 0.2%. Baud Rates Using 1.8462 MHz Clock for <=38.4; Using 1.843 MHz Clock for 115.2k; Using 3.6864 MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k SMSC DS – FDC37N958FR Table 39 - UART Baud Rates PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL* 0.001 - - 0 ...
Page 97
... This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character. SMSC DS – FDC37N958FR B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the baudrate). C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO ...
Page 98
... Bit 5 indicates when the XMIT FIFO is empty. ! Bit 6 indicates that both the XMIT FIFO and shift register are empty. SMSC DS – FDC37N958FR ! Bit 7 indicates whether there are any errors in the RCVR FIFO. There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters ...
Page 99
... INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO SMSC DS – FDC37N958FR Table 40 - Reset Function Table RESET CONTROL RESET All bits low RESET Bit 0 is high; Bits low RESET All bits low ...
Page 100
... Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. SMSC DS – FDC37N958FR REGISTER SYMBOL BIT 0 ...
Page 101
... Note 3: This bit no longer has a pin associated with it. Note 4: When operating in the XT mode, this register is not available. Note 5: These bits are always zero in the non-FIFO mode. Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. SMSC DS – FDC37N958FR BIT 4 BIT 5 BIT 6 ...
Page 102
... FIFO will be empty again and typically the UART's interrupt line would transition to the active state. This could cause a system with an interrupt SMSC DS – FDC37N958FR control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that Therefore, after the first byte has interrupt ...
Page 103
... Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the SMSC DS – FDC37N958FR CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud) ...
Page 104
... IrDA-SIR allows serial communication at baud rates up to 115K Baud. Each word is sent serially beginning with a “0” value start bit. signaled by sending a single IR pulse at SMSC DS – FDC37N958FR the beginning of the serial bit time. signaled by sending no IR pulse during the bit time. ...
Page 105
... FIGURE 3 - INTEGRATION OF IrCC LOGIC INTO THE FDC37N958FR HP_MODE = (MISC[14:13] == [1:0]) | (MISC[16:15] == [1:0]) FRX_SEL = (MISC[14:13] == [1:0]) IRRX/IRTX PIN ENABLE When MISC2=0 the IRRX and IRTX pins are enabled as when UART2 (LD5) is activated or enabled and the IrCC Output Mux is set to use SMSC DS – ...
Page 106
... ON 8 BYTE BOUNDARIES Register 0x60 stores the MSB and 0x61 the LSB of the 550-UART’s 16 bit Base Address. SMSC DS – FDC37N958FR Fast IR Base I/O Address registers 0x62 and 0x63; an IrCC DMA channel select register 0x74; and an IR Half Duplex Timeout register 0xF2. ...
Page 107
... Logical Device 5. Refer to the Configuation section of this specification for further details on setting the DMA channel and to the IrCC specificaton for details on IR DMA transfers. SMSC DS – FDC37N958FR FIXED REGISTER BASE +0 : Register Block N, address Register Block N, address Register Block N, address 2 ...
Page 108
... The FDC37N958FR incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation ...
Page 109
... Peripheral Interface for Personal Computers”, September 10, 1993. This document is available from the IEEE. IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is SMSC DS – FDC37N958FR STANDARD EPP nStrobe nWrite PData<0:7> PData<0:7> nAck Intr Busy ...
Page 110
... A logic “1” means that it is still processing the last character or has not received the data. SMSC DS – FDC37N958FR BIT 7 nBUSY - nBUSY The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic “ ...
Page 111
... EPP DATA PORT 0 ADDRESS OFFSET = 04H The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register SMSC DS – FDC37N958FR is cleared at initialization by RESET. During a WRITE operation, the contents of DB0-DB7 are buffered (non inverting) and output onto the ...
Page 112
... Address cycle. IOCHRDY is driven active low at the start of each EPP write and is released when it has been determined that the write cycle can complete. SMSC DS – FDC37N958FR The write cycle can complete under the following circumstances the EPP bus is not ready (nWAIT is active ...
Page 113
... Peripheral drives PData bus valid. 7. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. SMSC DS – FDC37N958FR 8. a) The chip latches the data from the PData bus for the SData bus and deasserts nDATASTB or nADDRSTRB ...
Page 114
... When the host deasserts nIOW the chip deasserts nDATASTB or nADDRSTRB and SMSC DS – FDC37N958FR latches the data from the SData bus for the PData bus. 7. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle. ...
Page 115
... Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required low. SMSC DS – FDC37N958FR Table 45 - EPP Pin Descriptions EPP DESCRIPTION O This signal is active low ...
Page 116
... Permits the use of active output drivers ! Permits the use of adaptive signal timing ! Peer-to-peer capability SMSC DS – FDC37N958FR Vocabulary The following terms are used in this document: assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. ...
Page 117
... MODE Note 1: These registers are available in all modes. Note 2: All FIFOs use one common 16 byte FIFO. SMSC DS – FDC37N958FR ! HostClk, nStrobe Reference Document IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993. This document is available from Microsoft. ...
Page 118
... LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an SMSC DS – FDC37N958FR automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions. ...
Page 119
... This pin is driven low to place the channel in the reverse direction. The peripheral is only allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low and nSelectIn is high. nSelectIn O Always deasserted in ECP mode. SMSC DS – FDC37N958FR Table 46 - ECP Pin Descriptions DESCRIPTION The peripheral drives this signal low to acknowledge " ...
Page 120
... Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition. SMSC DS – FDC37N958FR ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode ...
Page 121
... Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet. DEVICE STATUS REGISTER (dsr) ADDRESS OFFSET = 01H SMSC DS – FDC37N958FR Table 48 - Mode Descriptions DESCRIPTION* The Status Port is located at an offset of '01H' from the base address. ...
Page 122
... SMSC DS – FDC37N958FR BITS 6 and 7 during a read are a low level, and cannot be written. cFifo (Parallel Port Data FIFO) ...
Page 123
... RLE compression. It does support hardware de-compression! BIT 6 intrValue Returns the value on the ISA iRq line to determine possible conflicts. SMSC DS – FDC37N958FR BITS 5:0 Reserved The FIFO During a read are a low level. These bits cannot be written. ecr (Extended Control Register) ADDRESS OFFSET = 402H ...
Page 124
... All drivers have active pull-ups (push-pull). 111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). SMSC DS – FDC37N958FR BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full ...
Page 125
... ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. SMSC DS – FDC37N958FR After negotiation necessary to initialize some of the port bits. The following are required: ! Set Direction = 0, enabling the drivers. ...
Page 126
... Table 50 - Forward Channel Commands (HostAck Low) & Reverse Channel Commands (PeripAck Low SMSC DS – FDC37N958FR The most significant bit of the command indicates whether run-length count (for compression channel address. When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low ...
Page 127
... PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section.) Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals. SMSC DS – FDC37N958FR Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 serviceIntr = 0 ...
Page 128
... CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the SMSC DS – FDC37N958FR programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to “1” and serviceIntr to 0 ...
Page 129
... FIFO this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst. SMSC DS – FDC37N958FR PDRQ goes readIntrThreshold = (16-<threshold>) data bytes in FIFO An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-< ...
Page 130
... Port Physical Interface pins. Under 8051 control the Parallel Port Output pins are always enabled or driven and only tri-state when VCC2 is removed (powergood=0). SMSC DS – FDC37N958FR sources. The sources are detailed as follows: DESCRIPTION All configuration and control bits If the Host does not have control of the Parallel ...
Page 131
... These pins are outputs in mode PPFD2; in mode PPFD1 only one pair, depending on Drive Swap bit, is active and should be connected to the FDD, the inactive pair should not be connected to the FDD. SMSC DS – FDC37N958FR In this mode, the parallel port pins are controlled by the host through the parallel port logical device ...
Page 132
... Reminder the designer to provide pull-up resistors on these FDC output pins. nWDATA, DRVDEN0, nHDSELm nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1. Parallel Port - 8051 Control (FDC37N958FR Standard) In this mode, the parallel port pins are controlled by the 8051 through a set of three on-chip memory mapped registers ...
Page 133
... Hardware Description of the 8051, 8052, and 80C51 and the 80C51BH-1/80C51BH-2 CHMOS Single-Chip 8 Bit Microcomputer data sheets in SMSC DS – FDC37N958FR FEATURES the 8 Bit Embedded Controller Handbook. large set of External Memory/Mapped Control Registers provide the 80C51 core with the ability to directly control many functional blocks of the FDC37N958FR ...
Page 134
... Powering up or Reseting the 8051 Default Reset Conditions The FDC37N958FR has two sources of reset: a VCC1 Power On Reset (VCC1 POR VCC2 POR. An FDC37N958FR reset from any of these sources will cause the hardware response shown in Table 55, 8051 On-Chip External Memory Mapped Registers. ...
Page 135
... The 8051 begins executing code at address 8000h. FIGURE 4 - SYSTEM POWER UP SEQUENCE SMSC DS – FDC37N958FR N The 8051 begins executing from program address 00h. Y Page 129 Rev. 09/01/99 ...
Page 136
... System Reset Sequence FIGURE 5 - TYPICAL SYSTEM RESET SEQUENCE SMSC DS – FDC37N958FR Page 130 Rev. 09/01/99 ...
Page 137
... ROM and 32K of external ROM. The nEA pin is used to enable access to the 256B of internal Scratch ROM or External program ROM. The FDC37N958FR also contains 256 bytes of internal on-chip RAM. When nEA=0, all the ROM is addressed as the external ROM. It can support up to 32K bytes of ...
Page 138
... Instructions to access memory: MOV: Internal RAM/Registers. MOVC: Program ROM from 0000h through FFFFh MOVX: External RAM from 7D00h through 7FFFh -AND- External ROM from 8000h through FFFFh. (allows flashing of ROM). SMSC DS – FDC37N958FR 7FFFh M/M Registers 7F00h RAM 7E00h Scratch RAM 7D00h ...
Page 139
... JMP instructions must be located at {0x03, 0x0B, 0x13, 0x1B, 0x23, 0x2B} to {0x8003, 0x800B, 0x8013, 0x801B, 0x8023, 0x802B} respectively. SMSC DS – FDC37N958FR re-writeable ROM space can be added to the 8051’s internal ROM space to allow patch code upgrades. In order to take advantage of this ...
Page 140
... MOVC: Program ROM from 8000h through FFFFh MOVX: External RAM from 7D00h through 7FFFh -AND- External ROM from 8000h through FFFh. (allows flashing of ROM). SMSC DS – FDC37N958FR encoded at addresses 00h through 02h and a 256 byte scratch RAM is located at external addresses 7D00-7DFF. ...
Page 141
... Program ROM from 00h through 0FFh called from 00h-0FFh only. MOVX: External RAM from 7E00h through 7FFFh -AND- External ROM from 8000h through FFFFh. (allows flashing of ROM). SMSC DS – FDC37N958FR executable internal scratch ROM at address locations 00h-0FFh. The hard coded LJMP to 8000h is overridden by the scratch ROM. ...
Page 142
... Port 3: Does not exist. SMSC DS – FDC37N958FR Table map of the on-chip Special Function Register FDC37N958FR provides all standard 80C51 SFRs (see the Hardware Description of the 8051 and 8052 and 80C51 in the 8 Bit Embedded Controller Handbook). Table 55 - SFR Memory MAP TL0 ...
Page 143
... Data Read Reg] GATEA20 ------ N/A FBh PCOBF ------ N/A FDh SETGA20L ------ N/A FEh RSTGA20L ------ N/A FFh SMSC DS – FDC37N958FR 3. mov movx 4. mov movx ISAxxh = system ISA I/O address IDXxxh = Open Registers, See Configuration Section. 8051 Addresses = on-chip external Memory Mapped Register locations 8051 8051 POWER VCC1 (7F00+) ...
Page 144
... GPIO Ouput ------ N/A 1Ch register B GPIO Input ------ N/A 1Dh register B GPIO ------ N/A 1Eh Direction register C GPIO Ouput ------ N/A 1Fh register C GPIO Input ------ N/A 20h register C SMSC DS – FDC37N958FR 8051 8051 POWER VCC1 (7F00+) R/W SOURCE POR R VCC1 00h R/W VCC1 00h R VCC1 00h R/W VCC1 00h W VCC1 20h R VCC1 ...
Page 145
... Mask 3 WDT ------ N/A 37h Control/Statu s WDT Timer ------ N/A 38h PP Status N/A 3Ah Reg PP Control ------ N/A 3Bh Reg PP Data Reg ------ N/A 3Ch Multiplexing ------ N/A 3Dh 1 register SMSC DS – FDC37N958FR 8051 8051 POWER VCC1 (7F00+) R/W SOURCE POR R/W VCC1 R/W VCC1 R/W VCC1 R VCC1 N/A R/W VCC1 00h R/W VCC1 00h R/W VCC1 10h R/W VCC1 00h ...
Page 146
... Notes 1. Although the Input and Output Data registers are physically separate, they share address 7FF1H. 2. The FDC37N958FR CPU cannot write to some bits of the Status register. 3. Writing to the Auxiliary Output Data Register loads the Output data register and can set the AUXOBF1 output if enabled. This does not set the PCOBF output. ...
Page 147
... BOTH VCC2 is valid and PWRGD is asserted. 12. This register is powered by VCC1. The data contents remains undefined until VCC2 POR. 13. This register is impacted by a device functional revision. See FUNCTIONAL REVISION ADDENDUM on page 308 for VCC1 and VCC2 POR impact and default values. SMSC DS – FDC37N958FR Page 141 Rev. 09/01/99 ...
Page 148
... Note: This register is hardwired. This register is impacted by device functional revision. See FUNCTIONAL REVISION ADDENDUM on page 308 for devault values. Device ID Register 8051 R Bit description SMSC DS – FDC37N958FR By reading this register, 8051 firmware can confirm the device revision that it is running on. Host N/A ...
Page 149
... OBF of the status register is equal to 1. MMC Memory Map Control Bit : When MMC=0, a 256 Byte Scratch RAM area at 7D00h is available to the 8051. When MMC=1 the Scratch RAM at 7D00h-7DFFh becomes scratch ROM at 00h-- FFh. SMSC DS – FDC37N958FR Configuration Register 0 Host N/A 8051 0x7FF4 Power VCC1 ...
Page 150
... The 8051 can write this bit to start or stop the ring oscillator. Other hardware events can also start or stop this clock turn on ring oscillator = 0 turn off ring oscillator KBCLK1 SMSC DS – FDC37N958FR KSTP_CLK Register Host N/A 8051 0x7F27 Power VCC1 Default 0x10 ...
Page 151
... System N/A N/A R/W Parallel Serial Port Port Enable Enable Disable Disable Note 1: If D2=0, then the FLASH is write protected from the system. The system can still read the FLASH. SMSC DS – FDC37N958FR DISABLE Register Host N/A 8051 0x7F3F Power VCC1 Default 0x00 R/W R/W R/W N/A ...
Page 152
... RESET_OUT low. The RESET_OUT Override function allows the 8051 to take the rest of the FDC37N958FR chip (SIO) out of reset without giving up control (i.e., without stopping its clock and giving the flash interface to the Host). SMSC DS – FDC37N958FR Output Enable Register ...
Page 153
... Interrupts The FDC37N958FR provides the five standard 8051 interrupts (Group 0) plus an additional T5INT interrupt which is located at the vector address for Timer 2 which is standard on the 8051 standard micro-controller. describes the interrupts. The Group 0 interrupts use the standard 8051 interrupt enable and priority structures. ...
Page 154
... Additional Interrupt Sources Inside the FDC37N958FR, interrupt events from various sources are able to generate either an polling INT0 or INT1 8051 interrupt. The 8051 firmware masks these interrupt sources by writing “1s” into the 8051 INT0 or INT1 Mask Registers and enables these interrupts by writing “ ...
Page 155
... R Bit Description Reserved Note: this register is cleared on a read. D7-D4 D3 8051 R/W R/W R/W Bit Def Reserved 1=mask MSB When enabled, INT0 is generated on either positive or negative-going edge of WK_EE4 [ERDY]. SMSC DS – FDC37N958FR 8051 INT0 Source Register Host N/A 8051 0x7F00 (R) Power VCC1 Default 0x00 ...
Page 156
... Note 5: This bit is set when the system writes to mailbox register 0. This bit is cleared by a read of the mailbox 0 register D7 D6 8051 R/W R/W R/W Bit Mask Def Mask The IBF Keyboard Matrix Scan Flag SMSC DS – FDC37N958FR 8051 INT1 Source Register Host N/A 8051 0x7F02 (R) Power VCC1 Default 0x00 ...
Page 157
... WDT Activation Upon VCC1 POR the Watch Dog Timer powers up inactive. The Watch Dog Timer is activated SMSC DS – FDC37N958FR when the WDT enable bit (WDT CONTROL bit D1) is set by 8051 firmware. The WDT may be disabled under software control through a specific sequence ...
Page 158
... Reserved WLE Watchdog Load Enable bit must be set to enable writing to the WDT Timer register. This bit is automatically reset when the 8051 writes to the WDT register. If this bit is reset, writes to the WDT register are ignored. SMSC DS – FDC37N958FR R/W N/A WDT Timer ...
Page 159
... S S FDC37C957FR FIGURE 9 - FLASH INTERFACE DIAGRAM SMSC DS – FDC37N958FR Flash Interface Diagram Access to the Flash Memory is multiplexed inside of the FDC37N958FR. only has access nRESET_OUT is not asserted and the 8051 STP_CLK bit-0 is set. Please refer to the timing section for details on this interface. ...
Page 160
... System Flash Access Map 64K Host Interface FFFF 0 64K 8051 ROM FFFF Same as 0-7FFF 8000 0 SMSC DS – FDC37N958FR 256K FLASH ROM 8x 32K Blocks FIGURE 10 - 8051 MODE 2 Page 154 64K 8051 External RAM FFFF 8000 Internal Registers 0 Rev. 09/01/99 ...
Page 161
... R/W System R/W Bit Def The 8051 uses this register to access the Flash ROM in a 32K window. The 8051 is only barred KMEM SMSC DS – FDC37N958FR Keyboard BIOS (KMEM) KMEM Register Host N/A 8051 0x7F29 Power VCC1 Default 0x00 D7- R/W ...
Page 162
... Host Flash Access The FDC37N958FR has a special shared Flash ROM interface. The 8051 can be stopped to allow the Host CPU to access the flash ROM after a special handshake sequence is followed. HOST INITIATED FLASH ACCESS To access the FLASH memory, the 8051 must first be placed into idle mode, and then the 8051 clock must be stopped ...
Page 163
... Timer N IRQ ? (Note) FIGURE 11 - DYNAMIC SHARING OF FLASH INTERFACE BETWEEN HOST AND 8051 SMSC DS – FDC37N958FR Note: In order to leave idle mode the 8051 must receive an interrupt; typically a software timer interupt will be used. Y 8051 wakes up from idle mode and starts executing from where it left off ...
Page 164
... Default 0x00 D5-D1 Reserved, set to “0” 0=8051 Clock can run 1=8051 Clock stop The FDC37N958FR is fully static and will pickup from where it left off in the event of a wake-up event. Idle Mode Entering IDLE mode: Idle mode is initiated by an instruction that sets the PCON ...
Page 165
... RESET_OUT=low, 8051STP_CLK=0. FIGURE 12 - ENTERING IDLE MODE SMSC DS – FDC37N958FR System fully powered up and running. 8051 owns Flash interface, running keyboard code. The host either issues a user- defined command to put the 8051into idle mode, or the 8051 code determines that the 8051 should enter Idle mode ...
Page 166
... First, activation of any enabled interrupt will cause the PCON.0 bit to be cleared by hardware. The interrupt will be serviced and, following the RETI, the CPU will SMSC DS – FDC37N958FR Note: In order to leave idle mode the 8051 must receive an interrupt, typically a software timer interrupt will be used. Y operation by executing the instruction following the one that put the CPU into Idle mode ...
Page 167
... If an external crystal is used, the internal oscillator is turned off. RAM contents are preserved. SMSC DS – FDC37N958FR Design Note In this mode, the FDC, UART1, UART2 and parallel port are powered off if VCC2 is removed, but the RTC and 8051 are in powerdown (sleep) mode ...
Page 168
... FIGURE 14 - ENTERING SLEEP MODE SMSC DS – FDC37N958FR System fully powered up and running. RESET_OUT= low, 8051STP_CLK= 0. 8051 owns Flash interface, running keyboard code. The host either issues a user- defined command to put the 8051into sleep mode, or the 8051 code determines that the 8051 should enter sleep mode ...
Page 169
... Idle mode, executes T5INT service routine (disables T5INT) and executes an IRET when 8051 returns to executing from where it left off prior to entering sleep mode. FIGURE 15 - EXITING SLEEP MODE SMSC DS – FDC37N958FR Wake Up Events RTC Alarm, Unmasked Power Button, Wake-up Ring Indicator, Event ? etc ...
Page 170
... WK_HL6 WK_EE4 WK_EE4 N/A WK_ANYKEY (function of KSI[7:0] pins) GPIO8/COM- WK_HL7 RX [IR_WAKEUP] IRRX WK_HL8 [IR_WAKEUP] SMSC DS – FDC37N958FR LEVEL/EDGE INTERNAL OR SENSITIVE EXTERNAL Edge, high-to-low External Edge, high-to-low External Edge, high-to-low External Edge, high-to-low External Leading edge, Internal high-to-low ...
Page 171
... UART_ WK_EE4 RI2 RI1 occurs occurs Note: All the bits in this register are cleared on a read of this register. HTIMER Interrupt -- When HTIMER=1, the hibernation timer counted down to “0”. SMSC DS – FDC37N958FR WAKEUP SOURCE REGISTER 1 Host N/A 8051 0x7F2A (R) Power VCC1 Default ...
Page 172
... WK_ANYKEY function. WK_ANYKEY = !(KSI0 & KSI1 & KSI2 & KSI3 & KSI4 & KSI5 & KSI6 & KSI7) Note 2: IR Receive Activity Wake-up Events -- On the FDC37N958FR, GPIO8 or IRRX may be configured as an Infared receive pin. available on each of these pins. When un-masked, a high-to-low edge transition on either of these pins will generate an 8051 wake-up event ...
Page 173
... Hibernation Timer - This 8 bit binary count-down timer can be programmed for from 30 seconds to 128 minutes in 30 second increments. When it expires (reaches “0”), it stops (remains at “0”) and causes a hardware event that will wake up SMSC DS – FDC37N958FR WAKEUP MASK REGISTER 2 Host N/A 8051 ...
Page 174
... Added features include two high-drive serial interfaces, and additional interrupt sources. The FDC37N958FR provides an industry standard 8042-style host interface to the 80C51 to emulate standard 8042 keyboard controller and Table 59 - Keyboard Controller ISA I/O Address Map ISA ADDRESS NIOW ...
Page 175
... Buffer, set the OBF flag and set the PCOBF output if enabled. A read of this register by the The host CPU sends commands to the keyboard controller by writing command bytes to ISA port 0x64. SMSC DS – FDC37N958FR also sets PCOBF. A write to 7FFAH also sets AUXOBF1 . See Table 60 below. ...
Page 176
... Setting this flag activates the 8051's nIBF interrupt if enabled. When the 8051 reads the input data register, this bit is automatically reset and the interrupt is cleared. There is no output pin associated with this internal signal. SMSC DS – FDC37N958FR HOST I/F STATUS REGISTER Host ISA 0x64 (R) 8051 ...
Page 177
... PCOBF will normally reflect the status of writes to 7FF1H, if PCOBFEN (bit 2 of Configuration register “0”) = “0”. (KIRQ is normally selected as IRQ1 for keyboard support.) PCOBF is cleared by hardware on a read of the Host Data Register. SMSC DS – FDC37N958FR PCOBF Host N/A 8051 0x7FFD Power ...
Page 178
... GATEA20 hardware speed- up feature. GATEA20 is part of the control required to mask address line A20 to emulate 8086 addressing. SMSC DS – FDC37N958FR On power-up, after VCC1 POR, AUXOBF1 is reset to 0. AUXOBF1 will normally reflects the status of writes to 7FFAH. (MIRQ is normally selected ...
Page 179
... Table 61). The foregoing description assumes that configuration bit is reset. When the FDC37N958FR receives a "D1" command followed by data (via the host interface), the on-chip hardware copies the value of data bit 1 in the received data field to SMSC DS – FDC37N958FR Table 62 - Register Bit Allocation ...
Page 180
... Anything except D1. If multiple data bytes, set IBF and wait at state 0. Let the software know something unusual happened. For data bytes SA2=0, only D[1] is used; all other bits are don't care. SMSC DS – FDC37N958FR IBF GATEA20 0 Q GATEA20 Turn-on Sequence ...
Page 181
... Refer to the GATEA20 Hardware Speed-up description for information on this register. A write to this register sets GateA20. Refer to the GATEA20 Hardware Speed-up description for information on this register. A write to this register re-sets GateA20. SMSC DS – FDC37N958FR 8051 GATEA20 Control Registers GATEA20 Host N/A ...
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... CPU_RESET Hardware Speed-Up The ALT_CPU_RESET bit generates, under program control, the nALT_RST signal which provides an alternate means to drive the FDC37N958FR CPU_RESET pin which in turn is used to reset the Host CPU. The nALT_RST signal is internally NANDed together with the nKBDRESET pulse from the KRESET Speed up logic to provide an alternate software means of SMSC DS – ...
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... FE Command KRESET From Pulse KRESET Gen Speed up Logic ENAB_P92 Port92 Reg Bit 0 Pulse Gen FIGURE 17 - CPU_RESET IMPLEMENTATION DIAGRAM SMSC DS – FDC37N958FR 6us SAEN nALT_RST 14 us 6us Page 177 CPU_RESET Rev. 09/01/99 ...
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... Port 92 The FDC37N958FR supports ISA I/O writes to port 92h as a quick alternate mechanism PORT 92 REGISTER DESCRIPTION Host R/W Bit Def Reserved The Port92h register resides at ISA address 0x92 and is used to support the alternate reset (nALT_RST) and alternate GATEA20 (ALT_A20) functions. This register defaults to 0x00 on assertion of RESET_OUT or on VCC2 Power On Reset ...
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... The value of the KSI[x] pins can be read through this register. The pin values are latched during the read. SMSC DS – FDC37N958FR management in computer applications. properly configuring GPIO4 and GPIO5, the FDC37N958FR may be programmed to directly keyboard control keyboard interface matrixes 16x8. Host ...
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... Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the FDC37N958FR provides four pairs of signal pins that may be used to implement this interface directly for an external keyboard and mouse. The FDC37N958FR has four high-drive, open- drain output (external pull-ups are required), SMSC DS – ...
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... Mailbox Register Interface The FDC37N958FR provides a set bit registers, called mailbox registers, by which the Host CPU may communicate with the 8051. These registers are accessible to the host in configuration Mode or through the open mode Index and Data Registers also described in Configuration section. ...
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... MAILBOX REGISTER 1 If enabled by ESMI register, an SMI will be generated when the 8051 writes to this register. The SMI interrupt will be cleared when the Host reads this register. After reading this register the SMSC DS – FDC37N958FR System-to-8051 8051-to-System 14, 8 bit Mailbox ...
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... MAILBOX SMI INTERRUPT The host can enable/disable SMI interrupts generated as a result of the 8051 writing to Mailbox Register 1. The Host can read the ESMI source register FDC37N958FR Mailbox Interface was the cause of the SMI. ESMI MASK REGISTER Host IDX 0x97 (R) 8051 N/A ...
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... PS/2 Reserved Reserved port2 Only one of bits 2-0 can be set to one. Host 8051 Power Default Reserved Reserved PS/2 port1 PS/2 Reserved Reserved port2 SMSC DS – FDC37N958FR Port 1 Port 2 N/A N/A 0x7F41 0x7F49 VCC2 VCC2 0x00 0x00 R/W R/W Reserved EM_EN KB_EN Reserved IM_EN PS2_EN ...
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... Default D7 R/W W Host 8051 Power Default ACCESS.bus Interface Description The ACCESS.Bus interface is fully and directly controlled by the on-chip 8051 through its set of on-chip memory mapped control registers. The SMSC DS – FDC37N958FR Port 1 Port 2 N/A N/A 0x7F43 (R) 0x7F4B (R) VCC2 VCC2 0x00 0x00 ...
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... Busy), nBB is not affected. This is a self-clearing bit. Writing this bit to a logic “0” has no effect. ACCESS.BUS STATUS REGISTER D7 8051 R/W R Bit Def PIN ACCESS.BUS OWN ADDRESS REGISTER D7 D6 8051 R/W R/W R/W Reserved Bit Slave Def Address 6 SMSC DS – FDC37N958FR Host N/A 8051 0x7F31 (W) Power VCC1 Default 0x00 Reserved Reserved ENI Host N/A 8051 ...
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... R/W R/W D7 8051 R/W R/W AB_RST* (*) ACCESS.bus Reset, not self-clearing, must be written high and then written low. Bit 7 AB_RST: (ACCESS.bus Reset) setting this bit re-initializes all logic and registers in the ACCESS.bus block. SMSC DS – FDC37N958FR ACCESS.BUS DATA REGISTER Host N/A 8051 0x7F33 Power VCC1 Default ...
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... CLOCK CLOCK RATE D[1:0] 00 Off 10 Ring Osc Ring Osc=4 MHz Ring Osc=6 MHz Ring Osc=8 MHz 10 12 MHz 10 14.3 MHz 10 16 MHz 11 24 MHz SMSC DS – FDC37N958FR DATA NOMINAL RATE HIGH f/240 96/f 144/f 16.7 KHz 24"s 36"s 25 KHz 16"s 24"s 33.3 KHz 12"s 18"s 50 KHz 8" ...
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... LED on time is T=125msec; “0” is on, “1” is off. Period “P” is indicated above. Note 2: This register is impacted by a device functional revision. ADDENDUM on page 308 for VCC1 and VCC2 POR impact and default values. T SMSC DS – FDC37N958FR The FDC37N958FR has three independent LED outputs that are programmable under 8051 control. LED Register Host ...
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... MHz is used 1111111 = pin is high for 127, low for 1 select 3 MHz RTCCNTRL (RTC CONTROL) REGISTER SMSC DS – FDC37N958FR The FDC37N958FR has two independent Pulse Width Modulator outputs that are programmable under 8051 control. PWM0 REGISTER Host IDX 0x92 8051 0x7F25 ...
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... The FDC37N958FR implements an interface that allows the 8051 to read/write the RTC and CMOS registers. When RESET_OUT is active nSH 0 0 nSH nSmart Host - This bit is controlled by the 8051. When set to a “1”, the host is not a smart host and does not recognize the sharing protocol. When set to a “0”, the host is smart and can recognize the sharing protocol. When set to “ ...
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... CMOS RAM registers for a total of 256 registers. RTC DATA REGISTER (HIGH AND LOW) The low register is used to access the first bank of 128 bytes, in CMOS RAM the high register is used to access the second bank of 128 SMSC DS – FDC37N958FR Host N/A 8051 0x7FF8 & 0x7FF6 ...
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... FIGURE 20 - PARALLEL PORT MULTIPLEXOR From/to Host Parallel Port Interface From/to 8051 Parallel port interface PP_HA SMSC DS – FDC37N958FR parallel port registers (Status, Control, and Data) with the exception that the 8051’s Parallel Port Status register contains a write bit (bit 0) that allows the 8051 to disconnect the interface from the host and take control ...
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... Bit D7 (nBUSY): reflects the inverse state of pin BUSY Bit D6 (nACK): Bit D5 (PE): Bit D4 (SLCT): Bit D3 (nERR): SMSC DS – FDC37N958FR The 8051 uses the following three memory mapped registers to gain access to and control the parallel port interface. Host N/A 8051 ...