X25640S Xicor, X25640S Datasheet

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X25640S

Manufacturer Part Number
X25640S
Description
64K (8K x 8bit) Advanced SPI serial E2PROM with block lock protection
Manufacturer
Xicor
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
X25640S
Manufacturer:
XICOR
Quantity:
20 000
X25640
64K
FEATURES
FUNCTIONAL DIAGRAM
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3089-1.8 6/17/96 T4/C4/D1 NS
1MHz Clock Rate
Low Power CMOS
—200 A Standby Current
—5mA Active Current
5 Volt Power Supply
SPI Modes (0,0 & 1,1)
8K X 8 Bits
—32 Byte Page Mode
Block Lock Protection
—Protect 1/4, 1/2 or all of E
Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
8-Lead PDlP Package
14-Lead SOIC Package
AN19 • AN38 • AN41 • AN61
A V A I L A B L E
Advanced SPI Serial E
HOLD
A
SCK
PPLICATION
WP
SO
CS
SI
N
OTES
COMMAND
REGISTER
CONTROL
CONTROL
DECODE
STATUS
TIMING
WRITE
LOGIC
LOGIC
AND
AND
2
PROM Array
PROTECT
WRITE
LOGIC
2
PROM With Block Lock
X25640
1
DESCRIPTION
The X25640 is a CMOS 65,536-bit serial E
internally organized as 8K x 8. The X25640 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25640 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25640 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The WP input can be used as a hardwire input
to the X25640 disabling all write attempts to the status
register, thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25640 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
X DECODE
LOGIC
128
64
64
32
TM
DATA REGISTER
Characteristics subject to change without notice
Y DECODE
128 X 256
8K BYTE
Protection
64 X 256
64 X 256
ARRAY
8
8K x 8 Bit
3089 ILL F01
2
PROM,

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X25640S Summary of contents

Page 1

... LOGIC HOLD WRITE CONTROL AND TIMING WP LOGIC Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc. ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 3089-1.8 6/17/96 T4/C4/D1 NS X25640 2 PROM With Block Lock DESCRIPTION The X25640 is a CMOS 65,536-bit serial E internally organized The X25640 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus ...

Page 2

X25640 PIN DESCRIPTIONS Serial Output (SO push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) ...

Page 3

X25640 PRINCIPLES OF OPERATION 2 The X25640 PROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25640 contains an 8-bit instruction register accessed ...

Page 4

X25640 Write-Protect Enable The Write-Protect-Enable (WPEN) is available for the X25640 as a nonvolatile enable bit for the WP pin. Protected Unprotected Status WPEN WP WEL Blocks Protected Protected Protected 1 LOW 0 Protected ...

Page 5

X25640 Operational Notes The X25640 powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition required to enter an active state and receive an instruction. • ...

Page 6

X25640 Figure 3. Write Enable Latch Sequence CS SCK SI SO Figure 4. Byte Write Operation Sequence SCK INSTRUCTION SI HIGH IMPEDANCE HIGH IMPEDANCE ...

Page 7

X25640 Figure 5. Page Write Operation Sequence SCK INSTRUCTION SCK DATA BYTE Figure 6. Write Status Register ...

Page 8

X25640 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. – +135 C Storage Temperature ....................... – +150 C Voltage on any Pin with Respect to V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. ...

Page 9

X25640 EQUIVALENT A.C. LOAD CIRCUIT 2.16K OUTPUT 3.07K A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Data Input Timing Symbol Parameter f Clock Frequency SCK t Cycle Time CYC CS Lead Time t LEAD CS Lag Time ...

Page 10

X25640 Serial Output Timing CS SCK MSB OUT ADDR SI LSB IN Serial Input Timing CS t LEAD SCK MSB IN HIGH IMPEDANCE CYC MSB–1 OUT t t ...

Page 11

X25640 Hold Timing CS SCK SO SI HOLD 3089 ILL F12.1 ...

Page 12

X25640 PACKAGING INFORMATION HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 ...

Page 13

X25640 PACKAGING INFORMATION 14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S PIN 1 INDEX PIN 1 0.014 (0.35) 0.020 (0.51) (4X) 7 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0 – 8 0.016 (0.41) 0.037 (0.937) NOTE: ALL DIMENSIONS IN ...

Page 14

... LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ...

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