ML6696CQ Micro Linear, ML6696CQ Datasheet

no-image

ML6696CQ

Manufacturer Part Number
ML6696CQ
Description
100BASE-X fiber physical layer
Manufacturer
Micro Linear
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ML6696CQ
Manufacturer:
ML
Quantity:
831
GENERAL DESCRIPTION
The ML6696 implements the complete physical layer of
the Fast Ethernet 100BASE-X standard for fiber media. The
device provides the MII (Media Independent Interface) for
interface to upper-layer silicon. The ML6696 integrates the
data quantizer and the LED driver, allowing the use of
low cost optical PMD components.
The ML6696 includes 4B/5B encoder/decoder, 125MHz
clock recovery/clock generation, LED driver, and a data
quantizer. The device also offers a power down mode
which results in total power consumption of less than 20mA.
The ML6696 is suitable for the current 100BASE-FX IEEE
803.2u standard defined using 1300nm optics, as well as
for the proposed 100BASE-SX standard defined using lower
cost 820nm optics
BLOCK DIAGRAM
CLKREF
TXCLK
TXER
TXEN
TXD3
TXD2
TXD1
TXD0
MDC
MDIO
COL
CRS
RXCLK
RXER
RXDV
RXD3
RXD2
RXD1
RXD0
CARRIER & COLLISION
4B/5B ENCODER
4B/5B DECODER
TRANSMIT
MACHINE
MACHINE
RECEIVE
LOGIC
STATE
STATE
AND
AND
PCS
PCS
DESERIALIZER
100BASE-X Fiber Physical Layer
INITIALIZATION
MANAGEMENT
SYNTHESIZER
NRZ TO NRZI
SERIALIZER
INTERFACE
INTERFACE
MII SERIAL
ENCODER
CLOCK
FEATURES
* Some Packages Are Obsolete
100BASE-FX physical layer with MII
Optimal 100BASE-SX solution (draft standard)
Integrated data quantizer (post-amplifier)
Integrated LED driver
125MHz clock generation and recovery
4B/5B encoding/decoding
Power-down mode
CLOCK & DATA
NRZI TO NRZ
RECOVERY
ENCODER
DRIVER
DATA QUANTIZER
(POST AMPLIFIER)
LED
CAPB
CAPDC
ML6696*
December 1998
LINK100
EDOUT
RTSET
IOUT
IOUT
EDIN
V IN+
ECLK
V IN–
1

Related parts for ML6696CQ

ML6696CQ Summary of contents

Page 1

GENERAL DESCRIPTION The ML6696 implements the complete physical layer of the Fast Ethernet 100BASE-X standard for fiber media. The device provides the MII (Media Independent Interface) for interface to upper-layer silicon. The ML6696 integrates the data quantizer and the LED ...

Page 2

ML6696 PIN CONFIGURATION TXCLK 1 RXD3 2 DGND1 3 DGND1 4 DGND1 5 RXD2 RXD1 8 DGND2 9 DGND2 10 DGND2 11 RXD0 12 RXCLK 13 CRS 14 COL 15 DGND3 16 2 ML6696 52-Pin ...

Page 3

PIN DESCRIPTION (Pin Number in Parentheses is for PLCC Version) PIN NAME FUNCTION 1 (9) TXCLK Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ...

Page 4

ML6696 PIN DESCRIPTION (Pin Number in Parentheses is for PLCC Version) (Continued) PIN NAME FUNCTION 30 (32) CAPB Data quantizer input bias bypass capacitor input. The capacitor tied between this pin and AV the quantizer’s internal input bias reference. A ...

Page 5

PIN DESCRIPTION (Pin Number in Parentheses is for PLCC Version) (Continued) PIN NAME FUNCTION 60 (4) TXD2 Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on ...

Page 6

ML6696 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. V Supply Voltage Range ............................ –0. ...

Page 7

DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TRANSMITTER (IOUT, IOUT) I IOUT High Output Current LEDH I Low Output Current LEDL I RTSET Input Current RT POWER SUPPLY CURRENT I Supply Current, 100BASE-FX, Transmitting CC I Supply Current, Power-Down Mode CCPD AC ...

Page 8

ML6696 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER MII MANAGEMENT INTERFACE (MDC, MDIO) t Write Setup Time, MDIO Data Valid SPWS to MDC Rising Edge (1.4V Point) t Write Hold Time, MDIO Data Valid SPWH After MDC Rising Edge (1.4V Point) t ...

Page 9

TXCLKIN TXCLK TXD<3:0> TXER TXEN t TPS Figure 1. MII Transmit Timing RXCLK RXD<3:0> RXER RXDV t RCS Figure 2. MII Receive Timing MDC MDIO t SPWS Figure 3. MII Management Interface Write Timing t t TPWH TPWL t TPH ...

Page 10

ML6696 MDC MDIO Figure 4. MII Management Interface Read Timing ECLK 01 02 (DRIVEN BY ML6696) EDIN (DRIVEN BY ML6696) SB OP1 1 1 EDOUT (DRIVEN BY EEPROM) Figure 6. MII Management Interface Read Timing 10 t SPRH t t ...

Page 11

FUNCTIONAL DESCRIPTION FIBER OPTIC TRANSMITTER The on-chip transmit PLL converts a 25MHz TTL-level clock at CLKREF to an internal 125MHz bit clock. TXCLK from the ML6696 clocks transmit data from the MAC into the ML6696’s TXD<3:0> input pins upon assertion ...

Page 12

ML6696 EDIN MODE Floating (EEPROM ADDR) EEPROM High Microcontroller Low Hardwired BIT(S) NAME DESCRIPTION i.15 PHY A4 PHY address bit 4 i.14 PHY A3 PHY address bit 3 i.13 PHY A2 PHY address bit 2 i.12 PHY A1 PHY address ...

Page 13

BIT(S) NAME DESCRIPTION 1.14 100BASE-X 1=Full duplex 100BASE-X capability Full Duplex 0=No full duplex 100BASE-X capability 1.13 100BASE-X 1=Half duplex 100BASE-X capability Half Duplex 0=No half duplex 100BASE-X capability 1.12-1.3 Not used 1.2 Link Status 1=One and only one PHY-specific ...

Page 14

... GND OUT AV CC C10 0.1µF TXER TXCLK RXD3 DGND1 RXD2 C17 0.1µF U3 RXD1 ML6696CQ DGND2 RXD0 RXCLK CRS COL DGND3 C16 0.1µ C15 0.1µF 0.1µ FX_TXLED 74HC04 ...

Page 15

PHYSICAL DIMENSIONS 0.785 - 0.795 (19.94 - 20.19) 0.750 - 0.754 (19.05 - 19.15) 1 PIN 1 ID 0.042 - 0.048 (1.07 - 1.22 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 ...

Page 16

... ML6696 ORDERING INFORMATION PART NUMBER ML6696CH (Obsolete) ML6696CQ © Micro Linear 2000 registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; ...

Related keywords