DS2188 Dallas Semiconductor, DS2188 Datasheet
DS2188
Specifications of DS2188
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DS2188 Summary of contents
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... DS2187 Receive Line Interface DESCRIPTION The DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with an external 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all of the latest applicable specifications including those outlined in TR 62411 (Accunet* T1.5 Service Description and Interface Specifications, December 1990), TR-TSY-000170 (Digital Cross-Connect System Requirements and Objectives, November 1985), and the CCITT Recommendations G ...
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... E1” for additional information. BUFFER DEPTH SELECT The buffer size on the DS2188 can be configured to either 128 or 32 bits via the BDS pin. If BDS is tied low, then the buffer depth will be 128 bits and hence can handle input jitter up to 120 UIpp without losing its full attenuation capabilities as is described above in the Over-view ...
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... DS2188 TI JITTER ATTENUATION PERFORMANCE Figure 1 DS2188 CEPT JITTER ATTENUATION PERFORMANCE Figure DS2188 ...
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... DS2188 IN THE RECEIVE PATH Figure 3 DS2188 IN THE TRANSMIT PATH Figure DS2188 ...
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... DS2188. Receive Reference Clock. Dejittered 1.544 MHz or 2.048 MHz O clock. Receive Reference Negative Data Output. Dejittered data output. O Updated on the rising edge of RRCLK. Receive Reference Positive Data Output. Dejittered data output. O Updated on the rising edge of RRCLK. - Positive Supply. 5.0 volts DS2188 ...
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... CRYSTAL REQUIREMENTS The DS2188 must have a crystal connected to the XTAL1 and XTAL2 pins. For T1 environments, the frequency of this crystal should be 6.176 MHz. For CEPT environments, the frequency of this crystal should be 8.192 MHz. Table 2 lists some suggested crystal manufacturers that are recommended for use with the DS2188. Also, see DS2188 Application Note, “ ...
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... MIN - 5.50; outputs open TYP MAX UNITS V +0 +0 TYP MAX UNITS 5.0V ± 10%) DD TYP MAX UNITS +1.0 µ DS2188 NOTES NOTES NOTES ...
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... The average period of RCLK must be within ±200 ppm of the fundamental frequency of the crystal divided by four. 2. Only valid when the incoming jitter is less than 120 Ulpp (BDS= Ulpp (BDS=1). SYMBOL MIN TYP -200 100 5.0V ± 10%) DD MAX UNITS +200 ppm µA DS2188 NOTES 1 2 ...
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... AC TIMING DIAGRAM Figure 5 NOTE: 1. The phase relationship between XTAL OUT and RRCLK can be of either form DS2188 ...
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... DS1288 T1/CEPT JITTER ATTENTUATOR 16-PIN DIP PKG 16-PIN DIM MIN MAX AIN 0.740 0.780 MM 18.80 19. 0.240 0.260 MM 6.10 6. 0.120 0.140 MM 3.05 3. 0.300 0.325 MM 7.62 8. 0.015 0.040 MM 0.38 1. 0.120 0.140 MM 3.04 1. 0.090 0.110 MM 2.29 2. 0.320 0.370 MM 8.13 9. 0.008 0.012 MM 0.20 0. 0.015 0.021 MM 0.38 0. DS2188 ...
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... DIM MIN MAX AIN 0.402 0.412 MM 10.21 10. 0.290 0.300 MM 7.37 7. 0.089 0.095 MM 2.26 2. 0.004 0.012 MM 0.102 0. 0.094 0.105 MM 2.38 2. 0.050 BSC MM 1.27 BSC H IN 0.398 0.416 MM 10.11 10. 0.009 0.013 MM 0.229 0. 0.013 0.019 MM 0.33 0. 0.016 0.40 MM 0.40 1.02 phi 0° 8° DS2188 ...