GM71C18163CJ-6 Hynix Semiconductor, GM71C18163CJ-6 Datasheet

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GM71C18163CJ-6

Manufacturer Part Number
GM71C18163CJ-6
Description
1,048,576 words x 16 bit CMOS DRAM, 60ns
Manufacturer
Hynix Semiconductor
Datasheet

Specifications of GM71C18163CJ-6

Dc
0112

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Pin Configuration
Rev 0.1 / Apr’01
Description
generation dynamic RAM organized 1,048,576
x 16 bit. GM71C(S)18163C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71C(S)18163C/CL offers
Extended Data out(EDO) Mode as a high speed
access mode. Multiplexed address inputs permit
the GM71C(S)18163C/CL to be packaged in
standard 400 mil 42pin plastic SOJ, and standard
400mil 44(50)pin plastic TSOP II. The package
size provides high system bit densities and is
compatible with widely available automated
testing and insertion equipment.
The GM71C(S)18163C/CL is the new
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
V
V
V
WE
NC
NC
NC
NC
A0
A3
A1
A2
CC
CC 6
CC 21
15
12
18
19
1
2
3
4
5
7
8
9
10
11
13
14
16
17
20
42 SOJ
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
I/O15
I/O14
I/O13
I/O12
V
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
SS
SS
(Top View)
Features
* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
* Low Power
* RAS Only Refresh, CAS before RAS Refresh,
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 1024 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-version)
* 2 CAS byte Control
Active : 1045/935/825mW (MAX)
Standby : 11mW (CMOS level : MAX)
Hidden Refresh Capability
GM71C(S)18163C/CL-5
GM71C(S)18163C/CL-6
GM71C(S)18163C/CL-7
44(50) TSOP II
RAS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
A11
A10
V
V
WE
V
NC
NC
NC
A0
A1
A2
A3
CC
CC
0.83mW (L-version : MAX)
CC
18
10
11
15
16
17
19
20
21
22
23
1
2
3
4
5
6
7
8
9
24
25
1,048,576 WORDS x 16 BIT
GM71CS18163CL
CMOS DYNAMIC RAM
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
GM71C18163C
t
RAC
50
60
70
V
I/O15
I/O14
I/O13
I/O12
V
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
SS
SS
t
CAC
13
15
18
104
124
t
84
(Unit: ns)
RC
t
HPC
20
25
30

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GM71C18163CJ-6 Summary of contents

Page 1

Description The GM71C(S)18163C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71C(S)18163C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)18163C/CL offers Extended Data out(EDO) Mode as a high ...

Page 2

Pin Description Pin A0-A9 Address Inputs A0-A9 Refresh Address Inputs I/O0-I/O15 Data Input/Data Output RAS Row Address Strobe UCAS, LCAS Column Address Strobe Ordering Information Type No. GM71C(S)18163CJ/CLJ -5 GM71C(S)18163CJ/CLJ -6 GM71C(S)18163CJ/CLJ -7 GM71C(S)18163CT/CLT -5 GM71C(S)18163CT/CLT -6 GM71C(S)18163CT/CLT -7 Absolute ...

Page 3

Recommended DC Operating Conditions (T Symbol V Supply Voltage CC V Input High Voltage IH V Input Low Voltage IL Note: All voltage referred to Vss. The supply voltage with all VCC pins must be on the same level. The ...

Page 4

DC Electrical Characteristics (V Symbol V Output Level OH Output "H" Level Voltage (I V Output Level OL Output "L" Level Voltage (I I Operating Current CC1 Average Power Supply Operating Current (RAS, UCAS or LCAS Cycling I Standby Current ...

Page 5

Capacitance (V = 5V+/-10 Symbol C Input Capacitance (Address Input Capacitance (Clocks Output Capacitance (Data-In/Out) I/O Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. LCAS and UCAS = V ...

Page 6

Read Cycle Symbol Parameter t Access Time from RAS RAC t Access Time from CAS CAC t Access Time from Address AA t Access Time from OE OAC t Read Command Setup Time RCS t Read Command Hold Time to ...

Page 7

Write Cycle Symbol Parameter Write Command Setup Time t WCS Write Command Hold Time t WCH Write Command Pulse Width Write Command to RAS Lead Time RWL t Write Command to CAS Lead Time CWL Data-in Setup ...

Page 8

EDO Page Mode Cycle Symbol Parameter t EDO Page Mode Cycle Time HPC EDO Page Mode RAS Pulse Width t RASP Access Time from CAS Precharge t ACP t RAS Hold Time from CAS Precharge RHCP t Output data Hold ...

Page 9

Self Refresh Mode ( L-version ) Symbol Parameter t RAS Pulse Width(Self-Refresh) RASS t RAS Precharge Time(Self-Refresh) RPS t CAS Hold Time(Self-Refresh) CHS Notes : 1. AC measurements assume initial pause of 200us is required after power ...

Page 10

These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t defines RAS pulse width in EDO mode cycles. RASP 17. Access time ...

Page 11

Package Dimension 42 SOJ 1.058(26.89) MAX 1.072(27.23) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 44(50) TSOP-II 0.820(20.82) MIN 0.830(21.08) MAX 0.012(0.30) MIN 0.017(0.45) MAX Rev 0.1 / Apr’01 0.128(3.25) MIN 0.148(3.75) MAX 0.026(0.66) MIN 0.032(0.81) MAX 0.037(0.95) MIN 0.041(1.05) MAX ...

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