PM73121-RI PMC-Sierra Inc, PM73121-RI Datasheet
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... Data Sheet PMC-980620 AAL1 Segmentation And Reassembly PMC-Sierra, Inc. Issue 3 PM73121 AAL1gator II Processor DATA SHEET Issue 3: January 1999 PM73121 AAL1gator II AAL1 SAR Processor ...
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... The AAL1gator II device contains SRTS logic that Bellcore holds the patent on. Please refer to the NOTE on PMC-Sierra, Inc. Issue 3 AAL1gator trademark of PMC-Sierra, Inc. AT& registered trademark of AT&T of their respective companies or organizations. page 172 for more information regarding Bellcore’s SRTS patent. PM73121 AAL1gator II AAL1 SAR Processor ...
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... Transmit UTOPIA ATM Timing: TATM_DATA Tq(max) from 12 ns. • TUTOPIA SPHY Timing: RPHY_DATA Tq(max) from 12 ns. • TUTOPIA MPHY Timing: RPHY_DATA Tq(max) from 12 ns. PM73121 AAL1gator II AAL1 SAR Processor Major Changes section 7.8.12 163. Appendix 29, 205. ...
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... In Absolute Maximum Ratings section, removed undershoot/ overshoot specification, and replaced with absolute maximum voltage range for TTL inputs. • Moved all timing requirements on external logic for RAM and Microprocessor interface from section 6.5 to section 8.11. PM73121 AAL1gator II AAL1 SAR Processor Major Changes (max)=420mA and TYPE1 ...
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... From Version To Version 04/17/98 Issue 1 01/21/98 04/17/98 PMC-Sierra, Inc. ,VVXH • Changed from WAC-121-A to PM73121. • Changed from User’s Manual to Long Form Data Sheet. • Deleted references to the BT_Mode and default mode. • Added PMC part numbers to page 12, Figure 7 on page • Under the “ ...
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... Under section 2.7 “SRTS and Transmit Line Interface Clock Configurations” on page 21, and section 3.1. “SRTS for the Transmit Side” added the NOTE regarding Bellcore’s SRTS patent. PM73121 AAL1gator II AAL1 SAR Processor Major Changes 103, changed 119, changed the Fc maximum ...
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... Table 4 on page 72, changed “SRTS_PORT(3:0)” to “SRTS_LINE(3:0)”. • Under section 3.8 “Memory Interface and Arbitration Controller (MIAC)” starting on page paragraph. • Added section 3.9 “Configuration”, on page PM73121 AAL1gator II AAL1 SAR Processor Major Changes . OAM Figure 23 on 25, step 9 on page 25, and ...
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... Added section 8.4 “External FIFO Application” starting on page 171. • Under section 8.5 “External SRTS-Based Clock Recovery Application”, on page PM73121 AAL1gator II AAL1 SAR Processor Major Changes 81, deleted the last two sentences from and the description 83. 96, changed the Maximum value of Tq 104, changed the Minimum value of and the corresponding table ...
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... Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Potential System Impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PM73121 Required Board Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 System Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 Replacing a TDM Digital Access Cross-connect System (DACS) with an ATM System . . . . . . . . . . . . . 10 1.2 Replacing a Multiplexer Level 1 to Level 3 (M13) with an ATM System . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 Access Multiplexer Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 Using the AAL1gator Enterprise ATM Switch Application System Features ...
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... Memory Interface and Arbitration Controller (MIAC 3.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.1 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2.2 Pinout Table 4.3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.3.1 UTOPIA Interface Signals 4.3.2 Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.3.3 T1/E1 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.3.4 Microprocessor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.3.5 JTAG and Process Test Signals PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor LL ...
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... Control Registers Summary 123 7.4 Control Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.4.1 DEVICE_REV 124 7.4.2 COMP_LIN_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.4.3 LIN_STR_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.5 Transmit Data Structures Summary 127 7.6 Transmit Data Structures Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.6.1 P_FILL_CHAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.6.2 T_ADD_QUEUE 128 7.6.3 T_SEQNUM_TBL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.6.4 T_COND_SIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.6.5 T_COND_DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor LLL ...
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... UDF-HS Mode SRTS-Based Clock Recovery Application for DS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 8.8 Interfacing with the Mitel MT8980 Digital Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 8.9 Interfacing with the ATM Cell Multiplexer (WAC-185-B- 183 8.10 Jitter Characteristics of Clock Synthesis Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8.10.1 Nominal T1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 8.10.2 Nominal E1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor LY ...
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... PMC-980620 8.10.3 SRTS T1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 8.10.4 SRTS E1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8.11 Timing Requirements On External Logic for RAM and Microprocessor Interface . . . . . . . . . . . . . . . . 194 Appendix A Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 A.1 Definitions 198 A.2 Signal Name Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 A.3 Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 A.4 Glossary of Abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Appendix B References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor Y ...
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... Figure 30. RUTOPIA End-of-Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 31. Cell Header Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 32. Fast SN Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 33. Receive Cell Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 34. Cell Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 35. T1 ESF SDF-MF Format of the R_DATA_BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 36 SDF-MF Format of R_DATA_BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 37. T1 SDF-FR Format of the R_DATA_BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor YL ...
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... Figure 73. Microprocessor Write Command Register Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 74. Microprocessor Read Command Register Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 75. Microprocessor Holdoff Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 76. Microprocessor Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 77. Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 78. Low-Speed SRTS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor YLL ...
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... Figure 108. Suggested AAL1gator II Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Figure 109. Address Buffer (FCT244) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 110. Bidirectional Data Latch (FCT646) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 111. RAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 112. RAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor YLLL ...
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... Table 25. Memory Interface System Clock Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 26. Recommended Worst-Case Parameters for Suggested Memory Interface . . . . . . . . . . . . . . . . . . . . . 195 Table 27. Prefixes and Associated Functional Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Table 28. Standard Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 29. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 PMC-Sierra, Inc. List of Tables PM73121 AAL1gator II AAL1 SAR Processor L[ ...
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... Provides partially filled cell generation with the length configurable on a per-VC basis. • Generates and transmits Synchronous Residual Time Stamp (SRTS) values for unstructured modes. • Built-in transmit line clock generation based on received SRTS values, receive line clock nominal frequency. PMC-Sierra, Inc. Description 16 (12 ns) SRAM. PM73121 AAL1gator II AAL1 SAR Processor ...
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... Counts cells received, dropped, lost, or misinserted per VC. • Counts cells with incorrect Sequence Number (SN) or incorrect Sequence Number Protection (SNP). • Counts underrun occurrences per VC. • Counts overrun occurrences per VC. • Counts pointer reframes and pointer parity errors per VC. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ...
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... Block (RUTOPIA) UTOPIA Interface AAL1gator II Address/Data (PM73121) Buffer Control Microprocessor Strobes Microprocessor Address and Data UTOPIA Interface AAL1gator II Address/Data (PM73121) Buffer Control Microprocessor Strobes Microprocessor Address and Data PM73121 AAL1gator II AAL1 SAR Processor Output to UTOPIA Input from UTOPIA SRAM Buffers SRAM Buffers ...
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... Data Sheet ,VVXH PMC-980620 NEW FEATURES Changes in the AAL1gator II (PM73121) version from the WAC-021-C-X version are as fol- lows: • After power-up, setting the CMD_REG_ATTN register bit (refer to device revision register to be loaded with code 121A • Supports the “Fast Algorithm” method for processing SNs, as specified in the ITU-T Recommendation I.363.1. • ...
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... PMC-Sierra, Inc. “T_CHAN_NO_SIG” on page “R_CHAN_NO_SIG” on page “R_INCORRECT_SNP Word Format” on “R_SEQUENCE_ERR Word Format” on page 81) page 83) page 83) page 87) section 7.4.2 “COMP_LIN_REG” starting on PM73121 AAL1gator II AAL1 SAR Processor “IDLE_CONFIG 136) is for 157) is for the ...
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... Word Format” on page “R_UNDERRUNS Word Format” on page “R_LOST_CELLS Word Format” on page “R_OVERRUNS Word Format” on page “R_POINTER_REFRAMES Word Format” on “R_PTR_PAR_ERR Word Format” on page “R_MISINSERTED Word Format” on page PM73121 AAL1gator II AAL1 SAR Processor 157), 139) 160) 161) 162) ...
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... The math table was modified to support E1 and T1 lines at the same time. This was required since the WAC-021-CX has a different math table for E1 lines than for T1 lines. The PM73121 can configure some lines in E1 mode and some lines in T1 mode result, only one math table is required and anyone using E1 SDF-MF mode needs to use the new math table. • ...
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... Provide a means to tristate TL_CLK to the PM73121. • Provide pads to terminate TL_CLK correctly when sourced by the PM73121. You may need to remove the termination used when the AAL1gator II does not source TL_CLK. • Be aware of any skew issues that may arise when the AAL1gator II sources the TL_CLK instead of being externally generated, such as an external clock multiplexer ...
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... These address pins work like an active low chip select but follow the MPHY timing. • In PHY mode, all TATM signals will become RPHY signals (/TATM_EN becomes RPHY_CLAV and /TATM_FULL becomes /RPHY_EN). All RATM signals will become TPHY signals (/RATM_EN becomes TPHY_CLAV and /RATM_EMPTY becomes / TPHY_EN). PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ...
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... T1 Service Fractional T1 Service Digital Data Service T1 Service Fractional T1 Service DDS Service Figure 4. Using the AAL1gator II as Part of a TDM DACS Replacement PMC-Sierra, Inc. TDM Backbone TDM DACS Circuit Emulation Card ATM DACS AAL1gator II (PM73121) PM73121 AAL1gator II AAL1 SAR Processor ATM Backbone ...
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... ATM DACS or an ATM M13 when the backbone is converted to ATM. T1 Line T1 Line T1 Line T1 QDSX TQUAD (PM4314) (PM4344) Figure 5. Using the AAL1gator II as Part of an M13 Replacement PMC-Sierra, Inc. PDH DS3 Line M13 ATM Cell S/UNI-PDH AAL1gator II Multiplexer (PM7345) (PM73121) (WAC-185-X) PM73121 AAL1gator II AAL1 SAR Processor ATM DS3 Line LIU ...
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... As Figure 6 shows, CAS signaling is needed to support a wide variety of legacy PBXs. Private Branch T1 Exchange (PBX) SONET Workstation Figure 6. Using the AAL1gator ATM Access Multiplexer Application PMC-Sierra, Inc. Circuit Emulation Card AAL1gator II (PM73121) OC-3 ATM Access Interface Multiplexer PM73121 AAL1gator II AAL1 SAR Processor ATM Service S/UNI-LITE PM5346 ...
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... Table (WAC-187-X) ATM Switch ATM Switch Element Element (WAC-188-X) (WAC-188-X) ATM ATM Cell Routing Multiplexer Table (PM73121) (WAC-185-X) (WAC-187-X) PM73121 AAL1gator II AAL1 SAR Processor LAN Interface ATM Routing Table (WAC-187-X) ATM Switch Element (WAC-188-X) S/UNI- ULTRA (PM5350) ATM Switch Element UTP-PHY ...
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... Because of its extensive support of Digital Signal Level 0s PMC-Sierra, Inc. Corresponding AAL1gator II Channelization Mode UDF-ML No UDF-HS No SDF-MF Yes SDF-FR Yes section 3.2 “Cell Service Decision 33) is also simplified. Since there can be only eight queues, the PM73121 AAL1gator II AAL1 SAR Processor CAS Number of Signaling Lines Yes ...
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... VCI HEC HEC SN SNP CSI SN Payload 1 Pointer Payload 2 Payload Payload 42 Payload 47 Partially Filled Cell with Pointer 42 Payload Bytes PM73121 AAL1gator II AAL1 SAR Processor VPI GFC/VPI VPI VCI VPI VCI VCI PTI CLP VCI PTI HEC SNP CSI SN SNP Payload 1 Payload ...
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... Compatible with the ATM Forum Circuit Emulation Service (CES) standard (refer to Appendix B, “References”, on page PMC-Sierra, Inc. VPI GFC/VPI VCI VPI VCI VCI PTI CLP VCI HEC HEC SNP CSI SN Payload 1 Payload Payload 42 Partial Cell without Pointer 203). PM73121 AAL1gator II AAL1 SAR Processor VPI VCI PTI CLP SNP ...
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... Provides a supervisory transmit buffer for OAM/signaling with Cyclic Redundancy Check-10 (CRC-10) generation. • Generates sequence numbers and sequence number protection bits. • Provides partially filled cells with lengths configured on a per-VC basis. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor 16 SRAM external to the device. ...
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... Recommendation I.363.1. (refer to • Processes sequence numbers in accordance with I.363.1 “Fast SN Algorithm” (refer to Appendix B, “References”, on page disabled on a per queue basis. PMC-Sierra, Inc. Appendix B, “References”, on page 203). Sequence number processing can optionally be PM73121 AAL1gator II AAL1 SAR Processor 203). ...
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... Count of billable data cells received from the UTOPIA interface. 256 Count of cells that were received but dropped. 256 Count of the number of underruns on this queue to account for lost cells. 256 Count of cells detected lost for this queue. 256 Count of overruns on this queue. PM73121 AAL1gator II AAL1 SAR Processor ...
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... Counts data conditioned cells transmitted to the UTOPIA interface. 256 Counts cells not sent because of a line resynchronization, or, if the device was in UDF-HS mode, because TX_ACTIVE is set. Also if SUPPRESS_TRANSMISSION is set, any cells not sent will increment this counter. 158): PM73121 AAL1gator II AAL1 SAR Processor ...
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... The PCR numbers are per line, and • The SYS_CLK is 38.88 MHz. 2.8.1 Peak Cell Rates (PCRs) for Structured Cell Formats • PCR 176 n cells per second where 1 PMC-Sierra, Inc. for additional information regarding Bellcore’s SRTS patent (assuming completely filled cells). PM73121 AAL1gator II AAL1 SAR Processor 165. ...
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... data bytes per cell N = number of timeslots assigned to queue L = length of clock cycle NOTE: If OAM cells are used, add the following equation for the OAM cells: TCGT = 212 L (maximum number of OAM cells per second) OAM PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ...
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... The sum of TCGT + TCGT SDFMFE1 TCGT must be less than 1 second. OAM PMC-Sierra, Inc. L (8000 N 33 32) K (8000 N 49 48) K (8000 N) K (8000 32 TCGT + TCGT SDFMFT1 SDFFR PM73121 AAL1gator II AAL1 SAR Processor for all queues + UDFML ...
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... Layer Processor (TALP) 5 Memory Interface and Arbitration Controller To External Memory (MIAC) Receive Adaptation Layer Processor (RALP) 8 Microprocessor Control Bus PM73121 AAL1gator II AAL1 SAR Processor AAL1gator II (PM73121) Transmit UTOPIA Interface Output to UTOPIA Block (TUTOPIA) 6 Receive UTOPIA Interface Input from UTOPIA Block (RUTOPIA) 7 ...
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... The AAL1gator II reads the signaling nibble for each channel when it reads the last nibble of each channel’s data. See Figure 11 on page 26 for an example frame. PMC-Sierra, Inc. for an example frame. See PM73121 AAL1gator II AAL1 SAR Processor Figure 12 on page 26 ...
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... ABCD ABCD XXXX ABCD ... ... XXXX Channel 2 Channel 21 Line Signals During the Last Frame of a Multiframe ... 2 29 ABCD ABCD XXXX ABCD ... ... XXXX Channel 2 Channel 29 PM73121 AAL1gator II AAL1 SAR Processor 22 23 ABCD XXXX Channel 22 Channel ABCD XXXX Channel 30 Channel 31 ...
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... PMC-Sierra, Inc. Line 0 ATTN0 DATA0 Line Encoder Interface • • 16 • Line-to-Memory Line 7 ATTN7 Interface DATA7 16 section 7.6.6 “RESERVED (Transmit Signaling PM73121 AAL1gator II AAL1 SAR Processor 3 Line Number ANY 4 Channel Pair Number Interface 16 Data ...
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... Figure 15 SDF-MF Format of the T_DATA_BUFFER PMC-Sierra, Inc. DS0s MF0 23 32 MF1 55 64 MF2 87 96 MF3 119 127 DS0s MF0 11 12 MF1 23 32 MF2 43 44 MF3 55 64 MF4 75 76 MF5 87 96 MF6 107 108 MF7 119 PM73121 AAL1gator II AAL1 SAR Processor ...
Page 46
... Figure 16. T1 SDF-FR Format of the T_DATA_BUFFER PMC-Sierra, Inc. 0 DS0s 0 Frame 0 Frame 1 • • • Frame 23 32 Frame 24 Frame 25 • • • Frame 47 64 Frame 48 Frame 49 • • • Frame 71 96 Frame 72 Frame 73 • • • Frame 95 127 PM73121 AAL1gator II AAL1 SAR Processor 31 ...
Page 47
... Frame Buffer Number Figure 18. E1 SDF-MF with T1 Signaling Format of T_DATA_BUFFER PMC-Sierra, Inc. 0 DS0s 0 MF0 15 16 MF1 31 32 MF2 48 MF3 64 MF4 80 MF5 96 MF6 112 MF7 127 DS0s MF0 23 32 MF1 55 64 MF2 87 96 MF3 119 127 PM73121 AAL1gator II AAL1 SAR Processor 31 ...
Page 48
... Frame Buffer Number 0 127 Figure 20. Unstructured Format of the T_DATA_BUFFER PMC-Sierra, Inc. DS0s 31 0 Frame 0 Frame 1 Frame 2 • • • Frame 127 Data Bits 255 0 256-Bit Internal Frame 0 256-Bit Internal Frame 1 • • • 256-Bit Internal Frame 127 PM73121 AAL1gator II AAL1 SAR Processor ...
Page 49
... CH30 CH31 38 directed to build cells from the condi- for additional information regarding Bellcore’s SRTS patent. PM73121 AAL1gator II AAL1 SAR Processor section 3.3 “Trans- ...
Page 50
... UDF Latch Divide By 3008 Arm Input Reference Clock Frequency N_CLK (For T1/E1, 2.43 MHz. For T3, 77.76 MHz.) Figure 23 on page 35) describe how the CSD circuit schedules PM73121 AAL1gator II AAL1 SAR Processor RL_CLK > 4-bit SRTS Code 4-Bit Latch 4 Bits 4 Bits 4-Bit Counter ...
Page 51
... After servicing all the queues for that frame, the CSD circuit advances to the next active line located in the line queue. If there are no active lines, the CSD circuit returns to the idle state to wait for the next line to request service. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ...
Page 52
... Therefore, the next cell will be sent nine frames ahead of the current cell. Next frame = present frame number 9 PMC-Sierra, Inc. TFTC FR_ADVANCE_FIFO The TFTC sees frame advance and records this in the FR_ADVANCE_FIFO PM73121 AAL1gator II AAL1 SAR Processor CSD The CSD reads Set frame advances NEXT_ and determines SERV ...
Page 53
... Unstructured lines use the same procedure. In the case of unstructured lines, the number of chan- nels allocated to the queue is 32. Because there is never a pointer, the average number of credits spent per cell is always 47. PMC-Sierra, Inc 10, or three-eighths of a multiframe, remainder 1. 0.5 bytes per channel = 2 bytes PM73121 AAL1gator II AAL1 SAR Processor ...
Page 54
... E1 frames (for T1), this equates (for E1 (for T1). Queues should be added more than 16 ms apart (for E1 (for T1) to prevent them from being clumped together. Avoid configurations that will require sending a cell every n frames where integer divi- PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ...
Page 55
... CRC circuit that monitors the OAM cell sent to the TUTOPIA and computes the CRC on the fly. It then substitutes the 10-bit resultant CRC, preceded by six 0s, for the last two bytes of the cell. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor section 7.9 “ ...
Page 56
... This algorithm supplies a constant number of structure pointers and, therefore, data bytes, regardless of the structure size. The pointer is inserted in the seventh byte location of the cell. To force the TALP to build a structure consisting of a single DS0 with no signaling nibble and PMC-Sierra, Inc. section 7.6.8 “T_QUEUE_TBL” on page PM73121 AAL1gator II AAL1 SAR Processor 134). It will then ...
Page 57
... This process proceeds byte-by-byte until one of the following occurs: • The cell is complete. • All signaling nibbles for all channels assigned to the queue have been sent. PMC-Sierra, Inc. section 7.6.8 “T_QUEUE_TBL” on page PM73121 AAL1gator II AAL1 SAR Processor 134) determines ...
Page 58
... UTOPIA bus. The device will not assert the /TATM_EN signal until it has a full cell to send. PMC-Sierra, Inc. Channel T_DATA_BUFFER Figure 24. Payload Generation Figure 10 on page 24) conveys the cells emitted by the TALP to PM73121 AAL1gator II AAL1 SAR Processor TALP builds (segments) cell from T_DATA_BUFFER. In this case from DS0s 6 and 7. “PHY_ Appendix B, “Ref- ...
Page 59
... In SPHY mode, data is placed on RPHY_DATA any cycle following one in which /RPHY_EN was asserted. In MPHY mode, in PMC-Sierra, Inc. Figure 25 on page 42 PM73121 AAL1gator II AAL1 SAR Processor 06 07 ”, “17 ”, “1B ”, “1D ” ...
Page 60
... FULL(/RPHY_EN) for up to 128 line interface frames, but this would cause excessive CDV. The TALP circuit writes cells one byte at a time into the FIFO. The SOC is also placed into the FIFO. PMC-Sierra, Inc. Figure 26 on page 43 D49 D50 D51 PM73121 AAL1gator II AAL1 SAR Processor and Figure ...
Page 61
... See Figure 28 for the RUTOPIA timing diagram. RATM_CLK(i) /RATM_EMPTY(i) RATM_DATA(i) RATM_SOC(i) /RATM_EN(o) Figure 28. Receive UTOPIA Timing (ATM Mode) PMC-Sierra, Inc. Appendix B, “References” PM73121 AAL1gator II AAL1 SAR Processor ...
Page 62
... If a new TPHY_SOC occurs within a cell, the counter reinitializes. This means that the corrupted cell will be dropped and the good cell will be received. A small interme- diate FIFO allows the interface to accept data at the maximum rate. If the FIFO fills, the TPHY_ PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ” ...
Page 63
... OAM queue and are stored using the pointers located in the OAM receive queue table. The head pointer is the address to the first cell received for each queue, and is usually maintained PMC-Sierra, Inc D49 D50 D51 D52 PM73121 AAL1gator II AAL1 SAR Processor D3 D D53 ...
Page 64
... VPI Data Line Queue MOD 32 Figure 31. Cell Header Interpretation “R_INCORRECT_SNP Word Format” on page “DISABLE_SN” on page 160) has not been set for this queue, 155). PM73121 AAL1gator II AAL1 SAR Processor Ignored ...
Page 65
... The RALP will maintain bit integrity if there is no more than one consecutive errored cells there are up to six lost cells and the queue does not underrun. To maximize the tolerance of the RALP to errored cells, the R_CDVT and R_MAX_BUF values should be increased a little to PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor “ ...
Page 66
... SN is received, then the START state is re-entered and the cell is dropped. Otherwise, if the cell has a valid SN but is in the incorrect sequence, then the cell is dropped and the RALP remains in the OUT_OF_SYNC state. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor 160) is set SNP processing occurs. ...
Page 67
... Word Format” on page 161) is incremented and the SN_CELL_DROP sticky bit (refer to CELL_DROP” on page 158) is set. Anytime a cell is detected lost, the R_LOST_CELLS counter (refer to “R_LOST_CELLS Word Format” on page PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor “R_DROPPED_CELLS 162) is incremented by the number of lost “SN_ ...
Page 68
... SN/discard START valid SN/discard (unless invalid NODROP_IN_START is set) SN/discard out of seq/discard OUT OF SYNC seq/discard, force underrun in seq/accept invalid SN/accept in seq-1/discard SYNC in seq-1+1/accept in seq/accept Figure 32. Fast SN Algorithm PM73121 AAL1gator II AAL1 SAR Processor invalid SN/discard, force underrun out of INVALID ...
Page 69
... Correct SN/SNP as specified No in ITU-T Recommendation I.363.1 (refer to Appendix B “References” on page 203). Unable to correct Accept/drop cell as specified in ITU-T Recommendation No I.363.1 “Fast SN Algorithm” (refer to Appendix B “References” on page 203). Accept Figure 33. Receive Cell Processing PM73121 AAL1gator II AAL1 SAR Processor Drop ...
Page 70
... The RALP determines channels by reading from the R_CHAN_ALLOC table and then storing the data in the corresponding timeslots of successive frame buffers in the R_DATA_BUFFER. PMC-Sierra, Inc. R_DATA_BUFFER Channel Figure 34. Cell Reception PM73121 AAL1gator II AAL1 SAR Processor RFTC ...
Page 71
... This provides storage for 384 frames of T1 data. Frame Buffer Number Figure 36 SDF-MF Format of R_DATA_BUFFER PMC-Sierra, Inc. DS0 MF0 23 MF1 32 256 MF15 511 DS0 • • • 480 511 PM73121 AAL1gator II AAL1 SAR Processor 31 ...
Page 72
... Figure 38 shows the contents of the receive buffer with E1 data for lines in the SDF-MF mode. Frame Buffer Number Figure 38. E1 SDF-MF Format of the R_DATA_BUFFER PMC-Sierra, Inc. DS0 Frame 0 Frame 1 Frame Frame 24 Frame 47 • • Frame 360 Frame 383 511 DS0 496 MF 31 511 PM73121 AAL1gator II AAL1 SAR Processor ...
Page 73
... Figure 40 shows the contents of the receive data buffers with E1 data for lines in the SDF-FR mode. Frame Buffer Number Figure 40. E1 SDF-FR Format of the R_DATA_BUFFER PMC-Sierra, Inc. DS0 MF0 23 32 MF1 256 MF15 511 DS0 Frame 0 Frame 1 Frame 2 Frame 511 511 PM73121 AAL1gator II AAL1 SAR Processor ...
Page 74
... ABCD Multiframe 15 Figure 42. T1 ESF SDF-MF Format of the R_SIG_BUFFER PMC-Sierra, Inc. Data Bits 0 255 0 256 bits 1 256 bits 256 bits 2 256 bits 511 Byte Address Channel 24 Channel 23 Channel 22 Not Used ABCD ABCD PM73121 AAL1gator II AAL1 SAR Processor 31 Channel 31 Not Used ...
Page 75
... Figure 44. E1 SDF-MF Format of the R_SIG_BUFFER PMC-Sierra, Inc. Byte Address Channel 23 Channel 24 Channel 1 • • • ABAB Not Used ABAB Byte Address Channel 30 Channel 1 Channel 0 ABCD ABCD ABCD PM73121 AAL1gator II AAL1 SAR Processor 31 Channel 31 • • • Not Used Channel 31 ABCD ...
Page 76
... WITH_T1_SIG is set, then a T1 signaling structure is used. This means that for a single DS0, signaling is updated after 24 data bytes instead of after 16 data bytes. PMC-Sierra, Inc. Byte Address Channel 30 Channel 1 Channel 0 ABCD ABCD ABCD “E1_WITH_T1_SIG” on page 126). Normally the signaling PM73121 AAL1gator II AAL1 SAR Processor Channel 31 ABCD ...
Page 77
... The UNDERRUN sticky bit is set each time a cell is received during the underrun condition. Cells received while the pointer and start of structure are being located are PMC-Sierra, Inc. 157), then the queue is handled PM73121 AAL1gator II AAL1 SAR Processor ...
Page 78
... PTR_PARITY_ERR sticky bit will be set and the R_PTR_PAR_ERR counter will increment. If two consecutive pointer parity errors occur, then the RALP forces an underrun condition and resynchronizes. This resynchronization will cause R_POINTER_ REFRAMES to increment. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor that show how a start up after an underrun section 3 ...
Page 79
... Structure Found out-of-sequence or invalid cell received Pointer matches prediction and parity good (or not checking parity) PM73121 AAL1gator II AAL1 SAR Processor Pointer does not match prediction or underrun or force-underrun (or checking parity and One Mismatch (Signaling is not updated) 157) ...
Page 80
... NOTE: Inserting cells can cause an overrun. The threshold is checked as each byte is written into memory overflow occurs in the middle of a cell, the remainder of the cell will be dropped. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor Figure 47 on page 64 describes overrun “ ...
Page 81
... Write Pointer R_MAX_BUF Write Pointer (fixed) Write Pointer Read Pointer Write Pointer R_MAX_BUF R_CDVT Read Pointer R_MAX_BUF Old Location of Read Pointer R_CDVT Read Pointer = Underrun End Pointer Figure 47. Overrun Detection PM73121 AAL1gator II AAL1 SAR Processor Underrun End Pointer (fixed) Write Pointer ...
Page 82
... The RFTC outputs data to the external framer device. For structured data, the RFTC PMC-Sierra, Inc. “CMDREG Word Format” on page 163). section 7.9 “CMDREG (Command section 7.8.6 “R_CH_TO_QUEUE_TBL” on page PM73121 AAL1gator II AAL1 SAR Processor “R_ERROR_STKY Word 165) is set. The micro- 148). ...
Page 83
... Line Output Signals During Every Frame ... 2 21 ABCD ABCD XXXX ABCD ... ... XXXX Channel 2 Channel 21 Line Output Signals During Every Frame ... 2 29 ABCD ABCD XXXX ABCD ... ... XXXX Channel 2 Channel 29 PM73121 AAL1gator II AAL1 SAR Processor 22 23 ABCD XXXX Channel 22 Channel ABCD XXXX Channel 30 Channel 31 ...
Page 84
... PTR, then RFTC clears the R_RESUME bit. This occurs one CDVT time after the first valid cell arrives. If the line is in SDF_MF mode, then R_SIG_RESUME is set to indicate that signaling is not yet available. Once a multiframe has completed and signaling data is available, R_SIG_RESUME will be cleared. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ...
Page 85
... TL_CLK is an input. Or the AAL1gator II can generate it either by looping RL_ CLK, synthesizing a nominal clock, or synthesizing clock based on received SRTS values. PMC-Sierra, Inc. R_CH_TO_QUEUE 20 10 (Note 2) (Note 3) (Note 4) R_DATA_BUFFER (Note 5) R_COND_DATA (Note 6) PM73121 AAL1gator II AAL1 SAR Processor RFTC (Note 1) ...
Page 86
... SYS_CLK. Therefore ppm T1 clock is desired, SYS_CLK needs 38.88 MHz clock signal with 50 ppm accuracy. To lock the synthesized clock to a network clock, be sure SYS_CLK is derived from the network clock. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor 126). Once the LIN_STR_ “ ...
Page 87
... This interface is needed for high speed mode (E3 or DS3) SRTS PMC-Sierra, Inc. and section 8.10.2 “Nominal E1 Clock” for additional information regarding Bellcore’s SRTS patent. Figure 51 on page 71 shows the process implemented for section 6.7 “SRTS Timing” on page PM73121 AAL1gator II AAL1 SAR Processor TL_CLK > N_CLK > TL_ ...
Page 88
... DS0. The device does not support adaptive clocking in UDF-HS mode. PMC-Sierra, Inc. and section 8.10.4 “SRTS E1 Clock” on Remote 4-Bit SRTS SRTS-Code FIFO Queue Latch 4-Bit Latch 4 Bits 4-Bit Counter PM73121 AAL1gator II AAL1 SAR Processor Difference Between Remote SRTS Code and Local SRTS Code. 4 Bits Local 4-Bit SRTS Code ...
Page 89
... ADAP_STRB as each state is played out. Table 3. Channel Status SRTS_DOUT(3:0) Value line(2) channel(4) channel(3) channel(2) resume_h underrun_1 Table 4. Frame Difference SRTS_DOUT(3:0) Value 3 2 cell_vci(7) cell_vci(6) cell_vci(5) cell_vci(3) cell_vci(2) cell_vci(1) PM73121 AAL1gator II AAL1 SAR Processor Table line(1) line(0) channel(1) resume_1 1 0 cell_vci(4) cell_vci(0) ...
Page 90
... T1/E1 clock wan- der requirements. See Figure 52, which shows a direct adaptive clocking implementation. PMC-Sierra, Inc. SRTS_DOUT(3:0) Value frame_diff(8) frame_diff(5) frame_diff(4) frame_diff(1) frame_diff( PM73121 AAL1gator II AAL1 SAR Processor 0 frame_diff(7) frame_diff( Appendix B, “Refer- ...
Page 91
... AAL1gator II controls the tristating of its own address and data bus drivers so no conflicts occur with the microprocessor external buffers. PMC-Sierra, Inc. Line Interface with Transmit Framer Jitter Attenuator Frame Gain Nominal Frame Difference Underrun PM73121 AAL1gator II AAL1 SAR Processor Frequency Synthesizer Use Nominal Frequency ...
Page 92
... Configuration To transfer TDM data into cells or to transfer cells into TDM data, the PM73121 and each line needs to be configured, and the queues need to be configured and added to determine how the data should be mapped. To configure the AAL1gator II and each line, initialize the COMP_LIN_REG and the LIN_STR_ MODE register for each line ...
Page 93
... Figure 53. 240-Pin Physical Dimensions Diagram (Part PMC-Sierra, Inc. ,VVXH 0.40 34.60 ± (NOTE 3) 0.20 32.00 ± (NOTE 4) -D- (NOTE 2) TM PM73121 PM73121 AAL1gator II AAL1 SAR Processor Measurements are shown in millimeters. Not drawn to scale. 121 120 -B- (NOTE Refer to NOTES on the following page. ...
Page 94
... Controlling dimension = millimeter you need a measurement not shown in this figure, please contact PMC-Sierra. Figure 53. 240-Pin Physical Dimensions Diagram (Part PMC-Sierra, Inc. ,VVXH Measurements are shown in millimeters. Not drawn to scale. 0.05 PM73121 AAL1gator II AAL1 SAR Processor Base Plane (NOTE 6) -C- 0.20 0.50 ± ...
Page 95
... RL_FSYNC 8 TL_CLK 8 TL_SIG 8 TL_SER 8 TL_MSYNC 8 TL_FSYNC TLCLK_OUTPUT_EN 4 SRTS_DOUT 4 SRTS_LINE SRTS_STRB ADAP_STRB Figure 54. AAL1gator II Pinout Diagram PMC-Sierra, Inc PM73121 AAL1gator II AAL1 SAR Processor 8 TATM_DATA (RPHY_DATA) TATM_SOC (RPHY_SOC) /TATM_EN (RPHY_CLAV) /TATM_FULL (/RPHY_EN) TATM_CLK (RPHY_CLK) /RPHY_ADDR 8 RATM_DATA (TPHY_DATA) RATM_SOC (TPHY_SOC) /RATM_EN (TPHY_CLAV) /RATM_EMPTY ...
Page 96
... TL_FSYNC(3) 103 TL_CLK(3) 104 GND 105 RL_CLK(3) 106 RL_FSYNC(3) 107 RL_MSYNC(3) 108 RL_SER(3) 109 RL_SIG(3) 110 NC 111 TL_SIG(4) PM73121 AAL1gator II AAL1 SAR Processor Pin Name 115 TL_CLK(4) 116 GND 117 RL_CLK(4) 118 RL_FSYNC(4) 119 GND 120 GND 121 VDD 122 VDD ...
Page 97
... GND 211 MEM_ADDR(14) 212 VDD 213 VDD 214 MEM_ADDR(15) 215 MEM_ADDR(16) 216 ADDR17 217 NC 218 MEM_DATA(0) PM73121 AAL1gator II AAL1 SAR Processor Pin Name 150 NC (Must be left disconnected) 151 VDD 152 TL_SIG(7) 219 MEM_DATA(1) 220 MEM_DATA(2) 221 MEM_DATA(3) 222 GND 223 ...
Page 98
... MPHY mode, the AAL1gator II drives this bus only when the ATM layer has selected it for a cell transfer. Bit 0 is the LSB. Bit 7 is the MSB and should be transmitted first. Maximum output current (I PM73121 AAL1gator II AAL1 SAR Processor ) is 4 mA. MAX Description ) = 8 mA. ...
Page 99
... Bit 0 is the LSB. Bit 7 is the MSB and should be received first. PHY: Transmit UTOPIA PHY Layer Data Bits form the byte-wide data from the ATM layer device. Bit 0 is the LSB. Bit 7 is the MSB and should be received first. PM73121 AAL1gator II AAL1 SAR Processor Description ) = 8 mA. MAX ...
Page 100
... ATM layer MPHY address signals. This input is used as an output enable for RPHY_CLAV and to validate the activation of /RPHY_EN. In SPHY mode this input is not used. There is an internal pull-down resistor. PM73121 AAL1gator II AAL1 SAR Processor Description ) = 8 mA. MAX ...
Page 101
... TLCLK_OUTPUT_EN and the CLK_SOURCE bits, these pins are either outputs or inputs. If TLCLK_OUTPUT_EN is high, these pins are outputs and the clock is sourced internally at power up. This can later be changed by the CLK_SOURCE bits. Maximum output current (I PM73121 AAL1gator II AAL1 SAR Processor Description ) = 8 mA. MAX ) = 8 mA. ...
Page 102
... Receive Line Signal Bits carry the CAS signaling information from the corresponding framer devices in SDF-MF mode. In UDF-HS mode, only line 0 is active Receive Line Serial Data Bits carry the receive data from the corresponding framer devices. PM73121 AAL1gator II AAL1 SAR Processor Description ) = 8 mA. MAX ) = 8 mA. MAX ...
Page 103
... DOUT(3:0) and SRTS_LINE(2:0). This transfer is made synchronous to SYS_CLK. Out 0 Adaptive Strobe indicates that the channel status and frame difference are being played out on the SRTS_DOUT. The nibbles are identified by the values on SRTS_LINE Network Clock is the network-derived clock for SRTS. PM73121 AAL1gator II AAL1 SAR Processor Description ...
Page 104
... There is an internal pull-down resistor, so all TL_CLK pins are inputs if the pin is not connected. The value of this input is overwritten by the CLK_SOURCE bits in the LIN_ STR_MODE register (refer to MODE” starting on page PM73121 AAL1gator II AAL1 SAR Processor Description section 7.4.3 “LIN_STR_ 126). ...
Page 105
... Reset is an active low hardware reset. NA Output Enable is an active low signal that enables outputs of the device. It allows outputs to be disabled for in-circuit testing. Tie this signal to ground for normal operation. PM73121 AAL1gator II AAL1 SAR Processor 168), this 4), but need not ...
Page 106
... Scan Test Clock is the clock for boundary scan logic. 1 Process Test is an output to measure process test parameters only during device manufacture. Leave unconnected during normal operation. NA Pullup Disable is used to disable internal pullup resistors during manufacturing tests. Connect directly to ground. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 107
... All TTL inputs 2.0 All TTL inputs 2.4 OH MAX MAX all lines active, generating TL_CLK 77.76 MHz N_CLK All inputs -35 through Table 10 on page 89 for the different I PM73121 AAL1gator II AAL1 SAR Processor Min Max Unit -0.3 6 ° -65 150 C +0 Min Max Unit 4.75 5.25 ...
Page 108
... EXT ° NOTES: •Capacitance measured at 25 •Sample tested only. •*RAM interface has different loading. Refer to PMC-Sierra, Inc. Table 14. Capacitance Conditions To meet timing C. section 6.5 “RAM and Microprocessor Timing” on page PM73121 AAL1gator II AAL1 SAR Processor Min Max Unit 50* pF/pin 103 ...
Page 109
... Clock hold PMC-Sierra, Inc. Figure 57 on page 94, and Figure 58 on page 94 Th Tsu Signals RL_CLK RL_CLK RL_MSYNC, RL_FSYNC, RL_SIG, RL_SER RL_MSYNC, RL_FSYNC, RL_SIG RL_SER PM73121 AAL1gator II AAL1 SAR Processor show how the Tcp Tcp Tcp Tcp Min Max Unit 15 MHz ...
Page 110
... AAL1gator II will resync to the new structure. The sync pulses do not have to be driven every frame or multiframe. PMC-Sierra, Inc. CHAN 24, FRAME 24 CHAN 24, FRAME 1234 5678 XXXX ABCD ... X ... PM73121 AAL1gator II AAL1 SAR Processor CHAN 1, FRAME 1 CHAN 1, FRAME ...
Page 111
... 1234 5678 XXXX ABCD ... X ... Tsu Signals PM73121 AAL1gator II AAL1 SAR Processor TS1, FRAME 0 TS1, FRAME Tcp Tcp Tcp Tcp Min Max Unit 45 MHz ...
Page 112
... Figure 62 on page 96 show the receiver transmits Tsu Tcp Tcp Tcp Tcp Th Tq Signals Min TL_CLK TL_CLK 10 TL_MSYNC, TL_FSYNC 5 TL_MSYNC, TL_FSYNC 1 TL_SIG, TL_SER 2 and Figure 60. In all cases, signaling data is driven on PM73121 AAL1gator II AAL1 SAR Processor Max Unit 15 MHz ...
Page 113
... CHAN 0, FRAME 0 CHAN 0, FRAME Signals TL_CLK(0) TL_CLK(0) TL_SER(0) PM73121 AAL1gator II AAL1 SAR Processor CHAN 1, FRAME 1 CHAN 1, FRAME Table 16 on CHAN 1, FRAME 0 CHAN 1, FRAME ...
Page 114
... Appendix B, “References”, on page UTOPIA Name TxDATA TxSOC TxEnb* TxFull* TxClk Fc Fc Tdc Tdc Signals TATM_CLK TATM_CLK /TATM_FULL /TATM_FULL TATM_SOC, /TATM_EN TATM_DATA PM73121 AAL1gator II AAL1 SAR Processor 203). Table 17 indicates for addi- Th Tsu Min Max Unit 33 MHz ...
Page 115
... RPHY_CLK(i) RPHY_CLAV(o) RPHY_SOC(o) RPHY_DATA(o) /RPHY_EN(i) PMC-Sierra, Inc. Appendix B, “References”, on page section 3.4 “Transmit UTOPIA Interface Block UTOPIA Name RxAddr RxData RxSOC RxClav RxEnb* RxClk Thd Tsu Tq Figure 64. TUTOPIA SPHY Timing PM73121 AAL1gator II AAL1 SAR Processor 203). Table 18 indicates ...
Page 116
... PMC-Sierra, Inc. Signal /RPHY_EN RPHY_CLAV, RPHY_SOC /RPHY_EN RPHY_DATA indicates the AAL1gator II receive MPHY UTOPIA signal section 3.4 “Transmit UTOPIA Interface Block (TUTOPIA)” on Thd Tsu Tq Figure 65. TUTOPIA MPHY Timing PM73121 AAL1gator II AAL1 SAR Processor Min Max Unit 33 MHz ...
Page 117
... RATM_DATA RATM_SOC /RATM_EN /RATM_EMPTY RATM_CLK PMC-Sierra, Inc. Signal /RPHY_ADDR, /RPHY_EN RPHY_CLAV, RPHY_SOC /RPHY_ADDR, /RPHY_EN RPHY_DATA 203). Table 19 indicates the receive UTOPIA Name RxData RxSOC RxEnb* RxEmpty* RxClk PM73121 AAL1gator II AAL1 SAR Processor Min Max Unit 33 MHz ...
Page 118
... RATM_CLK /RATM_EMPTY, RATM_DATA, RATM_SOC /RATM_EMPTY, RATM_DATA, RATM_SOC /RATM_EN 203). Table 20 indicates the transmit section 3.5 “Receive UTOPIA Interface Block for additional information. UTOPIA Name TxAddr TxData TxSOC TxClav TxEnb* TxClk PM73121 AAL1gator II AAL1 SAR Processor Min Max Unit 33 MHz 45 ...
Page 119
... Figure 68 PMC-Sierra, Inc. Thd Tdc Tdc Tsu Tq D1 Figure 67. RUTOPIA SPHY Timing Signal TPHY_DATA, TPHY_SOC, /TPHY_EN TPHY_CLAV TPHY_DATA, TPHY_SOC, /TPHY_EN 203). Table 20 on page 101 PM73121 AAL1gator II AAL1 SAR Processor Min Max Unit 33 MHz ...
Page 120
... SRAMS. PMC-Sierra, Inc. for additional information. Thd Tsu Figure 68. RUTOPIA MPHY Timing Signal /TPHY_ADDR, TPHY_DATA, TPHY_SOC, /TPHY_EN TPHY_CLAV /TPHY_ADDR, TPHY_DATA, TPHY_ SOC, /TPHY_EN PM73121 AAL1gator II AAL1 SAR Processor section 3.5 “Receive UTOPIA D3 D4 Min Max Unit 33 MHz ...
Page 121
... Min /MEM_CS Tp-2 MEM_DATA Tp-Tch-10 MEM_DATA Tch - 4.3 /MEM_CS, MEM_ADDR, Tp -Tch -10 /MEM_WE MEM_ADDR, /MEM_CS 1 /MEM_WE Tch-1.3 section 8.6 “Board Requirements for the SRAM Interface” on page ° C, 4.75 - 5.25 V. PM73121 AAL1gator II AAL1 SAR Processor Twh Twdh Max Unit Tch+0.3 ns Figure 80 on 174. ...
Page 122
... RAM write. PMC-Sierra, Inc. Trc Trc Trdacc Toe Trdacc Trdacc Figure 70. RAM Read Cycle Timing Signals MEM_DATA /MEM_CS MEM_DATA, /MEM_CS, /MEM_ ADDR Figure 80 on page ° C, 4.75 - 5.25 V. PM73121 AAL1gator II AAL1 SAR Processor Min Max Unit Tp Tsc ns 119. ...
Page 123
... Cycles (1) and (2) are grouped together in Figure 71 for the sake of convenience. These are nor- mally two separate clock cycles. NOTE: The timing characteristics (indicated by asterisks in the table following Figure 71) are based on external component requirements. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ...
Page 124
... Tasu17 Twd Tasu Taa Tded Taed PROC WRITE CYCLE RECOVERY CYCLE Signals /PROC_ACK MEM_ADDR, /MEM_WE /PROC_ACK /MEM_WE MEM_DATA /SP_DATA_EN /SP_ADD_EN SP_DATA_DIR PM73121 AAL1gator II AAL1 SAR Processor 5 Tah Tdsu Tdh Twd Tq Tcea Tded Taed Tddh NON_PROC CYCLE Min Max Unit 5 29 SYS_CLK ...
Page 125
... In the following clock cycle (6), /MEM_CS and /MEM_OE are deactivated and /PROC_ACK is activated. PMC-Sierra, Inc. Signals /MEM_CS /PROC_ACK MEM_ADDR, /SP_ADD_EN MEM_DATA, /SP_DATA_EN /SP_DATA_EN, SP_DATA_DIR ADDR17 PM73121 AAL1gator II AAL1 SAR Processor Min Max Unit ...
Page 126
... Time from z state to enable PMC-Sierra, Inc Tzsu Taa Taed Tcaen Tq Tdsu Tq Tah Tasu Tdh Tq Tzen Tqmoe Tq PROC RD CYCLE RECOVERY CYCLE NON-PROC CYCLE Signals /PROC_ACK MEM_DATA, /MEM_OE PM73121 AAL1gator II AAL1 SAR Processor Tcea Tded Min Max Unit 5 29 SYS_CLK periods 1** ns ...
Page 127
... PMC-Sierra, Inc. Signals Min SP_DATA_CLK,/MEM_OE (deactivate) /MEM_CS MEM_OE (activate) ADDR17 /SP_ADD_EN MEM_ADDR, SP_DATA_CLK /SP_DATA_EN, /PROC_CS, 2** /PROC_RD /PROC_ACK MEM_DATA MEM_DATA, SP_DATA_CLK SP_DATA_CLK, /SP_ADD_EN MEM_ADD, SP_DATA_CLK MEM_ADDR 3** PM73121 AAL1gator II AAL1 SAR Processor Max Unit ...
Page 128
... Cycles (1) and (2) are grouped together in Figure 73 for the sake of convenience. These are nor- mally two separate clock cycles. NOTE: The timing characteristics (indicated by asterisks in the table following Figure 73) are based on external component requirements. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor (refer to “(Reserved)” on page ...
Page 129
... MEM_ADDR(i) MEM_DATA(io) ADDR17(i) /PROC_ACK(i) /SP_DATA_EN(o) /SP_ADD_EN(o) SP_DATA_DIR(o) /MEM_CS(o) /MEM_WE(o) /MEM_OE(o) Figure 73. Microprocessor Write Command Register Timing PMC-Sierra, Inc Tasu17 Tq Taa Tded Tded Tq NON-PROC CMDREG RECOVERY RD CYCLE WR CYCLE CYCLE PM73121 AAL1gator II AAL1 SAR Processor Tcea Tq NON_PROC CYCLE ...
Page 130
... At the following clock cycle (4), /SP_ADD_EN is deactivated but /SP_DATA_EN remains active. At clock cycle (5) the AAL1gator II begins driving valid data that is latched into the data latch in cycle (6) when SP_DATA_CLK is driven high. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor Signals ...
Page 131
... Cycles (1) and (2) are grouped together in Figure 74 for the sake of convenience. These are nor- mally two separate clock cycles. NOTE: The timing characteristics (indicated by asterisks in the table following Figure 74) are based on external component requirements. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ...
Page 132
... MEM_ADD(i) Tasu17 ADDR17(i) MEM_DATA(io) /PROC_ACK(i) Tded /SP_DATA_EN(o) SP_DATA_DIR(o) SP_DATA_CLK(o) /MEM_CS(o) /MEM_WE(o) /MEM_OE(o) Figure 74. Microprocessor Read Command Register Timing PMC-Sierra, Inc. Trd Trd Tdsu Taa NON_PROC CMDREG WRITE CYCLE RD CYCLE PM73121 AAL1gator II AAL1 SAR Processor 6 7 Tdhld Tcea Tded Tq ...
Page 133
... Microprocessor accesses are not honored unless this count has completed. /PROC_CS(i) HOLDOFF(o) Figure 75. Microprocessor Holdoff Timing PMC-Sierra, Inc. Signals /PROC_ACK MEM_ADDR SP_DATA_CLK /SP_DATA_EN, /MEM_CS, /MEM_RD MEM_DATA MEM_DATA /PROC_ACK Thoff PM73121 AAL1gator II AAL1 SAR Processor Min Max Unit 5 29 SYS_CLK periods SYS_CLK periods 2 ...
Page 134
... Clear intr due to clear latch bit PMC-Sierra, Inc. Tq Signals Min HOLDOFF 20 HOLDOFF 2 Tq Tmsk Tclr Figure 77. Interrupt Timing Signals SYS_CLK, PROC_INTR PROC_CS, PROC_INTR PROC_CS, PROC_INTR PM73121 AAL1gator II AAL1 SAR Processor Max Unit 20 SYS_CLK periods 16 ns Min Max Unit SYS_CLK ...
Page 135
... Data setup Thld Data hold PMC-Sierra, Inc. Tq Figure 78. Low-Speed SRTS Timing Signals SRTS_LINE, SRTS_DOUT, SRTS_STRB, ADAP_SRTB Tq Tsu Figure 79. High-Speed SRTS Timing Signals SRTS_DOUT, SRTS_STRB SRTS_DOUT SRTS_DOUT PM73121 AAL1gator II AAL1 SAR Processor Tq Min Max Unit Thld Tq Min Max Unit 18 ns ...
Page 136
... Figure 81 shows the timing for the RESET signal. /RESET(i) /PROC_CS PMC-Sierra, Inc Figure 80. SYS_CLK Timing Signals SYS_CLK SYS_CLK SYS_CLK SYS_CLK SYS_CLK SYS_CLK* Tres Tres Trec Figure 81. Reset Timing PM73121 AAL1gator II AAL1 SAR Processor Tcl Tcl Tch Tch Min Max Unit 40.00 MHz ** 25 ...
Page 137
... RL_CLK, active TL_CLK, or SYS_CLK Tjsu Tjh Tqj Figure 82. JTAG Timing Signals SCAN_TCLK SCAN_TCLK SCAN_TCLK SCAN_TMS, SCAN_TDI /SCAN_TRST SCAN_TMS, SCAN_TDI SCAN_TDO PM73121 AAL1gator II AAL1 SAR Processor Max Unit Tjres Tjres Tcl Tcl Tqj Min Max Unit 5 MHz 80 ns ...
Page 138
... Figure 83 on page 122 shows the distribution of the data structures within the AAL1gator II. All registers except CMDREG are stored in the SRAM and all are readable. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor “SW_RESET” on page 165) is applied. The “ ...
Page 139
... R_QUEUE_TBL VC=1 VC=2 • • • • VC=254 VC=253 1 2 R_OAM_QUEUE (256 cell buffers) R_OAM_QUEUE_TBL OAM_HEAD OAM_TAIL R_DATA_BUFFER PM73121 AAL1gator II AAL1 SAR Processor VC=3 • MATH_TBL • • VC=255 T_OAM_QUEUE OAM OAM T_DATA_BUFFER R_SRTS_CONFIG VC=3 R_SRTS_CDVT_0 • • • • R_SRTS_CDVT_7 • R_SRTS_QUEUE • ...
Page 140
... The Composite Line Register provides overall mode information. 2 bytes The Line Structure Mode register identifies which data structure type will be supported 2 bytes for each line. This is selectable on a line basis. 2 bytes 2 bytes 2 bytes 2 bytes 2 bytes 2 bytes PM73121 AAL1gator II AAL1 SAR Processor Description ...
Page 141
... Format: Refer to the following table. Field (Bits) DEVICE_REV This register is undefined until the microprocessor asserts CMD_REG_ATTN, at which (15:0) time the AAL1gator II writes it with 121A should be initialized to 0. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor Description . The revision of the device. This field h ...
Page 142
... Disables the UDF-HS (T3/E3) mode. 1 Enables the QUEUE_TBL and R_QUEUE_TBL entry index 0 are used. Initialize Device mode. T1 mode. 1 Device is in 126), set the FR_STRUCT field of each line to 10. PM73121 AAL1gator II AAL1 SAR Processor If this mode is selected, the T_ section 7.4.3 “LIN_ ...
Page 143
... Use T1 signaling. 0 Use E1 signaling. 00 Use external clock. (TL_CLK is an input). 01 LOOPED - Use RL_CLK as the clock source. 10 NOMINAL - Generate a clock of the nominal (T1 or E1) frequency from SYS_CLK. 11 SRTS - Generate a clock frequency based on the received SRTS values. PM73121 AAL1gator II AAL1 SAR Processor Description ...
Page 144
... C000 - 0 DFFF h h PM73121 AAL1gator II AAL1 SAR Processor Description The empty bytes in a partially filled cell are filled with P_FILL_CHAR. Bit table of queues to be added to the calendar queue after a CSD_ATTN assertion. The Transmit Sequence Number Table is initialized according to a table. ...
Page 145
... ATTN is detected. Bits left asserted from earlier add activities will be added back in with undesirable results. Initialization: Initialize to 0. PMC-Sierra, Inc. Description Offset Description 0 Queues 15:0 (line Queues 31:16 (line Queues 47:32 (line Queues 63:48 (line Queues 79:64 (line 2) h PM73121 AAL1gator II AAL1 SAR Processor ...
Page 146
... Offset Data Value 0 0000 0017 002D 003A 004E 0059 0063 0074 008B 009C 00A6 00B1 00C5 00D2 00E8 00FF h h PM73121 AAL1gator II AAL1 SAR Processor ...
Page 147
... Transmit conditioned signaling for line 5. Transmit conditioned signaling for line 6. Transmit conditioned signaling for line 7. Description Offset = ((channel -1) 2) line 16. Offset = ((channel -1) 2) line 16. Offset = ((channel -1) 2) line 16. Offset = ((channel -1) 2) line 16. Offset = (channel 2) line 16. Offset = (channel 2) line 16. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 148
... Transmit conditioned data for line 1. Transmit conditioned data for line 2. Transmit conditioned data for line 3. Transmit conditioned data for line 4. Transmit conditioned data for line 5. Transmit conditioned data for line 6. Transmit conditioned data for line 7. Description PM73121 AAL1gator II AAL1 SAR Processor line 16. 16. ...
Page 149
... PMC-Sierra, Inc. 32 DS0s 8 lines. Each of the eight lines are allocated 15 Bit 0 Word PM73121 AAL1gator II AAL1 SAR Processor ...
Page 150
... PMC-Sierra, Inc. Name Transmit OAM cell 1. Transmit OAM cell 2. Bits 15:8 Header 1 Header 3 Header 5 (HEC) Bits 7:1 Not used. Set to 0. Bit 0 0 Disables CRC-10 insertion. 1 Enables CRC-10 insertion. Payload Payload 47 PM73121 AAL1gator II AAL1 SAR Processor Description Bits 7:0 Header 2 Header 4 Payload Payload 48 ...
Page 151
... A bit table with a bit set per DS0 allocated to this queue for DS0s 31:16 on the line defined by queue 32. Initialize to the same value as T_CHAN_ALLOC(15:0). Initialize to the same value as T_CHAN_ALLOC(31:16). Controls transmission of data. Initialize to 0 each time this queue is initialized. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 152
... Set the bit corresponding to this queue in the T_ADD_QUEUE table (refer to section 7.6.2 “T_ADD_QUEUE” on page 3. Assert the CSD_ATTN bit in the CMD_REG (refer to mat” on page 165). ters in the queue table for that queue. PM73121 AAL1gator II AAL1 SAR Processor 139) is set. 128). “CMDREG Word For- ...
Page 153
... DS0 in SDF-FR mode, no pointer should be used. PER_CELL number must exceed the number of DS0 channels allocated to the queue by two. For example channel SDF-MF queue may have the number set from 19 to 47. Description PM73121 AAL1gator II AAL1 SAR Processor Appendix B, “References” Initialize to 0. After h ...
Page 154
... It is measured in eighths (three LSBs are fractional bits). Initialize (178 UDF modes full cells and Single-DS0-no-pointer mode full cells, 46.875 SDF modes full cells the partially filled cell length 8. PMC-Sierra, Inc. Description Description Description Description . b PM73121 AAL1gator II AAL1 SAR Processor ) for h 8 (177 ) for h ...
Page 155
... Initialize to the same value as T_CHAN_ALLOC(15:0). (15:0) T_CHANNEL_LEFT(31:16) Word Format Field (Bits) T_CHANNEL_LEFT Initialize to the same value as T_CHAN_ALLOC(31:16). (31:16) PMC-Sierra, Inc. Description Description for UDF-ML and UDF-HS modes. h Description for UDF-ML and UDF-HS modes. h Description Description PM73121 AAL1gator II AAL1 SAR Processor 8. This field is not ...
Page 156
... Transmit data for: (15:8) Channel = (offset mod 16 offset = line T1 offset = line T_DATA_L Transmit data for: (7:0) Channel = (offset mod 16 offset = line T1 offset = line PM73121 AAL1gator II PMC-Sierra, Inc. Description section 7.4.3 “LIN_STR_MODE” start- Description 1. 2048 + multiframe 256 + frame 16 + (channel - 2048 + multiframe 512 + frame ...
Page 157
... Format: The four values resulting from the math operations are stored in the same table, as shown in Figure 85. Field (Bits) This table is available in the Software Driver available at http://www.pmc-sierra.com. NOTE: The AAL1gator II uses a different math table than previous versions of the chip. The PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor Description ...
Page 158
... A000 - 0 h BFFF h 16 kBytes 0 E000 - 0 FFFF h 1 0000 - 1 FFFF h PM73121 AAL1gator II AAL1 SAR Processor Address Description Receive OAM head and tail pointers. h Count of received OAM cells. Count of dropped OAM cells. Reserved (SRTS Queue Pointers). h Receive SRTS configuration. h Mask of bits. Initialized from a table. ...
Page 159
... All read-only port bits marked “Not used” are driven with a 0 and should be masked off by the software to maintain compatibility with future versions. PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor section 7.5 “Transmit Data Structures ...
Page 160
... Word Format” on page Description Head pointer. Tail pointer. Description The microprocessor should increment to the next cell location when it reads a cell. Initialize to 0. Description Incremented by the RALP after it writes a cell to the OAM cell queue. Initialize to 0. PM73121 AAL1gator II AAL1 SAR Processor 165). ...
Page 161
... OAM cells dropped. OAM cells are dropped when more than 255 are present in the receive queue. The software must initialize this counter to 0 during reset. After initialization, do not write to this word. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 162
... Receive SRTS CDVT for line 4. Receive SRTS CDVT for line 5. Receive SRTS CDVT for line 6. Receive SRTS CDVT for line 7. Description Write with 0 to maintain compatibility with future software versions. Receive SRTS CDVT. PM73121 AAL1gator II AAL1 SAR Processor 256, or 11.75, and ...
Page 163
... Header PM73121 AAL1gator II AAL1 SAR Processor Data Offset (Hex ...
Page 164
... PM73121 AAL1gator II AAL1 SAR Processor Data (Hex ...
Page 165
... R_COND_DATA table. 11 When the queue is in underrun, read the signaling from multi- frame 0 and play out the contents of the buffer. Write with maintain future software compatibility. PM73121 AAL1gator II AAL1 SAR Processor section 7.8.8 “ ...
Page 166
... Write with maintain future software compatibility. Five LSBs of the queue index associated with this DS0. The three MSBs are implicitly those of the line number. Offset = channel 2 + line 16. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 167
... Receive conditioned D signaling bit or B bit for: Offset = (channel - line Write with maintain future software compatibility. Receive conditioned A signaling bit for: Offset = channel 2 + line 16. Receive conditioned B signaling bit for: Offset = channel 2 + line 16. PM73121 AAL1gator II AAL1 SAR Processor 16. 16. 16. 16. ...
Page 168
... Receive conditioned data for line 4. Receive conditioned data for line 5. Receive conditioned data for line 6. Receive conditioned data for line 7. Description Receive conditioned data for: Offset = (channel - line 16. Receive conditioned data for: Offset = channel 2 + line 16. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 169
... Format: One SRTS nibble per word. R_SRTS_QUEUE_n Word Format Field (Bits) Not used (15:4) R_SRTS (3:0) PMC-Sierra, Inc. 8 lines. Each line is allocated a separate 64-entry queue to store Description Write with maintain future software compatibility. Receive SRTS data for line = offset 64. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 170
... Write with maintain compatibility with future software versions. Receive signaling data for: Channel = (offset mod 16) 2. Multiframe offset mod 512) Line = offset 512. Offset = line 512 + multiframe 16 + channel 2. PM73121 AAL1gator II AAL1 SAR Processor 32 byte mem- 16. 16. ...
Page 171
... Initialize to 0. 16-bit rollover count of the occurrences of pointer reframes. Initialize to 0. 16-bit rollover count of the occurrences of pointer parity errors. Initialize to 0. 16-bit rollover count of the occurrences of misinserted cells. Initialize to 0. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 172
... A 6-bit integer specifying how many bytes per cell are required if no structure pointers are used. For UDF-HS mode, this must be set to 47. In other modes, set this to the partially filled length. If cells are not partially filled, set this to 47. Write with maintain future software compatibility. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 173
... Indicates that this queue is currently in underrun. Initialize to 1. Not used in UDF-HS mode. Indicates that this queue is currently in resume state. Initialize to 0. Not used in UDF-HS mode. Indicates that this queue is currently in signal resume state. Initialize to 0. Not used in UDF-HS mode. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 174
... SYNC state to the OUT_OF_SEQUENCE state. This is the atmfCESAal1SeqErrors count from the CES specification. Note that if SN processing is disabled, this counter will count all out-of-sequence cells. Initialize to 0. Once initialized, do not write to this word. PM73121 AAL1gator II AAL1 SAR Processor . R_ h ...
Page 175
... CES specification. Initialize to 0. Once initialized, do not write to this word. Description 16-bit rollover count of received cells. This is the atmfCESReassCells counter from the CES specification. Initialize to 0. Once initialized, do not write to this word. Description “R_MAX_BUF Word Format” on page PM73121 AAL1gator II AAL1 SAR Processor 157) was asserted. ...
Page 176
... For T1/E1 SDF-FR: R_TOT_SIZE = no. of DS0s 1 For T1 SDF-MF and E1_W_T1_SIG: R_TOT_SIZE = 24 no. of DS0s For E1 SDF-MF: 16 no. of DS0s R_TOT_SIZE = Description “R_CHAN_ALLOC(15:0) Word Format” 161). Not used in UDF-ML or UDF-HS modes. PM73121 AAL1gator II AAL1 SAR Processor no. of DS0s + 1 ------------------------------------------- - 1 + – 2 no. of DS0s + 1 ------------------------------------------- - 1 + – ...
Page 177
... Insert data from R_CONDQ_DATA with the MSB controlled by b the pseudorandom number algorithm x UDF-HS). If set, sequence number processing is disabled. Statistics will still be kept but no cells will be dropped due to SN errors. PM73121 AAL1gator II AAL1 SAR Processor (not valid for ...
Page 178
... Pointer mismatch. • Overrun. • Blank allocation table (refer to “R_CHAN_ALLOC(15:0) Word For- mat” on page 161). • SN processing. • Structured cell received while in underrun but structure start has not been found yet. PM73121 AAL1gator II AAL1 SAR Processor 155) equals 155) equals , b ...
Page 179
... CES specification. Initialize to 0. Once initialized, do not write to this word. Description 16-bit rollover count of the occurrences of pointer parity errors on this queue. This is the atmfCESPointerParityErrors counter in the CES specification. Initialize to 0. Once initialized, do not write to this word. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 180
... OAM and non-data cells. Name R_OAM_CELL_0 Receive OAM cell 0 R_OAM_CELL_1 Receive OAM cell R_OAM_CELL_255 Receive OAM cell 255 Bits 15:8 Header 1 Header 3 Header 5 (HEC) Payload Payload 47 CRC_10_PASS PM73121 AAL1gator II AAL1 SAR Processor Description . . . Bits 7:0 Header 2 Header 4 Blank Payload Payload 48 ...
Page 181
... Initialization not necessary to initialize this structure. Format: Two data bytes per word. PMC-Sierra, Inc. Description The CRC_10_PASS bit is set if the cell passes the CRC-10 check. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 182
... Description 1 means an OAM interrupt is present. 0 means an OAM interrupt is not present. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 183
... After the requested change has been performed, the AAL1gator II clears the attention bit. The microprocessor must not request another change PMC-Sierra, Inc. Description Description 00 Not used. 01 Signal data FIFO. 10 Receive FIFO. 11 Transmit FIFO. PM73121 AAL1gator II AAL1 SAR Processor ...
Page 184
... Before reactivating a previously active queue, be sure to reinitialize all the registers in the queue table for that queue. PMC-Sierra, Inc. 134. The proper bit in the T_ 134). The queue will not be the frame rate “FRAMES_PER_CELL” on page PM73121 AAL1gator II AAL1 SAR Processor 136. ...
Page 185
... DS3, B3ZS DS3 Line Module DS3 LIU (ATT) PMC-Sierra, Inc. DS1(1-8) DS1(9-16) DS3MX TQUAD PM8318 PM4344 DS1(17-24) DS1(25-28) 4 Microprocessor Figure 86. Typical DS1 Application PM73121 AAL1gator II AAL1 SAR Processor SRAM 4 To Switch Fabric ATM Routing AAL1gator II UTOPIA Table (PM73121) (WAC-187-X) 4 ...
Page 186
... Quad T1 Framer (PMC 4344) BRFPI RCLK 4 RCLKI Figure 87. Typical PMC Quad Framer Interface PMC-Sierra, Inc. 4 BTPCM 4 BTSIG 4 4 BRPCM 4 BRSIG 4 BRFPO 4 RCLKO PM73121 AAL1gator II AAL1 SAR Processor 4 TL_CLK TL_SER TL_SIG TL_FSYNC TL_MSYNC AAL1gator II (PM73121) RL_SER RL_SIG RL_FSYNC RL_MSYNC RL_CLK ...
Page 187
... Figure 88 shows the AAL1gator DS3 application. DS3 Line DS3 Framer DS3, B3ZS Module PMC-Sierra, Inc. SRAM AAL1gator II DS3 UTOPIA (PM73121) Microprocessor Figure 88. Typical DS3 Application PM73121 AAL1gator II AAL1 SAR Processor ATM Routing To Switch Fabric Table (WAC-187-X) ...
Page 188
... PMC-Sierra, Inc D(8:0) TATM_DATA(7:0) TATM_SOC /TATM_FULL /PAF External Transmit /WEN1 /TATM_EN FIFO WCLK TATM_CLK (IDT SyncFIFO*) TATM_CLK_Source 9 8 Q(8:0) RATM_DATA(7:0) RATM_SOC /RATM_EMPTY / External CLK Receive /RATM_EN /REN1 FIFO /OE (IDT SyncFIFO*) RATM_CLK RCLK RATM_CLK_Source PM73121 AAL1gator II AAL1 SAR Processor AAL1gator II (PM73121) ...
Page 189
... Bellcore must make this patent available under fair and equitable conditions. Bellcore believes they are satisfying this requirement by offering the license to the equipment manufacturers rather than to the silicon manufacturers. PMC-Sierra, Inc. Figure 90 on page Appendix B, “References”, on page 203 PM73121 AAL1gator II AAL1 SAR Processor 173. The circuit for a list of references. ...
Page 190
... Generation SRTS Logic T1 Frequency Generation DIV (193 + SRTS) (193 + SRTS) ( (158 + SRTS)) = 1.544 if SRTS = Frequency Generation DIV (64 - SRTS) (64 - SRTS) ( (63 - SRTS)) = 2.048 if SRTS = 0 PM73121 AAL1gator II AAL1 SAR Processor Clock Smoother LTX305A or T7690 TL_CLK_SRC (1.544 MHz) TL_CLK_SRC (2.048 MHz) ...
Page 191
... A(0:16 Y(0:16) G Octal Buffers with Tristate Outputs (FCT244) A(0:16) PROC_ADD (17) PROC_ADD (0:16) 17 Microprocessor to 100 See this application note for requirements for /MEM_WE resistors. PM73121 AAL1gator II AAL1 SAR Processor (2) 128K 8 SRAMs D(0:15) 16 Vcc A(0:15) Octal Bus SAB G Transceivers and CBA DIR Registers SBA (FCT646) ...
Page 192
... Tch is the high pulse width of SYS_CLK at 1 the clock period, and Rs is the delay through the resistor. PMC-Sierra, Inc. Delay (ns) 33 0.3 50 0.4 75 0.6 100 0.7 is not recommended, since this will cause rise/fall times - 4 -10 max PM73121 AAL1gator II AAL1 SAR Processor ...
Page 193
... To increase the margin, the tolerance on the clock PMC-Sierra, Inc. , the minimum and maximum duty cycle must be defined. Also -10 max of 11.6 ns and a Tch min 175, selecting a 50 resistor would meet both of these PM73121 AAL1gator II AAL1 SAR Processor of 14.1 ns max ...
Page 194
... In summary, one possible solution when using an SRAM with 7 ns setup is to use a 2.5% duty cycle CMOS clock (with a minimum rise/fall time of 0.5 ns and a maximum rise/fall time of 2 ns) and a 33 series resistor. PMC-Sierra, Inc. min shows that selecting a 33 PM73121 AAL1gator II AAL1 SAR Processor of 12.2 ns and a Tch of max resistor would meet both ...
Page 195
... Assuming we want a 0.5 ns margin on both setup and hold time, the requirements to meet are: Tch - 4 8.5 ns min PMC-Sierra, Inc. of 12.6 ns and a Tch min shows that selecting a 50 PM73121 AAL1gator II AAL1 SAR Processor of 13.1 ns. max resistor would meet both should not be used since ...
Page 196
... Therefore, the SRAM trace lengths should be approximately four inches long. Also, the series resistor should be placed as close as possible to the source pin. PMC-Sierra, Inc. 175, selecting a 33 resistor would meet both of these PM73121 AAL1gator II AAL1 SAR Processor of 12.2 ns and a Tch of min max ...
Page 197
... PMC-Sierra, Inc. 8 SRTS EPLD 4 (EC3125)* *NOTE: Manufacturer’s data sheets are subject to change. Please confirm specifications before using this part. SRTS_DOUT 8-Bit DAC Code (Binary) (Hex) 0111 E7 0110 CD 0101 C0 PM73121 AAL1gator II AAL1 SAR Processor VCC Ref In D0-D7 DAC (AD7801)* VOUT VCO ® ...
Page 198
... SRTS nibbles. PMC-Sierra, Inc. SRTS_DOUT 8-Bit DAC Code (Binary) (Hex) 0100 B3 0011 A6 0010 9A 0001 8D 0000 80 1111 73 1110 66 1101 5A 1100 4D 1011 40 1010 33 1001 26 1000 19 XXXX 80 PM73121 AAL1gator II AAL1 SAR Processor ...
Page 199
... MHz 2.048 MHz RL_CLK (0) TL_CLK (0) EPLD RL_MSYNC (0) TL_MSYNC (0) *NOTE: Manufacturer’s data sheets are subject to change. Please confirm specifications before using this part. Channel31 bit 0 Channel0 bit 7 Channel31 bit, last Channel0 bit, 1st PM73121 AAL1gator II AAL1 SAR Processor AAL1gator II (PM73121) ...
Page 200
... ATM_MPHY_EN bit to “0” and the ATM_CELL_EN bit to “1” in the GEN_ 5 microprocessor port. (The ATM_CELL_EN is set because the AAL1gator II implements cell-level handshaking due to its cell-based internal FIFOs.) In this mode the WAC-185-B-X does PM73121 AAL1gator II PMC-Sierra, Inc. AAL1 SAR Processor ...