PM7351-BI PMC-Sierra Inc, PM7351-BI Datasheet
PM7351-BI
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PM7351-BI Summary of contents
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... RELEASED DATA SHEET PMC-1980582 OCTAL SERIAL LINK MULTIPLEXER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 TM S /UNI - VORTEX S/UNI-VORTEX DATA SHEET RELEASED ISSUE 5: MARCH 2000 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER ...
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... Updated D.C. Characteristics R Changes marked with side bars. Matches functionality of PM7351 Rev B Changed the confidentiality notices for the document’s public release. Changes in all areas from Issue 1. Matches functionality of product PM7351-BI, Rev A Preliminary Document PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER and V in. IN ...
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... REGISTER MEMORY MAP ........................................................ 51 10 NORMAL MODE REGISTER DESCRIPTION ....................................... 55 11 TEST FEATURES DESCRIPTION .......................................................117 11.1 RAM BUILT-IN-SELF-TEST ...................................................... 120 11.2 JTAG TEST PORT .................................................................... 122 12 OPERATION ........................................................................................ 127 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER i ...
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... ABSOLUTE MAXIMUM RATINGS ....................................................... 147 15 D.C. CHARACTERISTICS ................................................................... 148 16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS..... 152 17 A.C. TIMING CHARACTERISTICS...................................................... 156 18 ORDERING AND THERMAL INFORMATION...................................... 162 19 MECHANICAL INFORMATION............................................................ 163 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER ii ...
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... REGISTER 0X013: MICROPROCESSOR INSERT FIFO READY................... 79 REGISTER 0X014: MICROPROCESSOR EXTRACT FIFO READY ............... 80 REGISTER 0X015: INSERT CRC-32 ACCUMULATOR (LSB)......................... 81 REGISTER 0X016: INSERT CRC-32 ACCUMULATOR (2ND BYTE) .............. 81 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER iii ...
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... REGISTERS 0X088, 0X0A8, 0X0C8, 0X0E8, 0X108, 0X128, 0X148, 0X168: RECEIVE HIGH-SPEED SERIAL FIFO OVERFLOW............................ 97 REGISTERS 0X089, 0X0A9, 0X0C9, 0X0E9, 0X109, 0X129, 0X149, 0X169: UPSTREAM ROUND ROBIN WEIGHT ................................................. 98 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER iv ...
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... REGISTER 0X099, 0X0B9, 0X0D9, 0X0F9, 0X119, 0X139, 0X159, 0X179: RECEIVE BIT ORIENTED CODE STATUS ..........................................113 REGISTERS 0X09C, 0X0BC, 0X0DC, 0X0FC, 0X11C, 0X13C, 0X15C, 0X17C: UPSTREAM LINK FIFO CONTROL .....................................................114 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER v ...
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... RELEASED DATA SHEET PMC-1980582 REGISTER 0X200: MASTER TEST ................................................................118 REGISTER 0X201: MASTER TEST CONTROL .............................................119 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER vi ...
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... FIG. 16 RSTB TIMING .................................................................................... 156 FIG. 17 RECEIVE SCI-PHY/ANY-PHY INTERFACE TIMING ......................... 157 FIG. 18 TRANSMIT SCI-PHY INTERFACE TIMING ....................................... 158 FIG. 19 JTAG PORT INTERFACE TIMING..................................................... 160 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER vii ...
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... TABLE 2 PREPENDED FIELDS....................................................................... 34 TABLE 3 : ASSIGNED BIT ORIENTED CODES .............................................. 41 TABLE 4: BOUNDARY SCAN REGISTER ..................................................... 123 TABLE 5 FROM NEAR-END DOWNSTREAM BUS TO FAR-END UPSTREAM BUS 131 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER viii ...
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... LVDS links. • Optionally routes the embedded control channels from the 8 link's to/ from the system bus. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 1 ...
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... Error monitoring and cell counting on all links. • Requires no external memories. • Low power 3.3V CMOS technology. • Standard 5 pin P1149 JTAG port. • 304 ball SBGA, 31mm x 31mm. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 2 ...
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... Multiservice access multiplexer. • Universal Mobile Telecommunication System (UMTS) wireless base stations. • UMTS wireless base station controllers. • Multi-shelf access concentrators. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 3 ...
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... American National Standard for Telecommunications, “Network and Customer Installation Interfaces – Asymmetric Digital Subscriber Line (ADSL) Metallic Interface”, ANSI T1.413-1998, November, 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 4 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Policing S/UNI- OA&M VORTEX Scheduling WAN Card Policing S/UNI- OA&M VORTEX Scheduling WAN Card PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Buffering WAN Discard OA&M up-link Buffering WAN Discard OA&M up-link 5 ...
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... Component costs are reduced, while system reliability increases due to reduced component count. In this type of architecture there are often three stages of signal concentration or multiplexing, as shown in Fig. 2. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 6 ...
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... One serial link attaches to the active core card, the other to the standby core PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 S/UNI- VORTEX Policing Buffering OA&M Discard S/UNI- Scheduling VORTEX Stage 3 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER WAN OA&M up-link WAN Card 7 ...
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... OA&M layers, as implemented by devices such as PMC-Sierra’s S/UNI-APEX and the S/UNI-ATLAS. This is the third stage of multiplexing single core card implementation is also supported, of course. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 8 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 33 Cell per-PH Y buffer 6 Cell FIFO 2 Cell FIFO 4 Cell FIFO to all blocks PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER TXD 0+ Cell TXD 0- Processor RXD0+ RXD0- TXD 7+ TXD 7- RXD7+ RXD7- Clock ...
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... DATA SHEET PMC-1980582 6 DESCRIPTION The PM7351 S/UNI-VORTEX is a monolithic integrated circuit typically used with its sister device, the S/UNI-DUPLEX, to implement a point-to-point serial backplane interconnect architecture sixteen S/UNI-VORTEX devices can reside on a common cell processing card along side a traffic management device. The traffic management device exchanges cells with the S/UNI-VORTEX via 16-bit SCI-PHY or Any-PHY interfaces ...
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... Provides read/write access to all configuration and status registers. • Provides CRC32 calculation and cell transfer registers to support an embedded microprocessor to microprocessor communication channel over the LVDS link. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 11 ...
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... PIN DIAGRAM The S/UNI-VORTEX is packaged in a 304-ball enhanced ball grid array (BGA) package having a body size and a ball pitch of 1.27 mm. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 12 ...
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... E1 or board interconnect. D.C. or A.C. coupling may be F2 used depending on the application current sinks, these outputs must see a 100Ω K2 reflected impedance between the pins in a signal pair N1 to produce correct LVDS signal levels PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 13 ...
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... The rising edge of RX8K is accurate to the nearest byte boundary of the high-speed serial link; therefore, a small amount of jitter is present link rate of 155.52 Mb/s, the jitter is 63ns peak-to-peak. Pulses on RX8K are always 16 high-speed serial link bit periods wide (two REFCLK periods). PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 14 ...
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... RPA with the cell availability status immediately if RANYPHY is logic low. If RANYPHY is logic high, RPA has an additional cycle of latency. RPA will be a one if at least one entire cell is available. RPA is high-impedance when not polled. RPA is updated on the rising edge of RCLK. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 15 ...
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... RENB is held low beyond the end of a cell. When RENB is sampled high or the S/UNI-VORTEX is not selected, no read is performed and outputs RDAT[15:0], RPRTY, RSX and RSOP become high impedance. The RENB input is sampled on the rising edge of RCLK. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 16 ...
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... S/UNI-VORTEX occupies. When the VADR[4:0] inputs match the value sampled on RADR[4:0] inputs, the S/UNI-VORTEX drives RPA to indicate the existence of queued cells. Otherwise, RPA is high impedance. VADR[4:0] are expected to be held static. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 17 ...
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... RSX becomes high impedance (with a cycle latency) upon sampling RENB high or if the S/UNI- VORTEX device is not selected for transfer. When RANYPHY is high, autonomous deselection occurs after the last word of a cell resulting in setting RSX high-impedance until reselection. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 18 ...
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... RANYPHY is logic high. RPRTY becomes high impedance upon sampling RENB high or if the S/UNI-VORTEX device is not selected for transfer. When RANYPHY is high, autonomous deselection occurs after the last word of a cell resulting in setting RPRTY high-impedance until reselection. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 19 ...
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... Control Channel Base Address, Logical Channel Base Address and Logical Channel Address Range / Logical Channel Base Address MSB registers is sampled from the TADR[11:3] inputs. TPA is updated on the rising edge of TCLK. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 20 ...
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... TSX is high, the first word of the cell structure is present on the TDAT[15:0] stream. TSX must be asserted for each cell. An interrupt may be generated if TSX is high during any word other than the expected first word of the cell structure. TSX is sampled on the rising edge of TCLK. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 21 ...
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... RSTB input. The active-low read enable (RDB) signal is low during S/UNI-VORTEX register read accesses. The S/UNI- VORTEX drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 22 ...
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... S/UNI-VORTEX interrupt source is active and that source is unmasked. The S/UNI-VORTEX may be enabled to report many alarms or events via interrupts. INTB becomes high impedance when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output. JTAG Boundary Scan Port PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 23 ...
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... When tied to +5V, the BIAS inputs are used to bias the wells in the input and I/O pads so that the pads can tolerate 5V on their inputs without forward biasing internal ESD protection devices. When tied to +3.3V, the inputs and bi-directional inputs will only tolerate 3.3V level inputs. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 24 ...
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... D20 D18 D15 D12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function A1 The pad ring power (VDD) pins should be connected well-decoupled +3 supply PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 25 ...
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... The pad ring ground (VSS) pins should be connected C2 to GND Quiet Analog Power (QAVD1, QAVD0). QAVD1 and D8 QAVD0 should be connected to analog +3.3 V. Quiet Analog Ground (QAVS1, QAVS0). QAVS1 and C7 QAVS0 should be connected to analog GND. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 26 ...
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... These pins should be connected to analog GND The power (TAVD) pins for the LVDS transmitters. G2 These pins should be connected to analog +3.3V The ground (TAVS) pins for the LVDS transmitters. E3 These pins should be connected to analog GND PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 27 ...
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... VDD must be less than 0.5 V. The relative power sequencing of the multiple AVD power supplies is not important. 3.4 Power down the device in the reverse sequence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 28 ...
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... The traffic manager need only poll those logical channels for which it has downstream cells queued. A cell transfer can be initiated after a polled logical PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 29 ...
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... They exist in the Any-PHY data structure, but are not passed across the high-speed serial interfaces. The contents are ignored. 3. They are passed transparently across the high-speed serial interfaces. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 30 ...
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... Any-PHY interface; only the bus timing and protocols need be respected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 In this case Word 0 is not used and should not PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 31 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Bit 15 Bit 8 Bit 7 Reserved ADDR[13:0] User Prepend PAYLOAD1 PAYLOAD3 PAYLOAD47 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Bit UDF 1 PAYLO AD2 PAYLO AD4 PAYLOAD48 32 ...
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... An encoding of “111110” in ADDR[5:0] indicates the cell is a control channel cell. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 SCI-PHY PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Any-PHY RDAT[15:0], RPRTY, RSOP and RSX are driven or become high ...
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... Description The CA[15:0] bits carry logical channel flow control information in the upstream direction. To support 32 logical channels, the status for each logical channel is sent every other cell; the CASEL indicates PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER self-synchronous ATM Payload ATM Payload 48 bytes ...
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... The PHY identifier determines to which PHY a cell is destined in the downstream direction and from which PHY it came in the upstream direction. It also indicates whether the cell is a stuff or control channel cell. The field is encoded as PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 35 ...
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... The link active bit indicates which of the redundant links is currently chosen. The S/UNI-DUPLEX will switch to the link which contains a one in this location for at least 3 consecutive cells. The line card microprocessor can override this selection. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 36 ...
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... The TREF[5:0] binary value represents the number of high-speed link bytes after this one at which the timing reference is inferred. An all ones value indicates no timing mark is associated with this cell. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 37 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Diagnostic Loopback 33 Cell per-PH Y buffer 6 Cell FIFO 4 Cell FIFO 4 Cell FIFO to all blocks PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER M etallic Loopback TXD 0+ Cell TXD 0- Processor RXD0+ RXD0- TXD 7+ TXD 7- RXD7+ RXD7- ...
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... The receiver can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER ...
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... The Remote Defect Indication (RDI) is sent whenever Loss of Signal (LOS) or Loss of Cell Delineation (LCD) is declared. This code word takes precedence over all others. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 40 ...
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... DELTA cells and the delineation state machine falls back to the HUNT state incorrect HCS is not found in this PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Codeword (left bit transmitted first) 11111111 00000000 ...
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... LVDS links connecting the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 correct HCS (bit by bit) Incorrect HCS (cell by cell) SYNC PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER PRESYNC DELTA consecutive correct HCS's (cell by cell) 42 ...
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... In the upstream direction, the subscribed aggregate bandwidth can exceed that accommodated by the WAN PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 43 ...
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... Otherwise, a simple round robin algorithm is used among the remaining eligible channels to share the downstream link fairly and schedule the next cell to be sent. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 44 ...
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... Upstream queues could congest due to restricted up-link capacity, in which case appropriate congestion management algorithms within the TM device should be invoked. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER . In this case, upstream traffic 1 ...
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... The S/UNI-VORTEX monitors the TREF[5:0] field on the selected upstream LVDS link and initializes an internal counter to the value of TREF[5:0] each time the field is received. The counter decrements with each subsequent byte PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 46 ...
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... The transmitting of control cells across the high-speed serial PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 47 ...
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... LVDS if the corresponding Transmit High-Speed Serial Configuration register and the far- PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER ...
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... Obviously the near and far end must configure their corresponding High-Speed Serial Configuration registers such that the high speed link format is the same at both transmitter and receiver or the receiver will always be out of frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 49 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Bit 7 Bit 0 Unused Unused * User Prepend * User Prepend UDF Unused Unused PAYLOAD1 PAYLO AD48 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 50 ...
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... Master Reset and Identity / Load Performance Meters 0x001 Master Configuration 0x002 Receive Serial Interrupt Status 0x003 Transmit Serial Interrupt Status 0x004 Miscellaneous Interrupt Statuses PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 51 ...
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... Registers associated with RXD5+/- and TXD5+/- 0x13F 0x140 – Registers associated with RXD6+/- and TXD6+/- 0x15F 0x160 – Registers associated with RXD7+/- and TXD7+/- 0x17F PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 52 ...
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... Transmit High-Speed Serial Cell Counter (MSB) 0x015 Serial Link Maintenance 0x016 Reserved 0x017 Transmit Bit Oriented Code 0x018 Bit Oriented Code Receiver Enable PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 where the link index = 0..7 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 53 ...
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... Receive Bit Oriented Code Status 0x01A – Reserved 0x01B 0x01C Upstream Link FIFO Control 0x01D – Reserved 0x01F For all register accesses, CSB must be low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 54 ...
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... To ensure that the S/UNI-VORTEX operates as intended, reserved register bits must only be written with logic zero. Similarly, writing to reserved registers should be avoided. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 55 ...
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... Master Test Register (0x200) is not reset by a software reset. Register 0x200 should be written after a software reset to ensure known state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default RESET 0 TYPE[2] 0 TYPE[1] 1 TYPE[0] 0 ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 56 ...
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... If MINTE is logic 0, INTB is unconditionally high-impedance. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Reserved 0 Unused X MINTE 0 TPAEN 0 ROUTECC 0 RX8KSEL[2] 0 RX8KSEL[1] 0 RX8KSEL[0] 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 57 ...
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... RELEASED DATA SHEET PMC-1980582 Reserved: The Reserved bit should be set be logic 0 for correct operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 58 ...
Page 69
... Receive High-Speed Serial Interrupt Status, Receive High-Speed Serial FIFO Overflow or Receive Bit Oriented Code Status registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default RXI[7] X RXI[6] X RXI[5] X RXI[4] X RXI[3] X RXI[2] X RXI[1] X RXI[0] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 59 ...
Page 70
... Transmit High-Speed Serial Cell Count Status or Downstream Logical Channel FIFO Interrupt Status registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default TXI[7] X TXI[6] X TXI[5] X TXI[4] X TXI[3] X TXI[2] X TXI[1] X TXI[0] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 60 ...
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... This bit is not self-clearing only cleared to logic 0 by reading the Microprocessor Cell Interrupt Status register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X ROOLI X UPCBI X UCIFI X DCIFI X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 61 ...
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... Clock Monitor register has changed state since the last time this register was read. The ROOLI bit is reset when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 62 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default CCBA[10] 0 CCBA[9] 0 CCBA[8] 0 CCBA[7] 0 CCBA[6] 0 CCBA[5] 0 CCBA[4] 0 CCBA[3] 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 63 ...
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... Bit 0 R/W CCBA[11] This is the most significant bit of the Control Channel Base Address. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X CCBA[11] 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 64 ...
Page 75
... REFCLK reference clock input. REFCLKA is set high on a rising edge of REFCLK, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X ROOLE 0 ROOLV X REFCLKA X RCLKA X TCLKA X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 65 ...
Page 76
... When ROOLE and the Master Interrupt Enable bit of the Master Configuration register are set to logic one, and the INTB output is asserted low when the ROOLV bit changes state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 66 ...
Page 77
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default H5UDF 1 Unused X Unused X INADDUDF 0 Reserved 0 PREPEND 0 Unused X PTYP 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 67 ...
Page 78
... When H5UDF is logic 1 (default), the H5 and UDF octets are included, i.e. the optional “Word 4” illustrated in Fig. 3 (p. 32) is included in the data structure expected on TDAT[15:0]. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 68 ...
Page 79
... Cell Interface Interrupt Status register). Reserved: This bit must be logic 0 for correct operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Reserved 0 CELLXFERRE 0 PARERRE 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 69 ...
Page 80
... TDAT[15:0] data bus, an interrupt is generated. The interrupt is reset when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X CELLXFERRI X PARERRI X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 70 ...
Page 81
... H5UDF bit, in that it forces the inclusion of “Word 4”. This bit has no effect if the RANYPHY input is logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default CELLXFERRI X CELLXFERRE 0 Unused X INADDUDF 0 H5UDF 1 Reserved 0 PREPEND 0 PTYP 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 71 ...
Page 82
... This bit does not indicate the case where RENB is held low beyond the end of a cell transfer, when there is not a second cell to transfer. This bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 72 ...
Page 83
... The INSRDYI bit provides a status of the Insert FIFOs Ready Interrupt. This bit is set to logic 1 when one of the Insert FIFOs becomes ready to accept a PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default EXTCRCERRI X EXTRDYI X INSOVRI X INSRDYI X EXTCRCERRE 0 EXTRDYE 0 INSOVRE 0 INSRDYE 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 73 ...
Page 84
... Extract CRC Accumulator register differs from the expected CRC-32 remainder polynomial. Otherwise set to logic 0. This bit is also reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 74 ...
Page 85
... Insert CRC-32 accumulation register is kept to its preset value. If INSCRCPR is set to logic 0, CRC-32 calculations are performed on inserted cells. CRC- PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X INSCRCEND 0 INSCRCPR 1 INSRST X INSFSEL[2] 0 INSFSEL[1] 0 INSFSEL[0] 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 75 ...
Page 86
... CPCS-PDU. Setting this bit to logic 1 will cause the last four bytes of the cell transferred from the microprocessor to be replaced by the value of the ones complement of the Insert CRC-32 Accumulation register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 76 ...
Page 87
... EXTABRT is not readable cleared on every read from normal mode Microprocessor Cell Data register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X EXTCRCCHK 0 EXTCRCPR 1 EXTABRT X EXTFSEL[2] 0 EXTFSEL[1] 0 EXTFSEL[0] 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 77 ...
Page 88
... CRC-32 Accumulation register is equal to the expected CRC-32 remainder polynomial at the end of a cell read access by the microprocessor. If EXTCRCCHK is logic 1, the EXTCRCERRI bit will be set to logic 1 if the CRC-32 is incorrect. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 78 ...
Page 89
... Note that the INSRDY bit for the FIFO currently being written will always return a logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default INSRDY[7] X INSRDY[6] X INSRDY[5] X INSRDY[4] X INSRDY[3] X INSRDY[2] X INSRDY[1] X INSRDY[0] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 79 ...
Page 90
... Note that the EXTRDY bit for the FIFO currently being read will always return a logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default EXTRDY[7] X EXTRDY[6] X EXTRDY[5] X EXTRDY[4] X EXTRDY[3] X EXTRDY[2] X EXTRDY[1] X EXTRDY[0] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 80 ...
Page 91
... Bit 1 R/W Bit 0 R/W PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default INSCRCACC[7] 1 INSCRCACC[6] 1 INSCRCACC[5] 1 INSCRCACC[4] 1 INSCRCACC[3] 1 INSCRCACC[2] 1 INSCRCACC[1] 1 INSCRCACC[0] 1 Function Default INSCRCACC[15] 1 INSCRCACC[14] 1 INSCRCACC[13] 1 INSCRCACC[12] 1 INSCRCACC[11] 1 INSCRCACC[10] 1 INSCRCACC[9] 1 INSCRCACC[8] 1 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 81 ...
Page 92
... REFCLK periods. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default INSCRCACC[23] 1 INSCRCACC[22] 1 INSCRCACC[21] 1 INSCRCACC[20] 1 INSCRCACC[19] 1 INSCRCACC[18] 1 INSCRCACC[17] 1 INSCRCACC[16] 1 Function Default INSCRCACC[31] 1 INSCRCACC[30] 1 INSCRCACC[29] 1 INSCRCACC[28] 1 INSCRCACC[27] 1 INSCRCACC[26] 1 INSCRCACC[25] 1 INSCRCACC[24] 1 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 82 ...
Page 93
... Bit 1 R/W Bit 0 R/W PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default EXTCRCACC[7] 1 EXTCRCACC[6] 1 EXTCRCACC[5] 1 EXTCRCACC[4] 1 EXTCRCACC[3] 1 EXTCRCACC[2] 1 EXTCRCACC[1] 1 EXTCRCACC[0] 1 Function Default EXTCRCACC[15] 1 EXTCRCACC[14] 1 EXTCRCACC[13] 1 EXTCRCACC[12] 1 EXTCRCACC[11] 1 EXTCRCACC[10] 1 EXTCRCACC[9] 1 EXTCRCACC[8] 1 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 83 ...
Page 94
... REFCLK periods. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default EXTCRCACC[23] 1 EXTCRCACC[22] 1 EXTCRCACC[21] 1 EXTCRCACC[20] 1 EXTCRCACC[19] 1 EXTCRCACC[18] 1 EXTCRCACC[17] 1 EXTCRCACC[16] 1 Function Default EXTCRCACC[31] 1 EXTCRCACC[30] 1 EXTCRCACC[29] 1 EXTCRCACC[28] 1 EXTCRCACC[27] 1 EXTCRCACC[26] 1 EXTCRCACC[25] 1 EXTCRCACC[24] 1 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 84 ...
Page 95
... The falling edge of RDB for two successive read accesses to this register must separated by at least three REFCLK periods. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default MCDAT[7] X MCDAT[6] X MCDAT[5] X MCDAT[4] X MCDAT[3] X MCDAT[2] X MCDAT[1] X MCDAT[0] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 85 ...
Page 96
... User Prepend byte is expected to contain the CRC-8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default DDSCR 0 HDSCR 1 Unused X CNTCELLERR 0 CELLCRC 0 PREPEND 0 USRHDR[1] 1 USRHDR[0] 0 Bytes in User Header Reserved PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 86 ...
Page 97
... Cell payload and header descrambling is disabled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload is descrambled. Cell header is left unscrambled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload and header are both descrambled. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER self-synchronous 87 ...
Page 98
... FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X HCSPASS 0 Reserved 0 OCDV X Unused X ACTV X LCDV X LOSV X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 88 ...
Page 99
... Regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states. Reserved: This bit must be logic 0 for correct operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 89 ...
Page 100
... CRC-8 protecting the entire cell. When CELLERRE and CELLCRC are set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X HCSE 0 XFERE 0 OCDE 0 CELLERRE 0 ACTE 0 LCDE 0 LOSE 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 90 ...
Page 101
... HCS error counter holding registers. When XFERE is set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 91 ...
Page 102
... The HCSI bit is set high when a HCS error is detected. This bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default OVR X XFERI X HCSI X OCDI X CELLERRI X ACTI X LCDI X LOSI X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 92 ...
Page 103
... HCS error counter holding registers have been overwritten. OVR is set to logic 0 when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 93 ...
Page 104
... Performance Meters (0x000) register, and remain valid until another transfer is triggered. The count saturates at all ones. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default HCSERR[7] X HCSERR[6] X HCSERR[5] X HCSERR[4] X HCSERR[3] X HCSERR[2] X HCSERR[1] X HCSERR[0] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 94 ...
Page 105
... Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default RCELL[7] X RCELL[6] X RCELL[5] X RCELL[4] X RCELL[3] X RCELL[2] X RCELL[1] X RCELL[0] X Function Default RCELL[15] X RCELL[14] X RCELL[13] X RCELL[12] X RCELL[11] X RCELL[10] X RCELL[9] X RCELL[8] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 95 ...
Page 106
... The count saturates at all ones. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default RCELL[23] X RCELL[22] X RCELL[21] X RCELL[20] X RCELL[19] X RCELL[18] X RCELL[17] X RCELL[16] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 96 ...
Page 107
... Upstream Microprocessor Cell Buffer. This bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X UPFOVRI X FOVRI X Unused X Unused X UPFOVRE 0 FOVRE 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 97 ...
Page 108
... RRW[1: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X RRW[1] 0 RRW[0] 0 Weight PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 98 ...
Page 109
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default LCBA[10] 0 LCBA[9] 0 LCBA[8] 0 LCBA[7] 0 LCBA[6] 0 LCBA[5] 0 LCBA[4] 0 LCBA[3] 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 99 ...
Page 110
... This is the most significant bit of the Logical Channel Base Address for the link. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default LCAR[1] 0 LCAR[0] 0 Unused X Unused X Unused X Unused X Unused X LCBA[11] 0 Addresses Allocated PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 100 ...
Page 111
... When FOVRE and the Master Interrupt Enable bit of the Master Configuration register are set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X FOVRE 0 FIFORST 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 101 ...
Page 112
... TXD+/- bit rate and the TCLK frequency. FOVRI is cleared to logic 0 when the register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X FOVRI X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 102 ...
Page 113
... PHY is all that is connected to the far-end S/UNI-DUPLEX. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X FREADY[5] 1 FREADY[4] 1 FREADY[3] 0 FREADY[2] 0 FREADY[1] 1 FREADY[ REFCLK − TCLK PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 103 ...
Page 114
... User Prepend byte is overwritten by the CRC-8 syndrome for the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default DSCR 0 HSCR 1 Unused X DHCS 0 CELLCRC 0 PREPEND 0 USRHDR[1] 1 USRHDR[0] 0 Bytes in User Header Reserved PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 104 ...
Page 115
... Cell payload and header scrambling is disabled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload is scrambled. Cell header is left unscrambled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload and header are both scrambled. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 105 ...
Page 116
... Master Configuration register are set to logic 1, the INTB output is asserted low if the XFERI bit is a logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default XFERE 0 XFERI X OVR X Unused X Unused X Unused X Unused X Unused X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 106 ...
Page 117
... Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default TCELL[7] X TCELL[6] X TCELL[5] X TCELL[4] X TCELL[3] X TCELL[2] X TCELL[1] X TCELL[0] X Function Default TCELL[15] X TCELL[14] X TCELL[13] X TCELL[12] X TCELL[11] X TCELL[10] X TCELL[9] X TCELL[8] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 107 ...
Page 118
... Registers or to the Load Performance Meters (0x000) register, and remain valid until another transfer is triggered. The count saturates at all ones. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default TCELL[23] X TCELL[22] X TCELL[21] X TCELL[20] X TCELL[19] X TCELL[18] X TCELL[17] X TCELL[16] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 108 ...
Page 119
... TXDIS does not affect the differential output impedance always within the range specified in the D.C. Characteristics section. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Reserved 0 Unused X Unused X RDIDIS 0 TXDIS 0 MLB 0 DLB 0 ACTIVE 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 109 ...
Page 120
... Note that RDI can be sent manually by writing all zeros to the Transmit Bit Oriented Code register. Reserved This bit should be logic 0 for correct operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 110 ...
Page 121
... Remote Defect Indication (RDI) is not currently being transmitted. The default value represents an idle code. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X BC[5] 1 BC[4] 1 BC[3] 1 BC[2] 1 BC[1] 1 BC[0] 1 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 111 ...
Page 122
... When BOCE and the Master Interrupt Enable bit of the Master Configuration register are set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X IDLE 0 AVC 0 BOCE 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 112 ...
Page 123
... BOCI is cleared to logic 0 when the register is read. BOCI will not be set at the transition to a validated IDLE code. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default IDLEI X BOCI X BOC[5] X BOC[4] X BOC[3] X BOC[2] X BOC[1] X BOC[0] X PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 113 ...
Page 124
... This cell will have arrived sometime previously over the LVDS. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Reserved 0 FIFORST 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 114 ...
Page 125
... Reserved: This bit should be logic 0 for correct operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 115 ...
Page 126
... RELEASED DATA SHEET PMC-1980582 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 116 ...
Page 127
... Writable test mode register bits are not initialized upon reset unless otherwise noted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 117 ...
Page 128
... CSB pin low tri-states the data bus. The PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Reserved 0 PMCATST X PMCTST X DBCTRL X IOTST 0 HIZDATA X HIZIO 0 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 118 ...
Page 129
... The LINK_TM[2:0] bits are not cleared by RSTB; therefore, they must be written to prior to testing. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused Unused Unused Unused Unused LINK_TM[2] LINK_TM[1] LINK_TM[0] PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 119 ...
Page 130
... Letting the test run indefinitely simply causes the test sequences to be repeated. A[9:0] 0x007 0x2nE, 0x3mE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Expected D[7:0] xxx0xx11 (Ensures TCLK and RCLK xxxx001x PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER have toggled.) 120 ...
Page 131
... Write 0x03 to 0x2nC, 0x3mC where A… 0,1,2...7 Write 0x02 to 0x2nD, 0x3mD Write 0x55 to 0x2nE, 0x3mE This tests the second port on the RAMs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 121 ...
Page 132
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Selected Instruction Register Codes, IR[2:0] Boundary Scan 000 Identification 001 Boundary Scan 010 Bypass 011 Bypass 100 Boundary Scan 101 Bypass 110 Bypass 111 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 122 ...
Page 133
... ALE OUT_CELL RSTB IN_CELL WRB 1 IN_CELL DOEB IN_CELL D[0] IN_CELL D[1] IN_CELL D[2] IN_CELL D[3] IN_CELL D[4] IN_CELL D[5] IN_CELL D[6] IN_CELL D[7] 5 IN_CELL INTB IN_CELL REFCLK PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Register Cell Bit Type 49 IN_CELL 50 IN_CELL 51 IN_CELL 52 IN_CELL 53 IN_CELL 54 IN_CELL 55 IN_CELL 56 IN_CELL 57 ENABLE 58 OUT_CELL 59 IN_CELL 60 IN_CELL ...
Page 134
... Input Pad SHIFT-DR I.D. Code bit CLOCK-DR Scan Chain In PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE MUX PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Scan Chain Out INPUT to internal logic 124 ...
Page 135
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE MUX MUX Scan Chain Out D MUX C PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Scan Chain O ut OUTPUT or Enable D C INPUT to internal logic G1 1 OUTPUT MUX 1 to pin D C 125 ...
Page 136
... OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Scan Chain Out OUT_CELL IO_CELL Scan Chain In PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER I/O PAD 126 ...
Page 137
... However, there are two scenarios in which the designer may be concerned about the time delay between TPA asserted and the last byte of the cell being written into the buffer: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 127 ...
Page 138
... FREADY has no real effect – that channel’s TPA status will remain deasserted until the entire cell has PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 128 ...
Page 139
... TPA asserted and the bus master starting the next write cycle. FREADY[5:0] should not be set lower than 9 for the reasons discussed previously. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 129 ...
Page 140
... LVDS link even if the bus interfaces are configured to embed the PHY address in the H5/UDF fields . This will slightly increase PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 130 ...
Page 141
... Control cell prepend bytes 2&3 and header bytes 8&9 are undefined at far-end microprocessor THIS CONFIGURATION NOT VALID IF RANYPHY = 1 • 59 byte cells (6 header bytes) are transferred from a 54 byte bus byte bus. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 131 ...
Page 142
... Prepend, PHY address and H5 & UDF bytes are valid. • Control cell prepend bytes 2&3 and header bytes 8&9 are valid at far-end microprocessor. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 132 ...
Page 143
... CRC, 4 header bytes) are transferred from a 54 byte bus byte bus. • At far-end the prepend, PHY address, and H5/UDF fields are all present. Word 0 contains the PHY address, the PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 133 ...
Page 144
... At far-end the H5/UDF fields contains the PHY address. There is no prepend. • Control cell prepend bytes 2 is carried as is. Prepend byte 3 is overwritten with the CRC8. Header bytes 8&9 are undefined. PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 134 ...
Page 145
... TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown in Fig. 8. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 135 ...
Page 146
... Using the boundary scan register, all digital inputs can be PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Boundary Scan Register Device Identification Register Bypass Register Instruction Register and Decode Control Select Tri-state Enable PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Mux DFF TDO 136 ...
Page 147
... The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is illustrated in Fig. 9. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 137 ...
Page 148
... Capture Shift Exit1 Pause Exit2 Update All transitions dependent on input TMS PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 1 Select-IR- Scan 0 1 Capture Shift Exit1 Pause Exit2 Update- ...
Page 149
... The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 139 ...
Page 150
... The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 140 ...
Page 151
... B, switch back to link A, reload the partial CRC and continue with the rest of link A’s packet. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 , each accumulator register can be preset, read and 1 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 141 ...
Page 152
... EXTFSEL bit of the Microprocessor Extract FIFO Control register. 3. Read the header of the cell to determine the end of message and to which virtual channel it belongs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 142 ...
Page 153
... EXTRDY[7:0] bit of an Extract FIFO indicates that the FIFO is ready again to be read from. Setting EXTABRT of the Extract FIFO Control register to logic 1 allows the microprocessor to discard a cell without reading the remaining contents. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 143 ...
Page 154
... Any-PHY compliant slave. The user prepend (W1) is excluded in this example. Note that relative to SCI-PHY mode, all outputs have an additional cycle latency. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 144 ...
Page 155
... The polls of logical channels “C” and “D” illustrate that polls in consecutive cycles are permitted. Once a logic high is returned on TPA in response to a poll, a cell may be transferred as per Fig. 13. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 145 ...
Page 156
... Fig. 13 Downstream Any-PHY Interface Transfer Timing TCLK TENB TSX TDAT[15: TPRTY PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 146 ...
Page 157
... Lead Temperature Absolute Maximum Junction Temperature PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 -40°C to +85°C -40°C to +125°C -0.5V to +6.0V -0. ±1000 V ±100 mA ±20 mA +300°C +150°C PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER +0.5V DD 147 ...
Page 158
... Volts 2.4 3.0 Volts 2.0 V Volts BIAS +0.5 0.8 Volts PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Guaranteed Input LOW Voltage Guaranteed Input HIGH Voltage for RANYPHY, A[8:0], RDB, WRB, CSB, ALE, D[7:0], TDI, TCK and TMS Guaranteed Input HIGH Voltage for TENB, TADR[11:0], TDAT[15:0], TPRTY, TSX, TCLK, RENB, RADR[4:0], RCLK, ...
Page 159
... PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER TTL Schmitt for RSTB and TRSTB =100 Ω ±1% R LOAD =100 Ω ±1% R LOAD =100 Ω ±1% R LOAD When the device is in reset, the differential voltage is approximately 80 mV ...
Page 160
... PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER =100 Ω ±1% R LOAD R =100 Ω ±1% LOAD Drivers shorted to ground Drivers shorted together GND. Notes Notes GND. Notes ...
Page 161
... RELEASED DATA SHEET PMC-1980582 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 151 ...
Page 162
... Valid Read to Valid Data Propagation Delay RD tZ Valid Read Negated to Output Tri-state RD tZ Valid Read Negated to Output Tri-state INTH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 = 3.3 V ±10%) DD PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Min Max Units ...
Page 163
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Valid Address tS tH ALR ALR Valid Data , tV , and tS are not applicable. ALR L LR PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER INTH tZ RD 153 ...
Page 164
... Data to Valid Write Hold Time DW tH Address to Valid Write Hold Time AW tV Valid Write Pulse Width WR PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Min Max Units ...
Page 165
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Valid Address tS tH ALW Valid Data , tV , and tS are not applicable. ALW L LW PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER ALW 155 ...
Page 166
... Symbol Parameter f REFCLK Frequency REFCLK D REFCLK Duty Cycle REFCLK PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 = 3.3 V ±10 RSTB PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Min Max Units 100 ns Min Max Units 12.5 25 MHz 20 80 ...
Page 167
... Fig. 17 Receive SCI-PHY/Any-PHY Interface Timing RCLK RADR[4:0] RENB RDAT[15:0] RPRTY RSOP RSX, RPA PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Min Max Units 0 52 MHz 0.5 ns ...
Page 168
... FALL ODM t V rise time, 20%-80% RISE ODM t Differential Skew SKEW PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 tS TCLK PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Min Max Units 0 52 MHz ...
Page 169
... TDI tH TDI Hold time to TCK TDI t P TCK Low to TDO Valid TDO tV TRSTB Pulse Width TRSTB PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER Min Max Units 4 MHz ...
Page 170
... Volt point of the input to the 1.4 Volt point of the clock. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE TMS TMS tS tH TDI TDI tP TDO tV TRSTB PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 160 ...
Page 171
... Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with load on the outputs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 161 ...
Page 172
... DATA SHEET PMC-1980582 18 ORDERING AND THERMAL INFORMATION PART NO. PM7351-BI PART NO. CASE TEMPERATURE PM7351-BI PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 DESCRIPTION 304 Enhanced Ball Grid Array (SBGA) -40°C to 85°C PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER ...
Page 173
... RELEASED DATA SHEET PMC-1980582 19 MECHANICAL INFORMATION PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER 163 ...
Page 174
... PMC-Sierra, Inc. has been advised of the possibility of such damage. © 2000 PMC-Sierra, Inc. PMC-1980582 (P5) ref PMC-1980170 (P5) PMC-Sierra, Inc. ISSUE 5 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com Issue date: March 2000 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM7351 S/UNI-VORTEX OCTAL SERIAL LINK MULTIPLEXER ...