VSC8111QB Vitesse Semiconductor Corp., VSC8111QB Datasheet

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VSC8111QB

Manufacturer Part Number
VSC8111QB
Description
ATM/SONET/SDH 155/622 Mb/s transceiver mux/demux with integrated clock generation
Manufacturer
Vitesse Semiconductor Corp.
Datasheet

Specifications of VSC8111QB

Case
QFP

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Part Number
Manufacturer
Quantity
Price
Part Number:
VSC8111QB
Manufacturer:
VITESSE
Quantity:
12 388
VSC8111
G52142-0, Rev 4.2
8/31/98
Data Sheet
Features
General Description
unit (PLL) for the high speed clock and 8 bit serial-to-parallel and parallel-to-serial data conversion. The high
speed clock generated by the on-chip PLL is selectable for 155.52 or 622.08 MHz operation. The demultiplexer
contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip-
ment loopback modes and two loop timing modes. The part is packaged in a 100 PQFP with an integrated heat
spreader for optimum thermal performance and reduced cost. The VSC8111 provides an integrated solution for
ATM physical layers and SONET/SDH systems applications.
VSC8111 Block Diagram
TXDATAOUT+/-
TXCLKOUT+/-
RXDA TAIN+/-
The VSC8111 is an ATM/SONET/SDH compatible transceiver integrating an on-chip clock multiplication
RXCLKIN+/-
• Operates at Either STS-3/STM-1 (155.52 Mb/s) or
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 155.52 Mhz
• Dual 8 Bit Parallel TTL Interface
• SONET/SDH Frame Detection and Recovery
EQULOOP
FACLOOP
STS-12/STM-4 (622.08 Mb/s) Data Rates
or 622.08 Mhz High Speed Clock
LOSPOL
LOSTTL
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
0
1
LOS (Internal Signal)
VITESSE
SEMICONDUCTOR CORPORATION
Q
D Q
D
VITESSE SEMICONDUCTOR CORPORATION
1
0
1
0
1
Mux/Demux with Integrated Clock Generation
0
ATM/SONET/SDH 155/622 Mb/s Transceiver
0
1
0
1
• Loss of Signal (LOS) Control
• Provides Equipment, Facilities and Split Loop-
• Meets Bellcore, ITU and ANSI Specifications for
• Single 3.3V Supply Voltage
• Low Power - 1.4 Watts Maximum
• 100 PQFP Package
back Modes as well as Loop Timing Mode
Jitter Performance
Divide-by-8
Divide-by-8
Divide-by-3/12
FRAMER
DEMUX
CMU
MUX
1:8
8:1
D Q
Q D
1
0
8
8
LOS
OOF
FP
RXOUT[7:0]
RXLSCKOUT
TXIN[7:0]
TXLSCKIN
TXLSCKOUT
RX50MCK
LOOPTIM0
REFCLK
LOOPTIM1
EQULOOP
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Related parts for VSC8111QB

VSC8111QB Summary of contents

Page 1

Data Sheet VSC8111 Features • Operates at Either STS-3/STM-1 (155.52 Mb/s) or STS-12/STM-4 (622.08 Mb/s) Data Rates • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 155.52 Mhz or 622.08 Mhz High Speed Clock • ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Functional Description The VSC8111 is designed to provide a SONET/SDH compliant interface between the high speed optical networks and the lower speed User Network Interface (UNI) devices such as the PM5355 ...

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Data Sheet VSC8111 Receive Section High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN inputs. RXDATAIN is clocked in on the rising edge of RXCLKIN+. See Figure 2. The serial data is ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation PLL clock multiplier. The VSC8111 has two TTL inputs LOSTTL and LOSPOL one to force the part into a Loss of Signal state, the other to control the polarity. The LOSTTL ...

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Data Sheet VSC8111 lel to serial conversion of the low speed data (TXIN [7:0]) is selected and converted back to parallel data in the receiver section and presented at the low speed parallel outputs (RXOUT [7:0]). See Figure 4. The ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Loop Timing LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU is bypassed by using the receive clock (RXCLKIN), and the entire part ...

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Data Sheet VSC8111 Clock Multiplier Unit Table 2: Reference Frequency Selection and Output Frequency Control STS12 G52142-0, Rev 4.2 8/31/98 741 Calle Plano, ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Table 3: Clock Multiplier Unit Performance Name RCd Reference clock duty cycle RCj Reference clock jitter (RMS) @ 77.76 MHz ref RCj Reference clock jitter (RMS) @ 51.84 MHz ref RCj ...

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Data Sheet VSC8111 Table 5: Receive High Speed Data Input Timing Table (STS-3 Operation) Parameter T Receive clock period RXCLK T Serial data setup time with respect to RXCLKIN RXSU T Serial data hold time with respect to RXCLKIN RXH ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Figure 9: Receive Data Output Timing Diagram RXCLKIN+ RXCLKIN- RXLSCKOUT RXOUT [7:0] FP Table 8: Receive Data Output Timing Table (STS-12 Operation) Parameter T Receive clock period RXCLKIN T Receive data ...

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Data Sheet VSC8111 Figure 10: Transmit High Speed Data Timing Diagram TXCLKOUT- TXCLKOUT+ TXDATAOUT+ TXDATAOUT- Table 10: Transmit High Speed Data Timing Table (STS-12 Operation) Parameter T Transmit clock period TXCLK Skew between the falling edge of TXCLKOUT+ and T ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation AC Characteristics Table 13: PECL and TTL Outputs Parameters Description T TTL Output Rise Time R,TTL T TTL Output Fall Time F,TTL T PECL Output Rise Time R,PECL T PECL Output ...

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Data Sheet VSC8111 Table 14: PECL and TTL Inputs and Outputs Parameters Description Output LOW V OL voltage (TTL) Input HIGH V IH voltage (TTL) Input LOW V IL voltage (TTL) Input HIGH I IH current (TTL) Input LOW current ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Absolute Maximum Ratings Power Supply Voltage (V ) Potential to GND .................................................................................-0. Input Voltage (PECL inputs) ............................................................................................ -0. Input Voltage (TTL inputs) .........................................................................................................-0.5V to ...

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Data Sheet VSC8111 Package Pin Description Table 16: Pin Definitions Signal Pin FACLOOP 1 VDD 2 N/C 3 RESET 4 LOOPTIM0 VDD 9 TXDATAOUT+ 10 TXDATAOUT- 11 VSS 12 TXCLKOUT+ 13 TXCLKOUT- 14 ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Table 16: Pin Definitions Signal Pin VDD 31 N/C 32 RX50MCK 33 VSS 34 RXOUT0 35 RXOUT1 36 VSS 37 RXOUT2 38 RXOUT3 39 VSS 40 RXOUT4 41 RXOUT5 42 VSS ...

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Data Sheet VSC8111 Table 16: Pin Definitions Signal Pin CP1 63 CN1 64 CN2 65 CP2 66 VDDA 67 VDDA 68 VDDA 69 VSSA 70 VSSA 71 VSS 72 N/C 73 N/C 74 VSS 75 VDD 76 N/C 77 N/C ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Table 16: Pin Definitions Signal Pin N/C 96 STS12 97 N/C 98 VDD 99 EQULOOP 100 Page 18 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR ...

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Data Sheet VSC8111 Package Information PIN 100 PIN 1 RAD 2.92 EXPOSED HEATSINK (NOTE 2) 9.0 X 9.0 (N0TE 2) PIN NOTES: (1) Drawings not to scale. (2) Two styles of exposed heat spreaders may be used; ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation The VSC8111 is manufactured in a 100PQFP package which is supplied by two different vendors. The crit- ical dimensions in the drawing represent the superset of dimensions for both packages. The ...

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... Commercial Temperature ambient case VSC8111QB1 155Mb/s-622Mb/s Mux/Dmux with CMU in 100 Pin PQFP Extended Temperature ambient to 110 C case VSC8111QB2 155Mb/s-622Mb/s Mux/Dmux with CMU in 100 Pin PQFP Industrial Temperature, -40 C ambient case Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore the reader is cautioned to confi ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Application Notes Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN) The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8111 has been brought off-chip to allow as much flexibility in system-level clocking schemes ...

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Data Sheet VSC8111 Important note: The 11 ns max Tpd on the PM5355 assumes a 50pf load @ 60ps/pf, therefore the max delay is due to loading. The VSC8113 input (TXLSCKIN) plus package is about 6pf. Assuming ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Table 18: AC Coupling Component Values Component C1, C2, C3, C4 TTL Input Structure The TTL inputs of the VSC8111 are 3.3V TTL which can accept 5.0V ...

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Data Sheet VSC8111 V +3 INPUT R GND REFCLK and TTL Inputs G52142-0, Rev 4.2 8/31/98 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock ...

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ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation Page 26 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8111 G52142-0, Rev 4.2 8/31/98 ...

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