PM5346-RC PMC-Sierra Inc, PM5346-RC Datasheet
PM5346-RC
Specifications of PM5346-RC
Available stocks
Related parts for PM5346-RC
PM5346-RC Summary of contents
Page 1
... S P TANDARD RODUCT ISSUE 6 ______________________________________________________________________________________________ S/UNI-155-LITE USER NETWORK INTERFACE 155.52 & 51.84 Mbit/s ______________________________________________________________________________________________ PMC-Sierra, Inc. PMC-Sierra, Inc. PM5346 SATURN Issue 6: March, 1996 8501 Commerce Court Burnaby, BC Canada V5A 4N3 604 668 7300 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 2
... Transmit Path Overhead Processor .................................................................... 32 Transmit ATM Cell Processor............................................................................... 34 Drop Side Interface ................................................................................................ 36 Microprocessor Interface....................................................................................... 37 REGISTER MEMORY MAP ............................................................................................ 38 NORMAL MODE REGISTER DESCRIPTION ............................................................. 40 TEST FEATURES DESCRIPTION................................................................................ 99 Test Mode Register Memory Map........................................................................ 99 Register 0x80: Master Test.............................................................................. 100 ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE i ...
Page 3
... Drop Side Transmit Interface................................................................................ 119 ABSOLUTE MAXIMUM RATINGS................................................................................ 121 D.C. CHARACTERISTICS.............................................................................................. 122 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS......................... 125 S/UNI-LITE TIMING CHARACTERISTICS .................................................................. 129 ORDERING AND THERMAL INFORMATION.............................................................. 138 MECHANICAL INFORMATION...................................................................................... 139 128 Pin Copper Leadframe Rectangular PQFP (R Suffix):............................. 139 ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ii ...
Page 4
... Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS), line remote defect indication (RDI), loss of pointer (LOP), path alarm indication signal (AIS), loss of cell delineation and path RDI. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 1 ...
Page 5
... BIP-8/24 codes (B2), line far end block error (FEBE) indications, section BIP-8 codes (B1) to allow performance monitoring at the far end. • Allows forced insertion of all zeros data (after scrambling) or corruption of framing byte or section, line, or path BIP-8 codes for diagnostic purposes. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 2 ...
Page 6
... T1.105, American National Standard for Telecommunications - Digital Hierarchy - Optical Interface Rates and Formats Specifications (SONET), 1991 • ATM Forum 155 Mbit/s Physical Medium Dependent (PMD) Twisted Pair Copper Specification DRAFT (155-C5-UTP-PMD, Rev 0.2) ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 3 ...
Page 7
... RODUCT ISSUE 6 ______________________________________________________________________________________________ APPLICATION EXAMPLES The PM5346 S/UNI-LITE is typically used to implement the core of an ATM User Network Interface by which an ATM terminal is linked to an ATM switching system using SONET/SDH compatible transport. The S/UNI-LITE finds application at either end of terminal to switch links or switch to switch links, both in private network (LAN) and public network (WAN) situations. In this application, the S/UNI-LITE typically interfaces on its line side with a line receiver/equalizer and a line driver ...
Page 8
... Tx ATM Framer & to Cell Overhead Serial Processor Processor Rx Serial Rx ATM Framer & to Cell Overhead Parallel Processor Processor 5 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE TSOC TXPRTY Tx ATM TDAT[7:0] Cell TCA FIFO TWRENB TFCLK RSOC RXPRTY Rx ATM RDAT[7:0] Cell RCA FIFO RRDENB RFCLK ...
Page 9
... ISSUE 6 ______________________________________________________________________________________________ DESCRIPTION The PM5346 S/UNI-LITE Saturn User Network Interface is a monolithic integrated circuit that implements the SONET/SDH processing and ATM mapping functions of a 155 Mbit/s or 51Mbit/s ATM User Network Interface fully compliant with both SONET and SDH requirements and ATM Forum UNI specifications. ...
Page 10
... The S/UNI-LITE is configured, controlled and monitored via a generic 8-bit microprocessor bus interface implemented in low power, +5 Volt CMOS technology. It has TTL and pseudo ECL (PECL) compatible inputs and TTL compatible outputs and is packaged in a 128 pin PQFP package. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 7 ...
Page 11
... RAVD4 RRCLK- RRCLK+ RAVS4 RAVD2 RAVS2 VSS PIN 38 PIN 39 ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE PM5346 S/UNI-LITE Top View 8 PM5346 S/UNI-LITE PIN 103 PIN 102 VSS RSTB CSB VCLK RATE[0] RATE[1] TSOC TXPRTY TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] ...
Page 12
... RXD+ and RXD- inputs. RXDO+/- are squelched (RXDO+ is forced low and RXDO- is forced high) when loss of signal (ALOS+/-) is asserted. 34 The receive differential reference clock inputs 33 (RRCLK+, RRCLK-) contain a jitter-free 19.44 MHz or 6.48 MHz reference clock. 9 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 13
... S/UNI-LITE transmit functions. TRCLK+/- may be left unconnected when S/UNI-LITE loop timing is enabled (using the S/UNI-LITE Master Control Register). 15 The transmit differential data/positive pulse outputs 16 (TXD+, TXD-) contain NRZ encoded data. TXD+/- is updated on the falling edge of TXC+/- 10 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 14
... FIFO. RFCLK must cycle MHz or lower instantaneous rate, but at a high enough rate to avoid FIFO overflow. RRDENB is sampled using the rising edge of RFCLK. RSOC, RDAT[7:0], RXPRTY and RCA are updated on the rising edge of RFCLK 11 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 15
... RDAT[7:0] bus. When RSOC is high, the first octet of the cell is present on the RDAT[7:0] stream. RSOC is updated on the rising edge of RFCLK and is tristated when not valid if the TSEN input is high. RSOC is always driven when TSEN is low, regardless of the level of RRDENB. 12 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 16
... Then the transmit cell data (TDAT[7:0]) bus carries the 90 ATM cell octets that are written to the transmit FIFO. 91 TDAT[7:0] is sampled on the rising edge of TFCLK 92 and is considered valid only when TWRENB is 93 simultaneously asserted PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 17
... TACP FIFO Control register. If the programmed depth is less than four, additional cells may be written after TCA is asserted. TCA is updated on the rising edge of TFCLK. The active polarity of this signal is programmable and defaults to active high. 14 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 18
... The active low chip select (CSB) signal is low during S/UNI-LITE register accesses. If CSB is not required (i.e. register accesses are controlled using the RDB abd WRB signals only), CSB must be connected to an inverted version of the RSTB input. 15 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 19
... The address latch enable (ALE) is active high and latches the address bus A[7:0] when low. When ALE is high, the internal address latches are transparent. It allows the S/UNI-LITE to interface to a multiplexed address/data bus. ALE has an integral pull up resistor. 16 PM5346 S/UNI-LITE ...
Page 20
... The pad ring power (VDDO1 - VDDO5) pins should be 55 connected to a well decoupled + common 73 with VDDI The pad ring ground (VSSO1 - VSSO5) pins should 56 be connected to GND in common with VSSI PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 21
... The power (RAVD2) pin for receive clock and data recovery block active loop filter and oscillator. RAVD2 should be connected to analog +5V. 31 The ground (RAVS1) pin for receive clock and data recovery block reference circuitry. RAVS1 should be connected to analog GND. 18 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 22
... RAVD4 should be connected to analog +5V. 29 The ground (RAVS3) pin for the RXD+/- and ALOS+/- PECL inputs. RAVS3 should be connected to analog GND. 35 The ground (RAVS4) pin for the RRCLK+/- PECL inputs. RAVS4 should be connected to analog GND. 19 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 23
... SONET data signal. The total loop dynamics of the clock recovery PLL yield a jitter tolerance which exceeds the minimum tolerance required for SONET equipment by GR-253-CORE (Figure 2). ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 20 ...
Page 24
... Framer The Framer Block determines the in-frame/out-of-frame status of the STS-3c or STS-1 data stream. Output RALM reflects this status, and is updated with timing aligned to RCLK. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE 10000 100000 1000000 Jitter Freq. (Hz) 21 PM5346 S/UNI-LITE 10000000 ...
Page 25
... The Loss of Frame Block monitors the in-frame / out-of-frame status of the Framer Block. A loss of frame (LOF) is declared when an out-of-frame (OOF) condition persists for 3 ms. To provide for intermittent out-of-frame conditions, the 3 ms timer ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE all zeros patterns is 22 ...
Page 26
... Note, this counter should be polled at least once per second to avoid saturation which in turn may result in missed bit error events. The Error Monitor Block also accumulates line far end block error indications (contained in the Z2 byte similar manner. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 23 ...
Page 27
... FEBEs are detected by extracting the 4-bit FEBE field from the path status byte (G1). The legal range for the 4-bit field is between 0000 and 1000, representing zero to eight errors. Any other value is interpreted as zero errors. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 24 ...
Page 28
... If no HCS errors are detected in this PRESYNC period then the SYNC state is entered. While in the SYNC state, synchronization is maintained until ALPHA consecutive incorrect HCS patterns are detected. In such an event a transition is made back to the HUNT state. The state diagram of the delineation process is shown in figure 3. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 25 ...
Page 29
... Header Pattern' and 'Match Header Mask' registers. Idle or unassigned cell filtering is accomplished by writing ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE correct HCS (byte by byte) Incorrect HCS (cell by cell) SYNC 26 PM5346 S/UNI-LITE PRESYNC DELTA consecutive correct HCS's (cell by cell) ...
Page 30
... PMC-Sierra, Inc. ATM DELINEATION SYNC STATE Apparant Multi-Bit Error (Drop Cell) MODE Single Bit Error (Correct Error and Pass Cell) No Errors Detected DETECTION (Pass Cell) MODE 27 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ALPHA consecutive incorrect HCS's (To HUNT state) Errors Detected (Drop Cell) ...
Page 31
... FIFO overruns are indicated through a maskable interrupt and register bit. The interface provided indicates the start of a cell (RSOC) when data is read from the receive FIFO (using RFCLK) and indicates the cell available status (RCA). ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 28 ...
Page 32
... Activation or deactivation of line AIS insertion is synchronized to frame boundaries. BIP-8 Insert The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1) into the unscrambled data stream. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 29 ...
Page 33
... RDI. Line RDI is inserted by this block when enabled via register control. Line RDI is inserted by transmitting the code 110 (binary) in bit positions 6, 7, and 8 of the K2 byte contained in the STS-3c or STS-1 stream. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 30 ...
Page 34
... B2 K1 (*) (0x00) (0x00) (0x00) D5 (0x00) (0x00) (0x00) D8 (0x00) (0x00) (0x00) D11 (0x00) (0x00) (0x00 (0x00) (0x00) (*) 31 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE (0x01) (0x02) (0x03) F1 (0x00) (0x00) (0x00) D3 (0x00) (0x00) (0x00 (0x00) (0x00) (0x00) K2 (0x00) (0x00) (0x00) ...
Page 35
... A2 C1 (0xF6) (0x28) (0x01 (*) (0x00) (0x00 (0x00) (0x00) (0x00 (0x62) (0x0A) (0x00 (*) (0x00) (0x00 (0x00) (0x00) (0x00 (0x00) (0x00) (0x00) D10 D11 D12 (0x00) (0x00) (0x00 (0x00) (*) (0x00) 32 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ...
Page 36
... Far end block errors may be inserted under register control for diagnostic purposes. SPE Multiplexer The SPE Multiplexer Block multiplexes the payload pointer bytes, the SPE stream, and the path overhead bytes into the STS-3c or STS-1 stream. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 33 ...
Page 37
... The Idle/Unassigned Cell Generator inserts idle or unassigned cells into the cell stream when enabled. Registers are provided to program the GFC, PTI, and CLP fields of the idle cell header and the idle cell payload. An all zeros pattern is ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE J1 (0x00) B3 ...
Page 38
... The latency through the transmit FIFO can be controlled by setting the fill level at which the cell available (TCA) signal is deasserted. Although all four cell buffers are ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 35 ...
Page 39
... External circuitry is notified, using the TCA signal, when a cell may be written to the transmit FIFO. The cell is written to the FIFO as a byte wide stream (along with a bit marking the first byte of the cell) at instantaneous rates MHz. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 36 ...
Page 40
... The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the S/UNI-LITE. The register set is accessed as follows: ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 37 ...
Page 41
... Reserved 0x2C-0x2F Reserved 0x30 RPOP Status/Control 0x31 RPOP Interrupt Status 0x32 RPOP Reserved 0x33 RPOP Interrupt Enable 0x34 RPOP Reserved 0x35 RPOP Reserved 0x36 RPOP Reserved 0x37 RPOP Path Signal Label ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 38 ...
Page 42
... TACP FIFO Configuration 0x64 TACP Transmit Cell Counter (MSB) 0x65 TACP Transmit Cell Counter (MSB) 0x66 TACP Transmit Cell Counter (MSB) 0x67 TACP Configuration 0x68-0x7F Reserved 0x80 S/UNI-LITE Master Test 0x81-0xFF Reserved for Test ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 39 ...
Page 43
... Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-LITE operates as intended, reserved register bits must only be written with logic zero. Similarly, writing to reserved registers should be avoided. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 40 ...
Page 44
... LITE out of reset. Holding the S/UNI-LITE in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. Otherwise the effect of a software reset is equivalent to that of a hardware reset. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 45
... The AUTOLRDI bit determines whether line remote defect indication (RDI) is sent immediately upon detection of an incoming alarm. When AUTOLRDI is set to logic one, line RDI is inserted immediately upon declaration of loss of signal (LOS), loss of frame (LOF) or line AIS. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 46
... AUTOFEBE is set to logic one, one line or path FEBE is inserted for each line or path BIP error event, respectively. When AUTOFEBE is set to logic zero, incoming line or path BIP error events do not generate FEBE events. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 43 ...
Page 47
... The TACP interrupt sources are enabled in the TACP Interrupt Control/Status Register. TROOLI: The TROOLI bit is the transmit reference out of lock interrupt status bit. TROOLI is set high when the TROOLV bit of the S/UNI-LITE Clock Synthesis ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 48
... Status register changes state. RDOOLV is a logic one if the divided down recovered clock frequency not within 244ppm of the RRCLK+/- frequency transitions have occurred on the RXD+/- inputs for more than 80 bit periods. RDOOLI is cleared when this register is read. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 45 ...
Page 49
... The RRCLK active (RRCLKA) bit monitors for low to high transitions on the RRCLK+ and RRCLK- inputs. RRCLKA is set high on a rising edge of RRCLK+, and is set low when this register is read. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 50
... TPOP Pointer Control register. LCDV: The LCDV bit reflects the current loss of cell delineation state. LCDV becomes a logic 1 when an out of cell delineation state has persisted for 4ms ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 51
... The LCDE bit enables the loss of cell delineation (LCD) interrupt. When logic one, the S/UNI-LITE INTB output is asserted when there is a change in the LCD state. When logic zero, the S/UNI-LITE INTB output is not affected by the change in LCD state. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 48 ...
Page 52
... The transmit reference out of lock status indicates the clock synthesis phase locked loop is unable to lock to the reference on TRCLK+/-. TROOLV is a logic one if the divided down synthesized clock frequency not within 244ppm of the TRCLK+/- frequency. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 53
... The RROOLV bit may remain set at logic 1 for several hundred milliseconds after the removal of the power on reset as the CRU PLL locks to the receive reference clock. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 54
... The DDS bit is set to logic one to disable the descrambling of the STS-3c (STM-1) stream. When DDS is a logic zero, descrambling is enabled. Reserved: The reserved bits must be programmed to logic zero for proper operation. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 55
... BIPEI: The BIPEI bit is the section BIP-8 interrupt status bit. BIPEI is set high when a section layer (B1) bit error is detected. This bit is cleared when this register is read. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 56
... Identity / Load Meters register (0x00). Writing to register address 0x00 loads all the error counter registers in the RSOP, RLOP, RPOP and RACP blocks. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default Default PM5346 S/UNI-LITE ...
Page 57
... The DS bit is set to logic one to disable the scrambling of the STS-3c or STS-1 stream. When logic zero, scrambling is enabled. Reserved: The reserved bits must be programmed to logic zero for proper operation. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 58
... BIP-8 byte (B1). When DBIP8 is set to logic one, the B1 byte is inverted. DLOS: The DLOS bit controls the insertion of all zeros in the transmit stream. When DLOS is set to logic one, the transmit stream is forced to 0x00. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 59
... STS-1 and 24 times per frame for STS-3c). Reserved: The reserved bits must be programmed to logic zero for proper operation. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 60
... AIS changes state. BIPEE: The BIPEE bit is an interrupt enable for the line BIP-24 errors. When BIPEE is set to logic one, an interrupt is generated when a line BIP-24 error (B2) is detected. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 61
... S P TANDARD RODUCT ISSUE 6 ______________________________________________________________________________________________ FEBEE: The FEBEE bit is an interrupt enable for the line far end block errors. When FEBE (Z2) is detected. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 58 ...
Page 62
... Line BIP Registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default Default Default PM5346 S/UNI-LITE ...
Page 63
... The error count can also be polled by writing to the S/UNI-LITE Master Reset and Identity / Load Meters register (0x00). Writing to register address 0x00 loads all the error counter registers in the RSOP, RLOP, RPOP, RACP and TACP blocks. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 60 ...
Page 64
... Line FEBE Registers within approximately 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default Default Default PM5346 S/UNI-LITE ...
Page 65
... The error count can also be polled by writing to the S/UNI-LITE Master Reset and Identity / Load Meters register (0x00). Writing to register address 0x00 loads all the error counter registers in the RSOP, RLOP, RPOP, RACP and TACP blocks. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 62 ...
Page 66
... Line RDI is inserted by transmitting the code 110 in bit positions 6, 7, and 8 of the K2 byte of the transmit stream. Reserved: The reserved bits must be programmed to logic zero for proper operation. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 67
... Bit 1 Unused Bit 0 R/W DBIP DBIP24: The DBIP bit controls the insertion of bit errors continuously in the line BIP byte(s) (B2). When DBIP is set to logic one, the B2 byte(s) are inverted. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 68
... PRDI, PAIS,LOP: The PRDI, PAIS, and LOP bits reflect the current state of the corresponding path level alarms. Reserved: The reserved bits must be programmed to logic zero for proper operation. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 69
... The current path signal label can be read from the RPOP Path Signal Label register. These bits (and the interrupt) are cleared when this register is read. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 70
... When written to the PSLE interrupt enable bit position, a change in the path signal label will activate the interrupt output. Reserved: The reserved bits must be programmed to logic zero for proper operation. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 71
... The PSL7 - PSL0 bits contain the path signal label byte (C2). The value in this register is updated to a new path signal label value if the same new value is observed for three consecutive frames. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 72
... Identity / Load Meters register (0x00). Writing to register address 0x00 loads all the error counter registers in the RSOP, RLOP, RPOP, RACP and TACP blocks. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default Default PM5346 S/UNI-LITE ...
Page 73
... Identity / Load Meters register (0x00). Writing to register address 0x00 loads all the error counter registers in the RSOP, RLOP, RPOP, RACP and TACP blocks. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default Default PM5346 S/UNI-LITE ...
Page 74
... BIP-8 results indicates a mismatch. When BLKBIP is set low, BIP-8 errors are accumulated and reported on a bit basis. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 75
... B3 byte is inverted, causing the insertion of eight path BIP-8 errors per frame. When a logic zero is written to this bit position, the B3 byte is transmitted uncorrupted. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 76
... If a legal value (i.e. 0 Pointer Registers, the transmit payload pointer will immediately change to the ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default pointer value 782) is transferred from the Arbitrary 73 PM5346 S/UNI-LITE ...
Page 77
... APTR[9:0] bits of the Arbitrary Pointer Registers are inserted into the H1 and H2 bytes of the transmit stream. At least one corrupted pointer is guaranteed to be sent. If FTPTR is a logic 0, a valid pointer is inserted. Reserved: The reserved bits must be programmed to logic zero for proper operation. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 74 ...
Page 78
... If the FTPTR bit in the Pointer Control register is a logic 1, the current APTR[9:0] value is inserted into the payload pointer bytes (H1 and H2) in the transmit stream. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default pointer value 75 PM5346 S/UNI-LITE 782) results in the ...
Page 79
... PLD bit in the Pointer Control Register) or when new data flag generation is enabled using the NDF bit in the TPOP Pointer Control Register. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 80
... Bit 7 R/W C2[7] Bit 6 R/W C2[6] Bit 5 R/W C2[5] Bit 4 R/W C2[4] Bit 3 R/W C2[3] Bit 2 R/W C2[2] Bit 1 R/W C2[1] Bit 0 R/W C2[0] This register allows control over the path signal label. C2[7], C2[6], C2[5], C2[4], C2[3], C2[2], C2[1], C2[0]: The C2[7:0] bits are inserted in the C2 byte position in the transmit stream. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 81
... PRDI bit position in the path status byte is set low provided AUTORDI is low or no alarms are currently active. G1[2], G1[1], G1[0]: The G1[2:0] bits are inserted in the unused bit positions in the path status byte . ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 82
... The DISCOR bit disables the HCS error correction algorithm. When DISCOR is a logic zero, the error correction algorithm is enabled, and single bit errors detected in the cell header are corrected. When DISCOR is a logic one, the ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 83
... When OOCDV is set low, the cell delineation state machine is in the 'SYNC' state and cells are passed through the receive FIFO. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 80 ...
Page 84
... HCS error. When HCSE is set to logic one, the interrupt is enabled. OOCDE: The OOCDE bit enables the generation of an interrupt due to a change of cell delineation state. When OOCDE is set to logic one, the interrupt is enabled. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 85
... Header Mask Register. CLP: The CLP bit contains the pattern to match in the eighth bit of the fourth octet of the 53 octet cell, in conjunction with the RACP Match Header Mask Register. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 86
... The MPTI[3:0] bits contain the mask pattern for the fifth, sixth and seventh bits of the fourth octet of the 53 octet cell. MCLP: The MCLP bit contains the mask pattern for the eighth bit of the fourth octet of the 53 octet cell. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 87
... Identity / Load Meters register (0x00). Writing to register address 0x00 loads all the error counter registers in the RSOP, RLOP, RPOP, RACP and TACP blocks. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default The contents of these 84 PM5346 S/UNI-LITE ...
Page 88
... The error count can also be polled by writing to the S/UNI-LITE Master Reset and Identity / Load Meters register (0x00). Writing to register address 0x00 loads all the error counter registers in the RSOP, RLOP, RPOP, RACP and TACP blocks. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 89
... The counter should be polled every second to avoid saturating. The contents of these registers are valid 200 ns after a transfer is triggered by a write to the ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default Default Default PM5346 S/UNI-LITE ...
Page 90
... The cell count can also be polled by writing to the S/UNI-LITE Master Reset and Identity / Load Meters register (0x00). Writing to register address 0x00 loads all the error counter registers in the RSOP, RLOP, RPOP, RACP and TACP blocks. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 87 ...
Page 91
... The active high fix stuff control enable bit FSEN selects the expected payload mapping of ATM cells when STS-1 mapping is selected. When FSEN is set to logic one assumed columns 30 and 59 of the Synchronous Payload ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 92
... GFC bit (first bit in the cell RGFCE bit is a logic 1, the RGFC output presents in the appropriate bit location the state of the associated GFC bit in the current cell; otherwise, RFGC is deasserted low. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 89 ...
Page 93
... The FOVRI bit is set high when a FIFO overrun occurs. This bit is reset immediately after a read to this register TSOCI: The TSOCI bit is set high when the TSOC input is sampled high during any ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 94
... The FIFOE bit enables the generation of an interrupt due to a FIFO overrun error condition, or when the TSOC input is sampled high during any position other than the first byte. When FIFOE is set to logic one, the interrupt is enabled. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 91 ...
Page 95
... The CLP bit contains the eighth bit position of the fourth octet of the idle/unassigned cell pattern. Idle cells are transmitted when the TACP detects that no outstanding cells exist in the transmit FIFO. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 96
... Cell rate decoupling is accomplished by transmitting idle/unassigned cells when the TACP detects that no outstanding cells exist in the transmit FIFO. Bit ICP[7] corresponds to the most significant bit of the octet, the first bit transmitted. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default PM5346 S/UNI-LITE ...
Page 97
... FIFO depth to 2 cells. Reserved: The reserved bits must be programmed to logic zero for proper operation. ______________________________________________________________________________________________ PMC-Sierra, Inc. Default FIFODP[1] FIFODP[ PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE FIFO DEPTH 4 cells 3 cells 2 cells 1 cell ...
Page 98
... The TXPTYP bit selects even or odd parity for input TXPRTY. When set to logic one input TXPRTY is the even parity bit for inputs TDAT[7:0]. When set to logic zero, inputs TXPRTY is the odd parity bit for inputs TDAT[7:0]. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 95 ...
Page 99
... A write to any one of the Transmit Cell Counter registers loads the registers with the current counter value and resets the internal 19 bit counter ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default Default Default PM5346 S/UNI-LITE ...
Page 100
... The cell count can also be polled by writing to the S/UNI-LITE Master Reset and Identity / Load Meters register (0x00). Writing to register address 0x00 loads all the error counter registers in the RSOP, RLOP, RPOP, RACP and TACP blocks. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 97 ...
Page 101
... TDAT[7:0] in the case of an assigned cell, or from the Idle/Unassigned Cell Header Control register in the case of unassigned cells. ______________________________________________________________________________________________ PMC-Sierra, Inc. Default FIXBYTE[1] FIXBYTE[ PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE BYTE 00H 55H AAH FFH ...
Page 102
... Reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. Writable test mode register bits are not initialized upon reset unless otherwise noted. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 99 ...
Page 103
... The PMCTST bit is used to configure the S/UNI-LITE for PMC's manufacturing tests. When PMCTST is set to logic one, the S/UNI-LITE microprocessor port becomes the test access port used to run the PMC ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Default 100 PM5346 S/UNI-LITE ...
Page 104
... TGFC XOFF TSOC TSEN RATE[1] RATE[0] Bit 5 Bit 4 Bit 3 2 RALM 1 RCA RCP RGFC RDAT[5] RDAT[4] RDAT[3] 101 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Bit 2 Bit 1 Bit 0 TDAT[2] TDAT[1] TDAT[0] TXPRTY TWRENB TFCLK RBYP Bit 2 Bit 1 Bit 0 2 RFP TFPO 1 RXPRTY ...
Page 105
... S/UNI-LITE are indicated in figures 8 and 9. Fig. 8 STS-3c (STM-1) Overhead TRANSPORT OVERHEAD ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE SOH 102 PM5346 S/UNI-LITE PATH OVERHEAD POH ...
Page 106
... B1 is calculated over all bits of the previous frame after scrambling placed in the current frame before scrambling. Receive B1 errors are accumulated in an error event counter. ______________________________________________________________________________________________ PMC-Sierra, Inc SOH 103 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE PATH OVERHEAD POH ...
Page 107
... Receive B3 errors are accumulated in an error event counter The path signal label byte indicates the content of the SPE. A hexadecimal value transmitted, which indicates "Mapping for ATM." ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 104 ...
Page 108
... Cell Data Structure ATM cells may be passed to/from the S/UNI-LITE using a 9 bit data structure, consisting of a start of cell indication and an 8-bit wide word. The data structure is shown in the figure 10: ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 105 ...
Page 109
... The S/UNI-LITE supports two loopback functions: line loopback, and diagnostic loopback. The diagnostic loopback connects the high speed transmit data and clock ______________________________________________________________________________________________ PMC-Sierra, Inc. Bit 7 Word 1 H1 Word 2 H2 Word 3 H3 Word 4 H4 Word 5 H5 Word 6 PAYLOAD1 Word 53 PAYLOAD48 106 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Bit 0 ...
Page 110
... The line loopback connects the high speed receive data and clock to the transmit data and clock. Diagnostic loopback and line loopback are activated by bits contained in the S/UNI-LITE Master Control Register. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 107 ...
Page 111
... Processor Driver Processor Data Rx Serial Rx ATM Recovery Framer & to Cell Overhead Parallel Processor Processor Clk Rec. Microprocessor DIAGNOSTIC LOOPBACK 108 PM5346 S/UNI-LITE TSOC TXPRTY Tx ATM TDAT[7:0] Cell TCA FIFO TWRENB TFCLK RSOC RXPRTY Rx ATM RDAT[7:0] Cell RCA FIFO RRDENB RFCLK TSEN ...
Page 112
... Connect digital and analog grounds together at only one point close to the connector where ground is brought into the card. ______________________________________________________________________________________________ PMC-Sierra, Inc. R1 Zo=100 C1 R2 109 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE + SUNI-LITE PECL INPUTS - Typical Values 200 R2 = 100 C1 = 10nF ...
Page 113
... ALOS+/- inputs which must be DC coupled because of their low frequency content. The D.C blocking capacitors shown in figure 13 should be ceramic in type. A minumum value recommended. ______________________________________________________________________________________________ PMC-Sierra, Inc. and 50 resistors divides the voltage down to a nominally resistors also terminate the signals. 110 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ). The BB ...
Page 114
... PMC's ATM Design Notes "Meeting SONET/SDH WAN Interface Jitter Transfer Requirements with the S/UNI-LITE", PMC-950139 ______________________________________________________________________________________________ PMC-Sierra, Inc ECL ECL BUFFER BUFFER - - 111 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ECL or PECL Driving SUNI-LITE 10nF Zo=50 RXD+ 330 100 SUNI-LITE 10nF Zo=50 RXD- 330 V EE ...
Page 115
... All resistors are 1% metal film (1/4 watt) resisters. Unpolarized capacitors are recommended. ______________________________________________________________________________________________ PMC-Sierra, Inc. RAVD2 OpAmp LF+ LF- LFO R2 R1 C21 C20 RAVS2 GND 200 412 200 412 112 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE recovered VCO clock R 2 C20, C21 ( ) ( F ) 0.47 2.2 ...
Page 116
... This back-to-back configuration effectively creates a "bi-polar" capacitor. ______________________________________________________________________________________________ PMC-Sierra, Inc. RAVD2 OpAmp LF+ LF- LFO RAVD2 R2 R1 2N3904 C1 min ( F) 68.1 90.9 68.1 90.9 113 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE recovered VCO clock 4.7 100 15 100 ...
Page 117
... The external connections and application for each of the options (A and B) is illustrated in Figure 17. Fig. 16 Conceptual Clocking Structure Internal Tx Clock Source RXD+/- ______________________________________________________________________________________________ PMC-Sierra, Inc. TRCLK+/- Clock Synthesizer Clock Recovery RRCLK+/- 114 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE TCLK Internal Rx Clock Source ...
Page 118
... TRCLK+/- must be jitter free. The source of TRCLK+/- may also be used as the clock recovery reference, RRCLK+/-. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Stratum or 19.44 MHz free-run reference TRCLK+/- SUNI-LITE S/UNI-LITE TCLK RXD+/- RRCLK+/- 115 PM5346 S/UNI-LITE ...
Page 119
... TRCLK+/- inputs are ignored. Normally, the transmit clock is locked to the receive data. In the event of a loss of signal condition, the transmit clock is synthesized from RRCLK+/-. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Stratum or 19.44 MHz free-run reference TRCLK+/- S/UNI-LITE TCLK RXD+/- RRCLK+/- 116 PM5346 S/UNI-LITE ...
Page 120
... W1 W2 W(n-2) W(n-1) XX •••• •••• •••• •••• •••• W(n-5) W(n-4) •••• 117 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE invalid read, no data available W( W(1) W(n-3) W(n-2) W(n-1) W(n) W(1) ...
Page 121
... The Receive GFC Serial Link Diagram (Figure 19) illustrates the operation of the receive generic flow control, RGFC, and receive GFC control pulse, RCP, outputs. The first RGFC bit position, which is coincident with the RCP being high, contains the ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE GFC[2] GFC[1] GFC[0] ...
Page 122
... TCA again. ______________________________________________________________________________________________ PMC-Sierra, Inc. •••• •••• •••• •••• W(n-4) •••• •••• 119 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE W(n-3) W(n-2) W(n-1) W(n) W1 ...
Page 123
... If the insertion is disabled, the default GFC value is inserted. For unassigned cells, the default is the contents of the TACP Idle/Unassigned Cell Header Pattern register. For assigned cells, the default is the value received from TDAT[7:0]. ______________________________________________________________________________________________ PMC-Sierra, Inc. TCP X GFC[3] GFC[2] 120 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE GFC[1] GFC[0] X ...
Page 124
... Storage Temperature Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature Power Dissipation ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE + +125 C -0.5V to +6.0V -0. +0.5V DD 500 V 100 ...
Page 125
... V DD +0.5 AVD AVD -1.0 -0.8 0.6 1.0 0.1 0.4 2.4 4.7 122 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Volts Guaranteed Input LOW Voltage Volts Guaranteed ALOS+, ALOS- Input LOW Voltage referenced to RAVD Volts Guaranteed Input HIGH Voltage Volts Guaranteed ALOS+, ALOS- Input HIGH Voltage referenced to RAVD Volts Input swing assuming ...
Page 126
... A -10 +10 A -10 + 123 PM5346 S/UNI-LITE = min for TXD+, TXD-, TXC+, and TXC-, Note 5 = min for TXD+, TXD-, TXC+, and TXC-, Note GND, Notes Notes GND, Notes 4, 3 ...
Page 127
... TXD-, TXC+, and TXC-. 6. Typical values are not production tested. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE 156 185 mA 85 110 mA V ensure a minimum 600 mV swing at the ECL TXOH 124 PM5346 S/UNI-LITE V = 5.25 V, Outputs DD Unloaded, TXD+/- = RXD+/- =155.52 Mbit/s, TXD+/- = RXD+/- =51.84 Mbit/s, ...
Page 128
... Latch to Read Hold LR tP Valid Read to Valid Data Propagation Delay RD tZ Valid Read Negated to Output Tri-state RD tZ Valid Read Negated to Output Tri-state INTH ______________________________________________________________________________________________ PMC-Sierra, Inc 5 125 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Min Units ...
Page 129
... In non-multiplexed address/data bus architectures, ALE should be held high, parameters ALR ______________________________________________________________________________________________ PMC-Sierra, Inc Valid Address tS ALR and tS are not applicable. ALR L LR 126 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ALR INTH tZ RD Valid Data ...
Page 130
... LW tH Data to Valid Write Hold Time DW tH Address to Valid Write Hold Time AW tV Valid Write Pulse Width WR ______________________________________________________________________________________________ PMC-Sierra, Inc. are not applicable if address latching is used. AR 127 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Min Units ...
Page 131
... Volt point of the input to the 1.4 Volt point of the clock. ______________________________________________________________________________________________ PMC-Sierra, Inc. Valid Address tS tH ALW Valid Data , tV , and tS are not applicable. ALW L LW are not applicable if address latching is used. AW 128 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE ALW ...
Page 132
... RALM t P RCLK High to RFP Valid RFP Fig. 24 Receive Alarm Output Timing RCLK RALM RFP ______________________________________________________________________________________________ PMC-Sierra, Inc 5 † tP RALM tP RFP 129 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Min Units -20 +20 ppm Min Units ...
Page 133
... TXC- High to TXD+ Valid TXDpos † The specification may be relaxed to +/- 50 ppm for LAN applications that do not require this timing accuracy. The specified tolerance is required to meet the SONET free run accuracy specification. ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Min 30 † -20 3 ...
Page 134
... RRDENB t P RFCLK High to RDAT[7:0] Valid RDAT t P RFCLK High to RXPRTY Valid RXP t P RFCLK High to RCA Valid RCA t P RFCLK High to RSOC Valid RSOC ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE tP TFPO tP TXDdiff tP TXDneg tP TXDpos Min ...
Page 135
... S P TANDARD RODUCT ISSUE 6 ______________________________________________________________________________________________ Fig. 26 Drop Side Receive Synchronous Interface Timing (TSEN = 0) RFCLK RRDENB RDAT[7:0] RCA RSOC RXPRTY ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE tS tH RRDENB RRDENB tP RDAT tP RCA tP RSOC tP RXP 132 PM5346 S/UNI-LITE ...
Page 136
... Z RFCLK High to RXPRTY Tristate RXP t P RFCLK High to RCA Valid RCA t P RFCLK High to RSOC Valid RSOC t Z RFCLK High to RSOC Tristate RSOC ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Min 133 ...
Page 137
... S P TANDARD RODUCT ISSUE 6 ______________________________________________________________________________________________ Fig. 27 Drop Side Receive Synchronous Interface Timing (TSEN = 1) RFCLK tS RRDENB RRDENB RDAT[7:0] RCA RSOC RXPRTY ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE tH RRDENB tP RDAT tP RCA tP RSOC tP RXP 134 PM5346 S/UNI-LITE tZ RDAT tZ RSOC tZ RXP ...
Page 138
... H TXPRTY Hold time to TFCLK TXP t S TSOC Set-up time to TFCLK TSOC t H TSOC Hold time to TFCLK TSOC t P TFCLK to TCA Valid TCA ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Min RGFC tP RCP Min ...
Page 139
... S P TANDARD RODUCT ISSUE 6 ______________________________________________________________________________________________ Fig. 29 Drop Side Transmit Synchronous Interface TFCLK TWRENB TDAT[7:0] TSOC TCA TXPRTY ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE tS tH TWRENB TWRENB tS tH TDAT TDAT tS tH TSOC TSOC tP TCA tS tH TXP TXP 136 PM5346 S/UNI-LITE ...
Page 140
... All output propagation delays are measured with load on the outputs. 3. Differential output propagation delay time is the time in nanoseconds from the crossing point of the reference signal to the crossing point of the output. ______________________________________________________________________________________________ PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Min TGFC TGFC tP TCP 137 PM5346 S/UNI-LITE Units ...
Page 141
... S P TANDARD RODUCT ISSUE 6 ______________________________________________________________________________________________ ORDERING AND THERMAL INFORMATION PART NO. PM5346-RC 128 Pin Copper Leadframe Plastic Quad Flat Pack (PQFP) PART NO. AMBIENT TEMPERATURE PM5346-RC ______________________________________________________________________________________________ PMC-Sierra, Inc. DESCRIPTION 138 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE Theta Ja Theta Jc 60 C/W 25 C/W ...
Page 142
... PIN METRIC RECTANGULAR PLASTIC QUAD FLATPACK-MQFP 2 22.95 0.25 2.57 19.90 16.95 2.70 23.20 20.00 17.20 0.53 2.87 23.45 20.10 17.45 139 PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE A A2 NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSIONS SHOWN ARE NOMINAL WITH TOLERANCES AS INDICATED. 3) FOOT LENGTH "L" IS MEASURED AT GAGE PLANE, 0.25 ABOVE SEATING PLANE. C ccc ccc 13.90 0.73 0.17 14.00 0.88 ...
Page 143
... S P TANDARD RODUCT ISSUE 6 ______________________________________________________________________________________________ NOTES ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 140 ...
Page 144
... S P TANDARD RODUCT ISSUE 6 ______________________________________________________________________________________________ NOTES ______________________________________________________________________________________________ PMC-Sierra, Inc. PM5346 S/UNI-LITE SATURN USER NETWORK INTERFACE 141 ...
Page 145
... Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller’s negligence. © 1996 PMC-Sierra, Inc. PMC-931110(R6) ref 931109(R8) ______________________________________________________________________________________________ PMC-Sierra, Inc. PMC-Sierra, Inc. SATURN USER NETWORK INTERFACE Issue date: March, 1996. 8501 Commerce Court Burnaby, BC Canada V5A 4N3 604 668 7300 PM5346 S/UNI-LITE ...