IP82C55A-5 Harris Corporation, IP82C55A-5 Datasheet
IP82C55A-5
Related parts for IP82C55A-5
IP82C55A-5 Summary of contents
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... Enhanced Control Word Read Capability • L7 Process • 2.5mA Drive Capability on All I/O Ports • Low Standby Power (ICCSB .10 A Ordering Information PART NUMBERS 5MHz 8MHz PACKAGE CP82C55A-5 CP82C55A 40 Ld PDIP IP82C55A-5 IP82C55A CS82C55A-5 CS82C55A 44 Ld PLCC IS82C55A-5 IS82C55A CD82C55A-5 CD82C55A 40 Ld ID82C55A-5 ID82C55A ...
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Pin Description PIN SYMBOL NUMBER TYPE GND 7 D0-D7 27-34 I/O RESET A0- PA0-PA7 1-4, 37-40 I/O PB0-PB7 18-25 I/O PC0-PC7 10-17 I/O Functional Diagram +5V POWER SUPPLIES ...
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Functional Description Data Bus Buffer This three-state bi-directional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control ...
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Ports A, B, and C The 82C55A contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to ...
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The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will ...
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Mode 0 (Basic Input) RD INPUT CS, A1, A0 D7-D0 Mode 0 (Basic Output) WR D7-D0 CS, A1, A0 OUTPUT Mode 0 Configurations CONTROL WORD # ...
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Mode 0 Configurations (Continued) CONTROL WORD # 82C55A CONTROL WORD # ...
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Mode 0 Configurations (Continued) CONTROL WORD # 82C55A CONTROL WORD # ...
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STB IBF INTR RD INPUT FROM PERIPHERAL INTR (Interrupt Request) A “high” on this output can be used to interrupt the CPU when and input device is requesting service. INTR is set by the condition: STB is a “one”, IBF ...
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WR OBF INTR ACK OUTPUT RD CONTROL WORD 1 PC6, PC7 1 = INPUT 0 = OUTPUT WR PORT A - (STROBED INPUT) PORT B - ...
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CONTROL WORD 1/0 1/0 1/0 FIGURE 11. MODE CONTROL WORD DATA FROM CPU TO 82C55A WR OBF INTR ACK STB IBF PERIPHERAL BUS RD NOTE: Any sequence where WR occurs ...
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MODE 2 AND MODE 0 (INPUT) CONTROL WORD 1/0 PC2-PC0 1 = INPUT 0 = OUTPUT RD WR MODE 2 AND MODE 1 (OUTPUT) CONTROL WORD D7 D6 ...
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MODE 0 IN PA0 In PA1 In PA2 In PA3 In PA4 In PA5 In PA6 In PA7 In PB0 In PB1 In PB2 In PB3 In PB4 In PB5 In PB6 In PB7 In PC0 In PC1 In PC2 ...
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Reading Port C Status (Figures 15 and 16) In Mode 0, Port C transfers data to or from the peripheral device. When the 82C55A is programmed to function in Modes Port C generates or accepts “hand shaking” ...
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INTERRUPT REQUEST PC3 PA0 R0 PA1 R1 PA2 R2 PA3 R3 DECODED PA4 R4 KEYBOARD PA5 R5 MODE 1 PA6 SHIFT (INPUT) PA7 CONTROL PC4 STROBE PC5 ACK 82C55A PB0 B0 PB1 B1 PB2 B2 BURROUGHS PB3 SELF-SCAN B3 DISPLAY ...
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INTERRUPT REQUEST PC3 PA0 D0 PA1 D1 PA2 D2 FLOPPY DISK PA3 D3 CONTROLLER PA4 D4 PA5 D5 MODE 2 PA6 D6 PA7 D7 PC4 DATA STB PC5 ACK (IN) DATA READY PC7 PC6 ACK (OUT) 82C55A PC2 TRACK “0” ...
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Absolute Maximum Ratings T A Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications V CC SYMBOL PARAMETER READ TIMING (1) tAR Address Stable Before RD (2) tRA Address Stable After RD (3) tRR RD Pulse Width (4) tRD Data Valid From RD (5) tDF Data Float After RD (6) tRV ...
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Timing Waveforms RD INPUT CS, A1, A0 D7-D0 WR D7-D0 tAW (7) CS, A1, A0 OUTPUT STB IBF INTR RD INPUT FROM PERIPHERAL 82C55A tRR (3) tIR (13) tAR (1) tRD (4) FIGURE 25. MODE 0 (BASIC INPUT) tWW (9) ...
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Timing Waveforms (Continued) WR OBF INTR ACK OUTPUT DATA FROM CPU TO 82C55A WR OBF INTR ACK STB IBF PERIPHERAL BUS RD NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF ...
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Timing Waveforms (Continued) A0-A1, CS tAW (7) DATA BUS tDW (10) WR tWW (9) FIGURE 30. WRITE TIMING AC Test Circuit V1 R1 OUTPUT FROM DEVICE UNDER TEST R2 NOTE: Includes STRAY and JIG Capacitance Burn-In Circuits MD82C55A CERDIP F6 ...
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Die Characteristics DIE DIMENSIONS 100 x 19 1mils METALLIZATION: Type: Silicon - Aluminum Å Å Thickness: 11k 1k Metallization Mask Layout RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 82C55A GLASSIVATION: Type: SiO 2 ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.042 (1.07) 0.048 (1.22) 0.056 (1.42) PIN (1) IDENTIFIER 0.050 (1.27 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN VIEW “A” ...
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Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -A- -D- E -B- bbb BASE Q PLANE A -C- SEATING PLANE aaa ccc ...
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Ceramic Leadless Chip Carrier Packages (CLCC) 0.010 -E- 0.007 -H- - ...