UPD75P036CW NEC, UPD75P036CW Datasheet
UPD75P036CW
Available stocks
Related parts for UPD75P036CW
UPD75P036CW Summary of contents
Page 1
... Caution Internal pull-up/pull-down resistors cannot be specified by mask option as for this device. Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on e devices and its recommended applications. The reliability of the EPROM version, PD75P036KG, is not guaranteed when used in mass-produced application sets ...
Page 2
PIN CONFIGURATIONS (Top View) • 64-pin plastic shrink DIP (750 mils) SB1/SI/P03 SB0/SO/P02 SCK/P01 INT4/P00 PPO/P21 PTO0/P20 MAT/P103 MAZ/P102 MAI/P101 MAR/P100 AN3/P113 AN2/P112 AN1/P111 AN0/P110 • 64-pin plastic QFP ( mm) • 64-pin ceramic WQFN P43 P42 P41 ...
Page 3
PIN IDENTIFICATION P00-P03 : Port 0 P10-P13 : Port 1 P20-P23 : Port 2 P30-P33 : Port 3 P40-P43 : Port 4 P50-P53 : Port 5 P60-P63 : Port 6 P70-P73 : Port 7 P80-P83 : Port 8 P90-P93 : ...
Page 4
BASIC INTERVAL TIMER INTBT TIMER PROGRAM TI0/P13 /COUNTER COUNTER PTO0/P20 #0 INTT0 SI/SB1/P03 SERIAL SO/SB0/P02 INTER- FACE SCK/P01 INTCSI INT0/P10 INT1/P11 INTER- RUPT INT2/P12 PROM CONTROL INT4/P00 PROGRAM KR0-KR3/P60-P63 MEMORY KR4-KR7/P70-P73 16256 x 4 BITS WATCH BUZ/P23 TIMER INTW AV ...
Page 5
... PIN FUNCTIONS ... 6 1.1 Port Pins ... 6 1.2 Non-Port Pins ... 8 1.3 Pin Input/Output Circuits ... 10 1.4 Recommended Connection of Unused Pins ... 13 2. MEMORY ... 14 2.1 Differences between PD75P036 and PD75028/75036 ... 14 2.2 Program Memory (ROM) ... 15 2.3 Data Memory (RAM) ... 17 3. WRITING AND VERIFYING PROM (PROGRAM MEMORY) ... 19 3.1 Operation Modes For Writing/Verifying Program Memory ... 19 3.2 Program Memory Write Procedure ... 20 3 ...
Page 6
PIN FUNCTIONS 1.1 Port Pins (1/2) Pin Name Input/Output Alternate Function Function P00 Input INT4 4-bit input port (PORT0). P01 Input/Output SCK Internal pull-up resistors can be specified in P02 Input/Output SO/SB0 3-bit units for the P01 to P03 ...
Page 7
Port Pins (2/2) Pin Name Input/Output Alternate Function Function P60 Input/Output KR0 Programmable 4-bit input/output port P61 KR1 (PORT6). P62 KR2 Internal pull-up resistors can be specified in P63 KR3 4-bit units by software. P70 Input/Output KR4 4-bit input/output ...
Page 8
Non-Port Pins (1/2) Pin Name Input/Output Alternate Function Function TI0 Input P13 External event pulse input pin to timer/event counter PTO0 Input/Output P20 Timer/event counter output pin PCL Input/Output P22 Clock output pin BUZ Input/Output P23 Fixed frequency output ...
Page 9
... Positive power supply pin — — GND potential pin. SS Notes 1. Circles indicate schmitt trigger inputs the V pin is not connected directly to the V PP normally. When Reset 8-bit analog input pin. — Reference voltage input — pin (AV side). DD Reference voltage input — ...
Page 10
Pin Input/Output Circuits The following shows a simplified input/output circuit diagram for each pin of the PD75P036. TYPE A (for TYPE P-ch IN N-ch CMOS-level input buffer TYPE B IN Schmitt-triggerred input with hysteresis ...
Page 11
TYPE P.U.R. P.U.R. P-ch enable data IN/OUT Type D output disable Type B P.U.R. : Pull-Up Resistor TYPE P.U.R. enable output V DD disable (P) P-ch data output N-ch disable output ...
Page 12
TYPE REF+ Reference voltage AV REF- 12 PD75P036 ...
Page 13
... Recommended Connection of Unused Pins Pin Name P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21/PPO P22/PCL P23/BUZ P30/MD0-P33/MD3 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80-P83 P90-P93 P100/MAR P101/MAI P102/MAZ P103/MAT P110/AN0-P113/AN3 AN4-AN7 AV REF+ AV REF– XT1 XT2 V PP PD75P036 Recomended Connecting Method Connect to V ...
Page 14
... CS version (not ES) of the mask ROM version. 14 PD75028 PD75036 Mask ROM 0000H-1F7FH 0000H-3F7FH (8064 x 8 bits) (16256 x 8 bits) 000H-1FFH 000H-3FFH (512 x 4 bits) (1024 x 4 bits) Can be connected by mask option Can be disconnected by mask option Internally connected P33-P30 PD75P036 ...
Page 15
Program Memory (ROM) ··· 16256 words x 8 bits The program memory is a 16256-word x 8-bit PROM and stores programs, table data, etc. The program memory is accessed by referencing the program counter contents. Table data can be ...
Page 16
Figure 2-1. Program Memory Map MBE 0 Internal reset start address (high-order six bits) Internal reset start address (low-order eight bits ...
Page 17
Data Memory (RAM) The data memory consists of a data area and a peripheral hardware area as shown in Figure 2-2. The data memory consists of banks, each consisting of 256 words x 4 bits, and the following memory ...
Page 18
Data area The data area consists of static RAM and is used to store process data and as stack memory when a (subroutine interrupt is executed. Even when CPU operation is stopped in the standby mode, the ...
Page 19
WRITING AND VERIFYING PROM (PROGRAM MEMORY) The program memory incorporated in the PD75P036 is a 16256 x 8-bit electrically writable PROM. The pins as listed in the table given below are used for write and verification of the PROM. ...
Page 20
... Write data write mode. (8) Set program inhibit mode. (9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times 1 ms ...
Page 21
... Program Memory Read Procedure The PD 75P036 program memory contents can be read in the following procedure. Read operation should be performed in the verify mode. (1) Connect the unused pins to V (2) Supply the V and (3) Wait for 10 s. (4) Set program memory address 0 clear mode. ...
Page 22
... Cautions 1. The contents of the program memory may be erased if the PD75P036 is exposed for a long time to direct sunlight or a fluorescent light. To protect the contents from being erased, mask the window with the opaque film. NEC attaches quality-tested opaque film to the UV EPROM products for shipping. ...
Page 23
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A Parameter Symbol Supply voltage Input voltage Output voltage V O Output current, high I OH Note Output current, low I OL Operating ambient temperature ...
Page 24
... Always keep the ground point of the capacitor of the oscillator circuit at the same potential not connect the power source pattern through which a high current flows. DD • Do not extract signals from the oscillation circuit. ...
Page 25
... Always keep the ground point of the capacitor of the oscillator circuit at the same potential not connect the power source pattern through which a high current flows. DD • Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock circuit is influenced by noise more easily than the main system clock oscillation circuit ...
Page 26
DC Characteristics (T = – Parameter Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leakage current, high Input leakage current, low Input leakage current, high Input leakage current, low Internal ...
Page 27
Parameter Symbol Test Conditions Note 1 Supply current I 4.19 MHz DD1 Crystal I oscillator DD2 mode I 32.768 kHz DD3 Crystal I oscillator DD4 I XT1 = 0 V DD5 STOP mode I ...
Page 28
... INTL RESET low-level width t RSL Notes 1. The CPU clock ( ) cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (SCC), and processor clock control register (PCC). The figure on the right is cycle time t supply voltage V characteristics at the DD main system clock. ...
Page 29
SERIAL TRANSFER OPERATION Two-Wire and Three-Wire Serial I/O Modes (SCK: internal clock output) Parameter Symbol Test Conditions SCK cycle time t KCY1 SCK high-, low-level widths t KL1 t KH1 SI setup time (to SCK ) t SIK1 SI hold ...
Page 30
SBI Mode (SCK: internal clock output (master)) Parameter Symbol Test Conditions SCK cycle time t KCY3 SCK high-/low-level widths t KL3 t KH3 SB0, 1 Setup time (to SCK ) t SIK3 SB0, 1 hold time (from SCK ) t ...
Page 31
A/D Converter (T = –40 to +70˚ Parameter Symbol Test conditions Resolution Absolute accuracy Note 1 Conversion time Note 2 t CONV Note 3 Sampling time t SAMP Analog input voltage V IAN Analog supply voltage AV DD ...
Page 32
AC Timing Test Point (excluding X1 and XT1 inputs) 0.8 V 0.2 V Clock Timing X1 Input TI0 Timing XT1 Input TI0 32 0 Test Points 0 1 ...
Page 33
Serial Transfer Timing Three-Wire Serial I/O Mode: SCK SI SO Two-Wire Serial I/O Mode: SCK SB0,1 t KCY1 t t KH1 KL1 t t SIK1 KSI1 Input Data t KSO1 Output Data t KCY2 t t KL2 KH2 t t ...
Page 34
Serial Transfer Timing Bus Release Signal Transfer SCK t KSB SB0,1 Command Signal Transfer SCK SB0,1 Interrupt Input Timing INT0,1,2,4 KR0 - 7 RESET Input Timing RESET 34 t KCY3 KL3,4 KH3 SBL SBK SBH ...
Page 35
Data Memory STOP Mode: Low-voltage Data Retention Characteristics (T Parameter Symbol Test Conditions Data retention supply voltage V DDDR Data retention supply I DDDR current Note 1 Release signal set time t SREL Oscillation stabilization wait t WAIT time Note ...
Page 36
... MD3 hold time (from MD0 ) Data output float delay time from MD3 Notes 1. These symbols are correspond to PD27C256A symbols. 2. The internal address signal is incremented the rising edge of fourth X1 input. The internal address is not connected to any pin 6.0 ...
Page 37
Program Memory Write Timing t V VPS VDS P40-P43 Data input P50-P53 MD0 t PW MD1 ...
Page 38
CHARACTERISTIC CURVES (REFERENCE VALUES (4.19-MHz Main System Clock, Crystal Resonator 5.0 3.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 XT1 Crystal resonator 4.19 MHz ...
Page 39
(2.0-MHz Main System Clock, Crystal Resonator 5.0 3.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 0 2 Supply Voltage V PD75P036 ( °C) A PCC = 0011 PCC = 0010 PCC = 0000 ...
Page 40
(4.19-MHz Main System Clock, Ceramic Resonator 5.0 3.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 XT1 Ceramic resonator 4.19 MHz Supply Voltage V ...
Page 41
(20-MHz Main System Clock, Ceramic Resonator 5.0 3.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 0 2 Supply Voltage °C) A PCC = 0011 PCC = 0010 PCC = 0000 Main ...
Page 42
[MHz ...
Page 43
(Ports 25° 2.7 V ...
Page 44
PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" ...
Page 45
PIN PLASTIC QFP ( 14 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition ...
Page 46
PIN CERAMIC WQFN NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition ...
Page 47
... It is recommended that the PD75P036 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. Table 7-1. Soldering Conditions for Surface Mount Devices ...
Page 48
... EV-9200GC-64 EV-9200G-80 used for PD75P036GC/75P036KG PG-1500 PROM programmer PA-75P036CW PROM programmer adapter used for PD75P036CW connected to PG-1500. PA-75P036GC PROM programmer adapter used for PD75P036GC connected to PG-1500. Software IE control program Host machine PG-1500 controller • PC-9800 series (MS-DOS RA75X relocatable • ...
Page 49
APPENDIX B. RELATED DOCUMENTS Please use this document in conjunction with the following. Related document may be "Preliminary." However, in this document, "Preliminary" is not indicated. Device Document Title PD75P036 Data Sheet (This document) PD75028 User's Manual PD75028 Instruction List ...
Page 50
... Title Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer-Related Product Guide — Third Party Products Caution The contents of the documents listed above are subject to change without prior notice to user's. ...
Page 51
... Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices ...
Page 52
... Aircrafts, aerospace equipment, submersible repeaters, nucleare reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance ...