M5M44260CTP-7 MITSUBISHI, M5M44260CTP-7 Datasheet

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M5M44260CTP-7

Manufacturer Part Number
M5M44260CTP-7
Description
Fast page mode 4194304 (262144-word by 16-bit) dynamic RAM
Manufacturer
MITSUBISHI
Datasheet

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1
M5M44260CJ,TP-5,-5S : Under development
DESCRIPTION
Microcomputer memory, Refresh memory for CRT
FEATURES
PIN DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs,
fabricated with the high performance CMOS process, and is ideal
for memory systems where high speed, low power dissipation, and
low costs are essential.
single-transistor dynamic storage stacked capacitor cell provide
high circuit density at reduced costs. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is small enough for
battery back-up application.
512 cycles every 8.2ms.
XX=J,TP
APPLICATION
The use of double-layer metalization process technology and a
Standard 40pin SOJ, 44 pin TSOP (II)
Single 5V±10% supply
Low stand-by power dissipation
Operating power dissipation
Self refresh capability *
Extended refresh capability
Fast-page mode (512-column random access), Read-modify-write,
RAS-only refresh, CAS before RAS refresh, Hidden refresh
capabilities.
Early-write mode, LCAS / UCAS and OE to control output buffer
impedance
512 refresh cycles every 8.2ms (A
512 refresh cycles every 128ms (A
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S
This device has 2CAS and 1W terminals with a refresh cycle of
M5M44260CXX-5,-5S
M5M44260CXX-6,-6S
M5M44260CXX-7,-7S
DQ
RAS
LCAS
UCAS
W
OE
V
A
V
Pin name
CC
0
SS
: option) only
Type name
CMOS Input level
CMOS Input level
M5M44260Cxx-5,-5S
M5M44260Cxx-6,-6S
M5M44260Cxx-7,-7S
Self refresh current
Extended refresh current
~A
1
~DQ
8
16
Lower byte control
Address inputs
Data inputs / outputs
Row address strobe input
column address strobe input
Upper byte control
Write control input
Output enable input
Power supply (+5V)
Ground (0V)
column address strobe input
(max.ns)
access
RAS
time
70
50
60
Function
(max.ns)
access
CAS
time
13
15
20
0
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Address
(max.ns)
0
~A
access
~A
time
25
30
35
8
8
)
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
) *
(max.ns)
access
time
13
15
20
OE
(min.ns)
550µW (Max) *
Cycle
110
130
688mW (Max)
605mW (Max)
523mW (Max)
time
5.5mW (Max)
150µA (Max)
150µA (Max)
90
M5M44260CJ,TP-5,-6,-7,
(typ.mW)
dissipa-
Power
625
550
475
tion
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
PIN CONFIGURATION (TOP VIEW)
Outline 44P3W-R (400mil TSOP Nomal Bend)
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
(5V)V
RAS
DQ4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RAS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Outline 40P0K (400mil SOJ)
NC
NC
NC
NC
NC
NC
CC
CC
CC
CC
CC
CC
A
A
A
A
A
A
A
A
W
W
1
2
3
4
5
6
7
8
0
1
2
3
1
2
3
5
6
7
8
0
1
2
3
10
11
12
13
14
15
16
17
18
19
20
10
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
-5S,-6S,-7S
MITSUBISHI LSIs
25
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
44
43
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
23
MITSUBISHI LSIs
NC: NO CONNECTION
V
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
A
A
A
A
A
V
V
V
A
A
A
A
A
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
LCAS
UCAS
OE
SS
SS
8
7
6
5
4
SS
SS
8
7
6
5
4
SS
SS
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
(0V)
(0V)
(0V)
(0V)
(0V)
(0V)

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M5M44260CTP-7 Summary of contents

Page 1

... MITSUBISHI LSIs MITSUBISHI LSIs -5S,-6S,-7S V (5V ...

Page 2

... DNC DNC DNC CLOCK GENERATOR CIRCUIT COLUMN DECODER SENSE REFRESH AMPLIFIER & CONTROL MEMORY CELL ROW (4194304 BITS) DECODER A 8 MITSUBISHI LSIs Input/Output Refresh Remark Row Column 1 9 address DQ DQ address 8 16 APD APD D OPN OUT ...

Page 3

... V 0.8 V (Note 2) Limits Typ Min 2 5.5V -10 OUT -10 , output open -0.5V IH 0.2V or CAS V -0. -0.2V CC -0. -0. -0.2V ~1µs RAS min MITSUBISHI LSIs Unit ˚C ˚C Unit Max 0.4 V µA 10 µA 10 125 110 1.0 mA 0.1 * 125 110 mA 95 125 110 mA ...

Page 4

... Typ Limits M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Min Max Min Max Min ±10 µA ) and is not reference to V OUT MITSUBISHI LSIs Unit Max Unit Max ...

Page 5

... RCD RCD(max and RAD RAD(max) ASC and RCD RCD(max) ASC and V . IL(max) Parameter M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S (Note 21) (Note 21) MITSUBISHI LSIs Limits Min Max Min Max Min 8.2 8.2 128 128 ...

Page 6

... DQ pins WCS WCS(min and RWD RWD(min) AWD AWD(min) CPWD ) is indeterminate. IH MITSUBISHI LSIs Unit Max ns ns 10000 ns 10000 Unit Max ns ns 10000 10000 ...

Page 7

... Parameter Min 35 71 (Note 25) 85 (Note 26) 30 (Note 23) 48 (Note 27) M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Parameter Min 10 20 M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Parameter Min 100 90 -50 MITSUBISHI LSIs (Note 24) Limits Max Min Max Min 100 100000 100000 115 100000 ...

Page 8

... RPC RSH t CAS t RAL t RRH t RCH t CDD Hi-Z t CAC t OFF DATA VALID t OEZ t OEA t ODD t OCH t ORH Indicates the don't care input IH(min) IN IH(max) IL(min) IN Indicates the invalid output. MITSUBISHI LSIs CRP t ASR ROW ADDRESS Hi-Z V IL(max) ...

Page 9

... FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t RAD RAH ASC CAH ROW COLUMN ADDRESS t RCS t DZC t CAC CLZ Hi-Z t RAC t DZO MITSUBISHI LSIs RSH t RPC t CAS t CPN t RAL t RRH t RCH Hi-Z t CDD Hi-Z t OFF DATA VALID t OEZ t OEA t ODD t ...

Page 10

... M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM RAS t CSH t RCD t CAS t CAH t ASC COLUMN ADDRESS t t WCS WCH DATA VALID MITSUBISHI LSIs RPC t RSH t CPN t ASR Hi-Z t CRP ROW ADDRESS ...

Page 11

... IL 11 M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t t RAH CAH t ASC COLUMN ROW ADDRESS t WCS t Hi DATA VALID Hi RPC t RSH t CAS t CPN WCH MITSUBISHI LSIs CRP t ASR ROW ADDRESS ...

Page 12

... M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t t RAH CAH t ASC ROW COLUMN ADDRESS t RCS t DZC Hi-Z t CLZ Hi-Z t DZO MITSUBISHI LSIs RPC t RSH t CPN t CAS t CWL t RWL WCH DATA VALID Hi-Z t ...

Page 13

... FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t CSH t RCD t t CAH RAH t ASC ROW COLUMN ADDRESS t RCS Hi-Z t DZC Hi-Z t CLZ Hi OEZ DZO MITSUBISHI LSIs RPC t RSH t CAS t CPN t CWL t RWL WCH DATA VALID Hi-Z t OEH ...

Page 14

... RAH CAH t ASC ROW COLUMN ADDRESS ADDRESS t AWD t CWD t RCS t RWD t DZC Hi-Z t CAC CLZ Hi-Z DATA VALID t RAC t t DZO OEA MITSUBISHI LSIs t RWC RPC t RSH t CAS t CWL t RWL DATA VALID Hi-Z t ODD t OEH t OEZ t CRP t ASR ROW ...

Page 15

... CAH RAH t ASC ROW COLUMN ADDRESS ADDRESS t AWD t CWD t RCS t RWD Hi-Z t DZC Hi-Z t CAC CLZ Hi-Z DATA VALID t RAC t t DZO OEA MITSUBISHI LSIs t RWC RPC t RSH t CAS t CPN t CWL t RWL DATA VALID Hi-Z t ODD t OEH t OEZ t CRP t ASR ...

Page 16

... ADDRESS ~ (INPUTS ~ (OUTPUTS M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RAS t RAH Hi-Z MITSUBISHI LSIs RPC t CRP t ASR ROW ADDRESS ...

Page 17

... OEZ t ODD M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM RAS t t CSR RPC t CHR MITSUBISHI LSIs RAS RP t CRP t t CHR RPC t ASR ROW ADDRESS Hi-Z COLUMN ADDRESS t RCS ...

Page 18

... COLUMN ADDRESS t RCS t RAL t DZC t CAC CLZ Hi-Z t RAC t t DZO OEA t ORH Timing requirements and output state are the same as that of each cycle described above. MITSUBISHI LSIs RAS t CHR t RRH t CDD Hi-Z t OFF DATA VALID t OEZ ASR ROW ...

Page 19

... CAH t ASC COLUMN ADDRESS1 t RCS t RCH t DZC Hi-Z t CAC OFF t CLZ DATA VALID-1 t RAC t t OEA DZO t t OCH t ODD MITSUBISHI LSIs RSH CAS CP CAS t CPRH ASC CAH CAH COLUMN COLUMN ADDRESS2 ADDRESS3 t RAL t RCS t t RCH RCS t t ...

Page 20

... ADDRESS2 t t RCS t RCH Hi-Z t DZC t DZC Hi-Z t CAC OFF t CLZ DATA VALID-1 t RAC t t DZO OEA t t OCH t ODD MITSUBISHI LSIs t t RSH CAS CP CAS t CPRH t t CAH t CAH ASC COLUMN COLUMN ADDRESS3 t RAL RCS t t RCH RCS t DZC Hi-Z t ...

Page 21

... FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t CSH t t RCD CAS t t CAH t ASC RAH ROW COLUMN ADDRESS1 t t WCS WCH DATA VALID-1 Hi-Z MITSUBISHI LSIs t RAS RSH CAS t CAS ASC CAH t ASC CAH COLUMN COLUMN ADDRESS2 ADDRESS3 ...

Page 22

... WCS DATA VALID-1 t RAS RSH CAS CAS t t ASC ASC t t CAH CAH COLUMN COLUMN ADDRESS2 ADDRESS3 WCS t WCH WCS WCH Hi DATA DATA VALID-2 VALID-3 Hi-Z MITSUBISHI LSIs ASR ROW ADDRESS ...

Page 23

... CLZ Hi-Z t OEZ t DZO t ODD t RAS t RSH CAS t RWL t ASC t t CWL CAH COLUMN ADDRESS2 t CWL t RCS WCH t DZC Hi-Z DATA DATA VALID-1 VALID-2 t CLZ Hi-Z t OEZ ODD DZO MITSUBISHI LSIs ASR ROW ADDRESS Hi-Z OEH ...

Page 24

... RAS t CSH t t RCD CAS t ASC t CAH COLUMN ADDRESS1 t CWL t RCS t WCH Hi-Z t DZC t DS Hi-Z DATA VALID-1 t CLZ Hi-Z t OEZ t DZO t ODD MITSUBISHI LSIs t RSH CAS t RWL t ASC t t CAH CWL COLUMN ADDRESS2 t RCS WCH t t DZC Hi-Z ...

Page 25

... COLUMN ADDRESS1 t AWD t t CWD RCS t RWD t DZC t DS Hi-Z t CAC CLZ Hi-Z DATA VALID-1 t RAC t ODD t t OEA DZO t OEZ MITSUBISHI LSIs t RAS t PRWC CAS ASC CWL CAH COLUMN ADDRESS2 t AWD t CWL t RCS t CWD CPWD DZC DH DS ...

Page 26

... COLUMN ADDRESS1 t AWD t t CWD RCS t RWD DZC Hi-Z t CAC CLZ Hi-Z DATA VALID-1 t RAC t ODD t t OEA DZO t OEZ MITSUBISHI LSIs t RAS t PRWC t t CAS ASC CAH CWL COLUMN ADDRESS2 t AWD t CWL t CWD t t RCS CPWD Hi ...

Page 27

... OFF ~ (OUTPUTS OEZ t ODD M5M44260CJ,TP-5,-5S : Under development M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM t RASS t CSR MITSUBISHI LSIs t RPS t RPC t t CHS CRP t ASR ROW ADDRESS Hi-Z COLUMN ADDRESS t RCS ...

Page 28

... Switching from self refresh operation to read/write operation. The time interval t the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16µs. MITSUBISHI LSIs Read / Write Cycle t SND first refresh cycle ...

Page 29

... Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within t (shown in table 3). SNB MITSUBISHI LSIs ...

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