MC14071BFEL

Manufacturer Part NumberMC14071BFEL
DescriptionB-Suffix Series CMOS Gates
ManufacturerON Semiconductor
MC14071BFEL datasheet
 


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MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
Pin–for–Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
MAXIMUM RATINGS
(Voltages Referenced to V
Symbol
Parameter
V
DC Supply Voltage Range
DD
V
, V
Input or Output Voltage Range
in
out
(DC or Transient)
I
, I
Input or Output Current
in
out
(DC or Transient) per Pin
P
Power Dissipation,
D
per Package (Note 2.)
T
Ambient Temperature Range
A
T
Storage Temperature Range
stg
T
Lead Temperature
L
(8–Second Soldering)
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
v
v
to the range V
(V
or V
)
V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
or V
). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 1
) (Note 1.)
SS
Value
Unit
– 0.5 to +18.0
V
– 0.5 to V
+ 0.5
V
DD
10
mA
500
mW
– 55 to +125
C
– 65 to +150
C
260
C
Device
MC14001B
MC14011B
MC14023B
and V
should be constrained
in
out
MC14025B
MC14071B
MC14073B
MC14081B
MC14082B
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
1
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP–14
MC140XXBCP
P SUFFIX
AWLYYWW
CASE 646
1
14
SOIC–14
140XXB
D SUFFIX
AWLYWW
CASE 751A
1
14
TSSOP–14
14
DT SUFFIX
0XXB
CASE 948G
ALYW
1
14
SOEIAJ–14
MC140XXB
F SUFFIX
AWLYWW
CASE 965
1
XX
= Specific Device Code
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
DEVICE INFORMATION
Description
Quad 2–Input NOR Gate
Quad 2–Input NAND Gate
Triple 3–Input NAND Gate
Triple 3–Input NOR Gate
Quad 2–Input OR Gate
Triple 3–Input AND Gate
Quad 2–Input AND Gate
Dual 4–Input AND Gate
ORDERING INFORMATION
Publication Order Number:
MC14001B/D

MC14071BFEL Summary of contents