UDA1334BTS Philips Semiconductors, UDA1334BTS Datasheet
UDA1334BTS
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UDA1334BTS Summary of contents
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... DATA SHEET UDA1334BTS Low power audio DAC Preliminary specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2000 Feb 07 ...
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... AC CHARACTERISTICS 14.1 2.0 V supply voltage 14.2 3.0 V supply voltage 14.3 Timing 15 APPLICATION INFORMATION 16 PACKAGE OUTLINE 17 SOLDERING 17.1 Introduction to soldering surface mount packages 17.2 Reflow soldering 17.3 Wave soldering 17.4 Manual soldering 17.5 Suitability of surface mount IC packages for wave and reflow soldering methods 18 DEFINITIONS 19 LIFE SUPPORT APPLICATIONS 2 Preliminary specification UDA1334BTS ...
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... GENERAL DESCRIPTION The UDA1334BTS supports the I word lengths bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits. The UDA1334BTS has basic features such as de-emphasis (at 44.1 kHz sampling rate) and mute. PACKAGE DESCRIPTION plastic shrink small outline package; 16 leads; body width 4 Preliminary specifi ...
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... A-weighted 44.1 kHz; code = 0; A-weighted kHz; code = 0; A-weighted s playback mode at 2.0 V supply voltage at 3.0 V supply voltage Sleep mode; at 2.0 V supply voltage clock running no clock running 4 Preliminary specification UDA1334BTS MIN. TYP. MAX. UNIT 1.8 2.0 3.6 V 1.8 2.0 3.6 V 2.3 mA 125 A 1.4 mA 250 ...
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... BCK DATAI UDA1334BTS 6 SYSCLK 8 MUTE 9 DEEM 10 PCS 14 VOUTL 2000 Feb 07 V DDD 4 DIGITAL INTERFACE DE-EMPHASIS INTERPOLATION FILTER NOISE SHAPER DAC DDA V SSA Fig.1 Block diagram. 5 Preliminary specification UDA1334BTS V SSD 5 7 SFOR1 11 SFOR0 16 DAC VOUTR 12 MGL964 V ref(DAC) ...
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... DAC output left DAC analog ground DAC output right BCK 1 16 VOUTR SSA DATAI 3 14 VOUTL V DDD DDA UDA1334BTS V SSD V ref(DAC SYSCLK 6 11 SFOR0 SFOR1 7 10 PCS MUTE 8 9 DEEM MGL963 Fig.2 Pin configuration. 6 Preliminary specification UDA1334BTS DESCRIPTION ...
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... Low power audio DAC 8 FUNCTIONAL DESCRIPTION 8.1 System clock The UDA1334BTS operates in slave mode only; this means that in all applications the system must provide the system clock and the digital audio interface signals (BCK and WS). The system clock must be locked in frequency to the digital interface signals ...
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... UDA1334BTS Fig.3 Power-on reset circuit. 2000 Feb 07 8.5 The UDA1334BTS has an internal Power-on reset circuit (see Fig.3) which resets the test control block. The reset time (see Fig.4) is determined by an external capacitor which is connected between pin V ground. The reset time should be at least 1 s for ...
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... Philips Semiconductors Low power audio DAC 8.6 Feature settings The features of the UDA1334BTS can be set by control pins SFOR1, SFOR0, MUTE, DEEM and PCS. 8.6.1 D IGITAL INTERFACE FORMAT SELECT The digital audio interface formats (see Fig.5) can be selected via the pins SFOR1 and SFOR0 as shown in Table 4 ...
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Acrobat reader. white to force landscape pages to be ... WS LEFT BCK DATA MSB B2 MSB 2 ...
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... DDA CONDITIONS = all voltages with respect to ground (pins V L CONDITIONS 1.8 note 1 1.8 at 2.0 V supply voltage at 3.0 V supply voltage Sleep mode at 2.0 V supply voltage at 3.0 V supply voltage 11 Preliminary specification UDA1334BTS MIN. MAX. 4.0 150 65 +125 40 +85 2000 +2000 200 +200 450 SSA ...
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... V supply voltage 1.3 at 3.0 V supply voltage 2.0 at 2.0 V supply voltage 0.5 at 3.0 V supply voltage 0.5 0.9V 0.4V 0.5 with respect to V 0.45V SSA (THD + N)/S < 0.1 800 L 3 note 3 12 Preliminary specification UDA1334BTS TYP. MAX. 1.4 2.1 250 20 375 30 3.3 5.0 +0.5 +0 0.5 DDD DDD 0.6V DDD DDD +0.5 0.5V ...
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... A-weighted kHz kHz dB; A-weighted 44.1 kHz; code = 0; A-weighted kHz; code = 0; A-weighted kHz; V ripple ripple 13 Preliminary specification UDA1334BTS MIN. TYP. 600 0 100 = 30 mV (p-p) 60 MIN. TYP. 900 0 ...
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... MHz sys f 19.2 MHz sys f < 19.2 MHz sys f 19.2 MHz sys = 44.1 kHz (sampling frequency Preliminary specification UDA1334BTS and V SSA SSD MIN. TYP. MAX. UNIT 35 88 780 520 390 ns 0.3T 0.7T ns sys sys 0.4T ...
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... Low power audio DAC t CWH handbook, full pagewidth handbook, full pagewidth WS t BCKH t r BCK T cy(BCK) DATAI 2000 Feb 07 t CWL T sys Fig.6 System clock timing. t h(WS) t su(WS BCKL Fig.7 Serial interface timing. 15 Preliminary specification UDA1334BTS MGR984 t su(DATAI) t h(DATAI) MGL880 ...
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... V) ( SSA V DDA V SSD V DDD UDA1334BTS Fig.8 Typical application diagram. 16 Preliminary specification UDA1334BTS VOUTL 14 100 ( 220 k ( VOUTR 16 100 ( ...
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... IEC SOT369-1 2000 Feb 2.5 scale (1) ( 0.32 0.25 5.30 4.5 6.6 0.65 0.20 0.13 5.10 4.3 6.2 REFERENCES JEDEC EIAJ MO-152 17 Preliminary specification UDA1334BTS detail 0.75 0.65 1.0 0.2 0.13 0.45 0.45 EUROPEAN PROJECTION SOT369 ( 0.48 10 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 18 Preliminary specification UDA1334BTS ...
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... Philips for any damages resulting from such improper use or sale. 2000 Feb 07 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 19 Preliminary specification UDA1334BTS (1) REFLOW suitable suitable suitable suitable suitable ...
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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...